JPH0382129A - Semiconductor chip - Google Patents
Semiconductor chipInfo
- Publication number
- JPH0382129A JPH0382129A JP21729789A JP21729789A JPH0382129A JP H0382129 A JPH0382129 A JP H0382129A JP 21729789 A JP21729789 A JP 21729789A JP 21729789 A JP21729789 A JP 21729789A JP H0382129 A JPH0382129 A JP H0382129A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- bumping
- semiconductor chip
- testing
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000012360 testing method Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 14
- 229910000679 solder Inorganic materials 0.000 abstract description 18
- 239000002184 metal Substances 0.000 abstract description 13
- 238000006748 scratching Methods 0.000 abstract 1
- 230000002393 scratching effect Effects 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 4
- 238000007664 blowing Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
フリップチップ方式で実装する半導体チップに関し、
ブロービングテストの際の針を立てる対象として、実装
の接続に供するバンプ用パッドまたはその上の半田バン
ブを除外し得るようにすることを目的とし、
上記バンプ用パッドの近傍に、該バンプ用パッドと電気
的に接続された試験用パッドを具えるように構成する。[Detailed Description of the Invention] [Summary] Regarding semiconductor chips mounted using the flip-chip method, the bump pads used for mounting connections or the solder bumps thereon are excluded as targets for setting a needle during a blowing test. For the purpose of achieving this, the test pad is configured to include a test pad electrically connected to the bump pad in the vicinity of the bump pad.
本発明は、半導体チップに係り、特に、フリップチップ
方式で実装する半導体チップに関する。The present invention relates to a semiconductor chip, and particularly to a semiconductor chip mounted using a flip-chip method.
コンピュータの高速化に伴い、半導体装置の実装技術も
新しい技術が要求されている。従来のパッケージによる
実装方法では実装密度及び高速性の点で限界が見えてき
た。そこで、パッケージを用いずにペアチップを直接実
装するフリップチップ方式が注目されている。As computers become faster, new mounting techniques for semiconductor devices are also required. Conventional packaging methods have reached their limits in terms of packaging density and high speed. Therefore, the flip-chip method, in which paired chips are directly mounted without using a package, is attracting attention.
フリップチップ方式は、半導体チップの表面にバンプ用
パッドを設け、その上に半田バンプを形威し、この半田
バンプにより半導体チップを直接実装基板に半田付けす
る実装方式である。この方式は、実装密度を高くなし得
るばかりではなく、接続用のリードが不要となることか
ら電気的特性の劣化が小さい利点がある。The flip-chip method is a mounting method in which bump pads are provided on the surface of a semiconductor chip, solder bumps are formed thereon, and the semiconductor chip is directly soldered to a mounting board using the solder bumps. This method not only allows for high packaging density, but also has the advantage of less deterioration of electrical characteristics since no connection leads are required.
(従来の技術〕
第2図はフリップチップ方式で実装する半導体チップの
従来例の平面図である。(Prior Art) FIG. 2 is a plan view of a conventional example of a semiconductor chip mounted by the flip-chip method.
同図において、11は半導体チップ、12は回路パター
ン領域、13はバンプ用パッド、である。回路パターン
領域12とバンプ用パッド13との間の配線は記載を省
略しである。In the figure, 11 is a semiconductor chip, 12 is a circuit pattern area, and 13 is a bump pad. The wiring between the circuit pattern area 12 and the bump pad 13 is omitted.
バンプ用パッド13は、配線金属からなり半導体チップ
11の表面に配置されて大きさが200 a m φ程
度であり、配線金属の表面に半田バンブに対するバリア
メタルの膜を設けである。そしてその上に半田バンプが
形成されて、フリップチップ方式による実装の接続に供
せられる。The bump pad 13 is made of a wiring metal, is placed on the surface of the semiconductor chip 11, and has a size of about 200 m φ, and a barrier metal film against the solder bump is provided on the surface of the wiring metal. Then, solder bumps are formed thereon and used for connection in flip-chip mounting.
この半導体チップは、実装の以前にブロービングテスト
により良否の確認が行われる。その際のブロービングと
しては、次の2通りがある。即ち、■ バンプ用パッド
13上(バリアメタル上)に針を立てる。The quality of this semiconductor chip is checked by a blowing test before it is mounted. There are two types of blobbing in this case: That is, (1) Place a needle on the bump pad 13 (on the barrier metal).
■ 半田バンブ形成後に、半田バンブ上に針を立てる。■ After forming the solder bump, place a needle on the solder bump.
しかしながら、上記■の場合には、バリアメタルに傷が
つき、半田バンプと配線金属が反応して配線の断線を起
こす恐れがあり、■の場合には、半田バンプが変形して
実装の接続を不安定にさせるので、何れの場合も信頼性
を低下させる問題がある。However, in the case of (■) above, the barrier metal may be damaged and the solder bumps may react with the wiring metal, causing the wiring to break. In either case, there is a problem of lowering reliability because it causes instability.
そこで本発明は、フリップチップ方式で実装する半導体
チップにおいて、ブロービングテストの際の針を立てる
対象として、実装の接続に供するバンプ用パッドまたは
その上の半田バンプを除外し得るようにすることを目的
とする。Accordingly, the present invention provides a method for excluding bump pads used for mounting connections or solder bumps thereon as targets for setting up needles during a blowing test in a semiconductor chip mounted using the flip-chip method. purpose.
上記目的は、実装の接続に供するバンプ用パッドの近傍
に、該バンプ用パッドと電気的に接続された試験用パッ
ドを具える本発明の半導体チップによって達成される。The above object is achieved by the semiconductor chip of the present invention, which includes a test pad electrically connected to the bump pad in the vicinity of the bump pad used for mounting connection.
上記試験用パッドが上記バンプ用パッドと電気的に接続
されていることから、この試験用パッドに針を立てるこ
とにより従来例と同様なブロービングテストを行うこと
が可能となる。Since the test pad is electrically connected to the bump pad, it is possible to perform a blobbing test similar to the conventional example by setting a needle on the test pad.
そしてそのようにしてブロービングテストを行えば、バ
ンプ用パッドまたはその上の半田バンプが針を立てる対
象から除外されて、バンプ用パッドに傷が付いたりバン
プ用パッド上の半田バンプが変形したりすることがなく
なり、その傷や変形に起因する信頼性の低下を防止する
ことができる。If you perform a blobbing test in this way, the bump pad or the solder bump on it will be excluded from the target, which will prevent the bump pad from being scratched or the solder bump on the bump pad from becoming deformed. This prevents deterioration in reliability due to scratches and deformation.
以下本発明の実施例について、それを模式的に示す第1
図の模式平面図を用いて説明する。Embodiments of the present invention will be described below in the first section which schematically shows them.
This will be explained using the schematic plan view shown in the figure.
同図において、1は半導体チップ、2は回路パターン領
域、3はバンプ用パッド、4は試験用パッド、である。In the figure, 1 is a semiconductor chip, 2 is a circuit pattern area, 3 is a bump pad, and 4 is a test pad.
回路パターン領域2とバンプ用パッド3または試験用パ
ッド4との間の配線は記載を省略しである。The wiring between the circuit pattern area 2 and the bump pad 3 or test pad 4 is omitted.
バンプ用パッド3は、従来例のバンプ用パッド13と同
様に、配線金属からなり半導体チップ1の表面に配置さ
れて大きさが200μmφ程度であり、配線金属の表面
に半田バンプに対するバリアメタルの膜を設けである。Like the conventional bump pad 13, the bump pad 3 is made of wiring metal and is placed on the surface of the semiconductor chip 1, and has a size of about 200 μmφ, and has a barrier metal film for solder bumps on the surface of the wiring metal. This is provided.
そしてその上に半田バンプが形成されて、フリップチッ
プ方式による実装の接続に供せられる。Then, solder bumps are formed thereon and used for connection in flip-chip mounting.
試験用パッド4は、配線金属からなり半導体チップlの
表面でバンプ用パッド3の近傍に配置され、バンブ用パ
ッド3と配線5で接続されて大きさが80μm角程度で
あり、表面は配線金属のままである。The test pad 4 is made of wiring metal, is placed near the bump pad 3 on the surface of the semiconductor chip l, is connected to the bump pad 3 by a wiring 5, has a size of about 80 μm square, and has a surface made of wiring metal. It remains as it is.
また、バンプ用パッド3または試験用パッド4の中の回
路パターン領域2に近いものが、回路パターン領域2の
回路と不図示の配線で接続されている。Further, the bump pad 3 or the test pad 4 that is close to the circuit pattern area 2 is connected to the circuit in the circuit pattern area 2 by wiring (not shown).
そして、バンブ用バンド3、試験用パッド4及び配線5
は、回路パターン領域2からの配線と同一配線層で形成
されている。Then, the bump band 3, the test pad 4 and the wiring 5
is formed of the same wiring layer as the wiring from the circuit pattern area 2.
この半導体チップ1のブロービングテストは、先に述べ
たように、試験用パッド4に針を立てて行う。こうする
ことにより、バンプ用パッド3に傷を付けたりバンプ用
パッド3上の半田バンブを変形させたりすることなしに
、従来例と同様なブロービングテストを行うことが可能
である。The blobbing test of the semiconductor chip 1 is performed by setting a needle on the test pad 4, as described above. By doing so, it is possible to perform a blobbing test similar to the conventional example without damaging the bump pad 3 or deforming the solder bump on the bump pad 3.
なお言うまでもなく、バンプ用バッド3及び試験用バッ
ド4の大きさや配列は、実施例で述べた寸法や第1図に
示す配列に限定されるものではない。Needless to say, the size and arrangement of the bump pads 3 and test pads 4 are not limited to the dimensions described in the embodiments or the arrangement shown in FIG.
以上説明したように本発明の槽底によれば、フリップチ
ップ方式で実装する半導体チップにおいて、ブロービン
グテストの際の針を立てる対象として、実装の接続に供
するバンプ用パッドまたはその上の半田バンプを除外し
得るようにすることができて、ブロービングテストの際
にバンプ用パッドに傷が付いたりバンブ用パッド上の半
田バンプが変形したりすることがなくなり、その傷や変
形に起因する信頼性の低下を防止させる効果がある。As explained above, according to the tank bottom of the present invention, in a semiconductor chip mounted by a flip-chip method, the bump pad used for mounting connection or the solder bump thereon can be used as a target for setting a needle during a blowing test. This eliminates damage to the bump pad or deformation of the solder bump on the bump pad during a blobbing test, and reduces reliability due to scratches or deformation. It has the effect of preventing sexual decline.
第1図は実施例の模式平面図、 第2図は従来例の模式平面図、 である。 図において、 ■、11は半導体チップ、 2.12は回路パターン領域、 3.13はバンプ用バッド、 4は試験用バッド、 5は配線、 である。 FIG. 1 is a schematic plan view of the embodiment; Figure 2 is a schematic plan view of the conventional example. It is. In the figure, ■, 11 is a semiconductor chip, 2.12 is the circuit pattern area, 3.13 is a bump pad, 4 is a test pad, 5 is wiring, It is.
Claims (1)
実装の接続に供するバンプ用パッドの近傍に、該バンプ
用パッドと電気的に接続された試験用パッドを具えるこ
とを特徴とする半導体チップ。A semiconductor chip mounted using a flip-chip method,
A semiconductor chip comprising a test pad electrically connected to the bump pad in the vicinity of the bump pad used for mounting connection.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21729789A JPH0382129A (en) | 1989-08-25 | 1989-08-25 | Semiconductor chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21729789A JPH0382129A (en) | 1989-08-25 | 1989-08-25 | Semiconductor chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0382129A true JPH0382129A (en) | 1991-04-08 |
Family
ID=16701932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21729789A Pending JPH0382129A (en) | 1989-08-25 | 1989-08-25 | Semiconductor chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0382129A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475236A (en) * | 1991-09-02 | 1995-12-12 | Fujitsu Limited | Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process |
US5554940A (en) * | 1994-07-05 | 1996-09-10 | Motorola, Inc. | Bumped semiconductor device and method for probing the same |
US5751015A (en) * | 1995-11-17 | 1998-05-12 | Micron Technology, Inc. | Semiconductor reliability test chip |
US5834849A (en) * | 1996-02-13 | 1998-11-10 | Altera Corporation | High density integrated circuit pad structures |
KR19990018725A (en) * | 1997-08-28 | 1999-03-15 | 윤종용 | Semiconductor wafer and its electrical property inspection method |
US6445001B2 (en) * | 1996-06-12 | 2002-09-03 | Kabushiki Kaisha Toshiba | Semiconductor device with flip-chip structure and method of manufacturing the same |
JP2006203215A (en) * | 2006-01-23 | 2006-08-03 | Renesas Technology Corp | Semiconductor integrated circuit device and method of manufacturing the same |
JP2007311432A (en) * | 2006-05-17 | 2007-11-29 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
JP2010034595A (en) * | 2009-11-12 | 2010-02-12 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
JP4837132B1 (en) * | 2011-03-23 | 2011-12-14 | 和也 山口 | Golf club gauge |
US9443811B2 (en) * | 2014-07-15 | 2016-09-13 | Lapis Semiconductor Co., Ltd. | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5230381A (en) * | 1975-09-03 | 1977-03-08 | Hitachi Ltd | Semiconductor integrating circuit |
-
1989
- 1989-08-25 JP JP21729789A patent/JPH0382129A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5230381A (en) * | 1975-09-03 | 1977-03-08 | Hitachi Ltd | Semiconductor integrating circuit |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475236A (en) * | 1991-09-02 | 1995-12-12 | Fujitsu Limited | Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process |
US5554940A (en) * | 1994-07-05 | 1996-09-10 | Motorola, Inc. | Bumped semiconductor device and method for probing the same |
US6770906B2 (en) | 1995-11-17 | 2004-08-03 | Micron Technology, Inc. | Semiconductor reliability test chip |
US5751015A (en) * | 1995-11-17 | 1998-05-12 | Micron Technology, Inc. | Semiconductor reliability test chip |
US5936260A (en) * | 1995-11-17 | 1999-08-10 | Micron Technology, Inc. | Semiconductor reliability test chip |
US6157046A (en) * | 1995-11-17 | 2000-12-05 | Micron Technology, Inc. | Semiconductor reliability test chip |
US6320201B1 (en) | 1995-11-17 | 2001-11-20 | Micron Technology, Inc. | Semiconductor reliability test chip |
US6538264B2 (en) | 1995-11-17 | 2003-03-25 | Micron Technology, Inc. | Semiconductor reliability test chip |
US5834849A (en) * | 1996-02-13 | 1998-11-10 | Altera Corporation | High density integrated circuit pad structures |
US6445001B2 (en) * | 1996-06-12 | 2002-09-03 | Kabushiki Kaisha Toshiba | Semiconductor device with flip-chip structure and method of manufacturing the same |
KR19990018725A (en) * | 1997-08-28 | 1999-03-15 | 윤종용 | Semiconductor wafer and its electrical property inspection method |
JP2006203215A (en) * | 2006-01-23 | 2006-08-03 | Renesas Technology Corp | Semiconductor integrated circuit device and method of manufacturing the same |
JP2007311432A (en) * | 2006-05-17 | 2007-11-29 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
JP2010034595A (en) * | 2009-11-12 | 2010-02-12 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
JP4837132B1 (en) * | 2011-03-23 | 2011-12-14 | 和也 山口 | Golf club gauge |
US9443811B2 (en) * | 2014-07-15 | 2016-09-13 | Lapis Semiconductor Co., Ltd. | Semiconductor device |
US9659887B2 (en) | 2014-07-15 | 2017-05-23 | Lapis Semiconductor Co., Ltd. | Semiconductor device |
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