JP4388265B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to an alignment mark used when a fuse is cut.
[0002]
[Prior art]
As a package that can be made smaller and thinner than wire bonding in which bonding pads on the surface of an IC (Integrated Circuit) chip and the external terminals of the package are electrically connected by a gold wire or the like, a CSP (chip) There has been proposed a mounting form in which a protruding (bump) electrode formed on a pad portion such as a size package is used for connection to an external terminal.
[0003]
This CSP is a generic name for a package that is equal to or slightly larger than the size of a semiconductor chip. 1) Easy to increase the number of pins, 2) A wide space between bump electrodes, and a large diameter of the bump electrodes. For reasons such as possible, some bump electrodes are arranged on the surface of the chip (so-called area array structure).
[0004]
In order to manufacture an IC having this area array structure, for example, wiring for connecting a pad portion arranged along the peripheral portion of the chip and a bump electrode arranged in an area on the entire surface of the chip, so-called rewiring is required. Become.
[0005]
[Problems to be solved by the invention]
On the other hand, memory LSIs such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and electrically erasable and erasable nonvolatile memory (EEPROM) are produced in the manufacturing process. By providing a redundant function for relieving defects, the manufacturing yield is improved.
[0006]
This is because a memory cell column or memory cell row for redundancy relief is prepared in advance in the semiconductor integrated circuit device, and when a defective memory cell column is generated in the memory array, an address signal entering the defective memory cell is generated. This is a defect relief function that causes a desired memory operation to be performed by inputting to the memory cell column (row) for redundancy relief.
[0007]
Switching between the defective memory cell and the redundant relief memory cell is performed by cutting a fuse connected to the address switching circuit. A laser fusing method or the like is employed for cutting the fuse.
[0008]
The present inventors are engaged in research and development of a semiconductor integrated circuit device (semiconductor device). In order to accurately determine the position of the fuse when the fuse of the semiconductor integrated circuit device is cut by a laser, Al (aluminum) is used. ) Was used to form a target (alignment mark).
[0009]
That is, after recognizing the target position, the fuse position is re-recognized from the relationship between the target and the fuse position, and the fuse is cut.
[0010]
In particular, with the miniaturization of elements, fuses are formed finely and at a short pitch, for example, with a width of about 1 μm and a distance of about 5 μm. In such a case, in order to accurately cut a desired fuse and to cut a fuse so as not to affect an adjacent fuse, the positioning accuracy of the target is important.
[0011]
However, when the inventors tried to cut a fuse in the semiconductor integrated circuit device using the rewiring described above, a target recognition failure occurred.
[0012]
Furthermore, as a result of the investigation of the cause by the present inventors, it has been found that the cause of the recognition failure is target corrosion (erosion).
[0013]
That is, as will be described in detail later, in a device using rewiring, a rewiring forming step and a bump electrode forming step exist after the formation of the target Al pattern.
[0014]
For example, when the rewiring is formed by an electrolytic plating method, an etching process of the seed layer is performed, and when a solder bump is used as the bump electrode, an Au (gold) film is formed as a base film. As a pretreatment for forming the gold film, cleaning using an acid or alkaline solution is performed.
[0015]
During such processing, the surface of the target was corroded by the etching solution or the cleaning solution, resulting in poor recognition.
[0016]
An object of the present invention is to improve the recognition accuracy of alignment marks and improve the fuse cutting accuracy.
[0017]
Another object of the present invention is to improve the yield of semiconductor integrated circuit devices and to improve the characteristics thereof.
[0018]
The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0019]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0020]
(1) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; Forming a second conductive film; (c) forming a first insulating film on the second conductive film; and (d) removing the first insulating film on the second conductive film. Exposing the first pad region, and (e) forming a third conductive film extending from the first pad region to the second pad region on the second conductive film. Forming a fourth conductive film in the same layer as the third conductive film on the scribe region; and (f) a second insulating film on the third conductive film and the fourth conductive film. And (g) a second insulating film on the second pad region of the third conductive film. Removing, those having the steps of cutting the (h) wherein (g) after the step, the first conductive film based on the position of the fourth conductive film.
[0021]
The first conductive film is, for example, a fuse, and redundancy repair of, for example, a memory cell is performed by cutting the fuse in the step (h). The second conductive film is, for example, a film having an Al film. The first insulating film is an inorganic film and is a film that attenuates the reflected light intensity of the second conductive film. The third and fourth conductive films are, for example, films having a Cu film. The second insulating film is, for example, a polyimide resin film.
[0022]
(2) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; Forming a second conductive film on the scribe region, forming a third conductive film in the same layer as the second conductive film; and (c) the second and third conductive films. Forming a first insulating film on the film; and (d) removing at least a portion of the third conductive film by removing the first insulating film on the second and third conductive films. Exposing a first pad region of the second conductive film; (e) forming a second insulating film on the second and third conductive films; and (f) the second conductive film. The first pad region is exposed by removing the second insulating film on the conductive film. A step of leaving the second insulating film so as to cover the exposed region of the third conductive film; and (g) a second pad from the first pad region on the second conductive film. A step of forming a fourth conductive film extending to a region; and (h) after the step (g), the position of the exposed region of the third conductive film is confirmed through the second insulating film. Cutting the first conductive film based on the position.
[0023]
The first conductive film is, for example, a fuse, and redundancy repair of, for example, a memory cell is performed by cutting the fuse in the step (h). The second and third conductive films are films having an Al film, for example. The first insulating film is an inorganic film and is a film that attenuates the reflected light intensity of the second and third conductive films. The fourth conductive film is, for example, a film having a Cu film. The second insulating film is, for example, a polyimide resin film.
[0024]
(3) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; Forming a first wiring having a second conductive film and an upper third conductive film, and forming a pattern having the second conductive film and an upper third conductive film in the scribe region; (C) forming a first insulating film on the first wiring and the pattern; and (d) removing the first insulating film on the first wiring and the pattern to remove the first wiring. Exposing a first pad region of the third conductive film to constitute and exposing at least a part of the third conductive film constituting the pattern; and (e) a first pad on the first wiring. Extends from area to second pad area Forming a second wiring that is one having the steps of cutting the first conductive film on the basis of the position of the (f) after step (e), the exposed region of said pattern.
[0025]
The first conductive film is, for example, a fuse, and redundant repair of, for example, a memory cell is performed by cutting the fuse in the step (f). The first wiring and the pattern have, for example, a second conductive film mainly composed of Al and a third conductive film made of a TiN film on the second conductive film. The first insulating film is an inorganic film and is a film that attenuates the reflected light intensity of the second and third conductive films. The second wiring is, for example, a wiring having a Cu film.
[0026]
(4) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; and (b) the chip region and the scribe. Forming a groove in the region; (c) forming a second conductive film in the groove; (d) forming a first insulating film on the second conductive film; e) exposing the first pad region on the second conductive film by removing the first insulating film on the second conductive film in the chip region; and (f) the second conductive property. Forming a third conductive film extending from the first pad region to the second pad region on the film; and (g) after the step (f), the second conductive film in the scribe region. The position is confirmed through the first insulating film, and the first position is determined based on the position. And cutting the conductive film, and has a.
[0027]
The first conductive film is, for example, a fuse, and redundant repair of, for example, a memory cell is performed by cutting the fuse in the step (g). The second conductive film is, for example, a film containing Cu as a main component. The first insulating film is an inorganic film and transmits the reflected light of the second conductive film. The third conductive film is a film having a Cu film, for example.
[0028]
(5) A semiconductor integrated circuit device according to the present invention includes: (a) a first conductive film formed in a chip region of a semiconductor substrate; (b) a second conductive film formed in the chip region; ) A first insulating film formed on the second conductive film and exposing a first pad region of the second conductive film; and (d) a first pad region on the second conductive film. A third conductive film extending to the two-pad region; (e) a fourth conductive film formed on the outer periphery of the chip region and having the same configuration as the third conductive film; And a bump electrode formed on the second pad region of the third conductive film.
[0029]
The first conductive film is, for example, a fuse, and redundancy repair of, for example, a memory cell is performed by cutting the fuse. The second conductive film is, for example, a film having an Al film. The first insulating film is an inorganic film and is a film that attenuates the reflected light intensity of the second conductive film. The third and fourth conductive films are, for example, films having a Cu film. The outer peripheral portion of the chip region is, for example, a scribe region remaining in the outer peripheral portion of the chip region when a wafer substrate is cut along a scribe line. The bump electrode is made of, for example, solder.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0031]
(Embodiment 1)
FIG. 1 is a plan view showing a semiconductor wafer W (semiconductor substrate 1) on which the semiconductor integrated circuit device of the present embodiment is formed.
[0032]
As shown in the figure, the semiconductor wafer W has a plurality of substantially rectangular chip areas CA, and the plurality of chip areas CA are partitioned by a scribe area SA. A target T, which will be described in detail later, is formed on the scribe region.
[0033]
Next, a semiconductor integrated circuit device according to an embodiment of the present invention will be described according to the manufacturing method thereof.
[0034]
First, a semiconductor element is formed on the semiconductor substrate 1. There are various types of semiconductor elements, and a detailed description thereof is omitted here. For example, FIG. 2 shows an example of the structure of a DRAM memory cell.
[0035]
As shown in FIG. 2, an element isolation 3 and a p-type well 5 in which an insulating film such as a silicon oxide film is embedded are formed in a semiconductor substrate 1. Information transfer is performed on the main surface of the p-type well 5. A MISFET Qt is formed.
[0036]
The information transfer MISFET Qt has a gate electrode G formed on the semiconductor substrate 1 via a gate insulating film 7, and includes source and drain regions 9 and 11 formed in the semiconductor substrate 1 on both sides of the gate electrode G. Have. The gate electrode G is composed of a stacked film of a polycrystalline silicon film 13a, a WN (tungsten nitride) film 13b, and a W (tungsten) film 13c, and a silicon nitride film 15 is formed thereon. Further, a silicon nitride film 17 is formed on the side wall of the gate electrode G and the like, plugs P1b and P1a are formed on the source and drain regions 9 and 11, and a plug P2a is provided on the plug P1a. Thus, a bit line BL is formed. Further, an information storage capacitive element C is formed on the plug P1b via the plug P2b. The information storage capacitive element C includes, for example, an upper electrode 21 made of a TiN (titanium nitride) film, a capacitive insulating film 23 made of a tantalum oxide film, and a lower electrode 25 made of a polycrystalline silicon film.
[0037]
Reference numerals 27a to 27e are interlayer insulating films made of, for example, a silicon oxide film.
[0038]
In addition to such a memory element, various elements such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) constituting a peripheral circuit are formed in the chip area CA described with reference to FIG.
[0039]
FIG. 3 is an enlarged view of the vicinity of the chip area CA in FIG. As shown in the figure, there are a plurality of memory areas MA in the chip area CA, and there is a redundant memory area RA at the end of this area. Further, between the memory areas MA is a peripheral circuit area PA, and MISFETs and the like constituting the peripheral circuit are formed.
[0040]
For example, the fuse area FA is arranged in the peripheral circuit area PA, and, for example, a plurality of linear conductive patterns (for example, a width of about 1 μm) are formed at a narrow pitch (about 5 μm).
[0041]
By appropriately disconnecting this fuse, for example, an address signal that enters a defective memory cell is input to the memory cell column for redundancy repair, thereby performing redundancy repair.
[0042]
This fuse can be formed of the same film as the conductive film constituting the memory cell or wiring.
[0043]
For example, the fuse F shown in FIG. 4 can be formed of the same film as the gate electrode G constituting the DRAM memory cell shown in FIG. In FIG. 4, descriptions of memory cells, other semiconductor elements, and plugs for connecting wirings to these are omitted (the same applies to the following drawings). 4 to 13 are cross-sectional views of the main part of the substrate in the chip area CA and the scribe area SA, a partially enlarged view thereof, or a main part plan view.
[0044]
As shown in FIG. 4, on the fuse F, for example, a silicon oxide film 31 is formed as an insulating film, and further, a first layer wiring M1 is formed thereon. The first layer wiring M1 and the fuse F are connected via a plug P1. As described above, when the fuse F is formed of the same film as the gate electrode G constituting the memory cell, the silicon oxide film 31 corresponds to, for example, the silicon oxide films 27a and 27b in FIG. Further, the first layer wiring M1 corresponds to, for example, the bit line BL in FIG.
[0045]
For example, a silicon oxide film 32 is formed as an insulating film on the first layer wiring M1, and further, a second layer wiring M2 is formed thereon. The second layer wiring M2 and the first layer wiring M1 are connected via a plug P2. For example, the silicon oxide film 32 corresponds to the silicon oxide films 27c to 27e in FIG.
[0046]
On the second layer wiring M2, for example, a silicon oxide film 33 is formed as an insulating film, and a plug P3 is formed in the silicon oxide film 33. The plug P3 serves as a connection portion between the second layer wiring M2 and a third layer wiring M3 described later.
[0047]
Next, as shown in FIG. 5, for example, a TiN film M3a, an Al (aluminum) alloy film M3b, and a TiN film M3c are sequentially deposited on the silicon oxide film 33 and the plug P3, and patterned into a desired shape to form a third. A layer wiring M3 is formed.
[0048]
Next, a silicon oxide film (lower layer) such as a TEOS film and a silicon nitride film (upper layer) are sequentially deposited on the upper part of the third-layer wiring M3 and the like by, for example, a CVD (Chemical Vapor Deposition) method, A passivation film 41 made of a film is formed. The passivation film 41 may be composed of a single layer.
[0049]
Next, the passivation film 41 on the third-layer wiring M3 is removed by dry etching to expose the first pad portion PAD1.
[0050]
Note that when the passivation film 41 is dry-etched, the TiN film M3c of the first pad portion PAD1 is removed.
[0051]
At this time, the insulating film (31 to 33, etc.) on the fuse F may be removed. This is because the fuse F can be easily cut with a laser by thinning the insulating film on the fuse F.
[0052]
Next, a photosensitive polyimide resin film 43 is spin-coated on the passivation film 41 and subjected to heat treatment (pre-baking). Next, the polyimide resin film is exposed and developed to expose the first pad portion PAD1 and the groove 42, and to expose the scribe region SA. Next, heat treatment (post bake) at about 350 ° C. is performed to cure (cure) the polyimide resin film.
[0053]
Next, as shown in FIG. 6, a seed layer (power feeding layer) 45 is formed on the polyimide resin film 43 including on the first pad portion PAD <b> 1. The seed layer 45 is made of, for example, a laminated film of a Cr (chromium) film and a Cu (copper) film. For example, the seed layer 45 may be formed of a laminated film of a TiN film and a Cu film.
[0054]
Next, a resist film R having a long groove 47 extending from the upper portion of the first pad portion PAD1 to the second pad portion PAD2 formation region described later is formed on the seed layer 45 using a photolithography technique.
[0055]
Here, a substantially L-shaped groove 47t having a width of about 10 μm for forming the target T is also formed on the scribe region SA (see FIG. 13).
[0056]
Next, a Cu film 49a is formed in the grooves 47 and 47t by electrolytic plating. In order to form the Cu film 49a, the seed layer 45 is fixed to the minus (−) electrode by immersing the substrate 1 in a Cu plating solution, and the seeds at the bottoms of the grooves 47 and 47t not covered with the resist film R are formed. A Cu film 49 a is deposited on the surface of the layer 45.
[0057]
Thereafter, a Ni (nickel) film 49b is formed on the Cu film 49a inside the grooves 47 and 47t by an electrolytic plating method. In order to form the Ni film 49b, the substrate 1 is immersed in a plating solution for Ni to fix the seed layer 45 to the minus (−) electrode, and Cu at the bottom of the grooves 47 and 47t not covered with the resist film R is formed. A Ni film 49b is deposited on the surface of the film 49a.
[0058]
Thereafter, as shown in FIG. 7, after removing the resist film R, the seed layer 45 which is no longer necessary by wet etching using the Cu film 49a and the Ni film 49b as a mask is removed. As an etching solution for the Cu film, for example, sulfuric acid perwater is used, and as an etching solution for the Cr film, for example, a mixed solution of potassium permanganate and sodium metasilicate is used.
[0059]
As a result, the rewiring 49 and the target T made of the Cu film 49a, the Ni film 49b, and the seed layer 45 are formed. FIG. 12 shows a partially enlarged view of the target T portion of FIG. FIG. 13 shows a plan view of the main part of the target T portion. Instead of the Cu film 49a and the Ni film 49b, a stacked film of a Cr film, a Cu film, and a Cr film may be formed by, for example, a sputtering method.
[0060]
In this rewiring, for example, since it is difficult to form a bump electrode on the first pad portion PAD1 formed densely around the center of the chip area CA, the bump electrode is formed over the entire surface of the chip area CA. When the first pad part PAD1 is arranged at a wider interval than the first pad part PAD1, it plays a role of connecting the first pad part PAD1 and the bump electrode (second pad part PAD2 described later). Further, the rewiring can be said to be a wiring for rearranging the first pad portion PAD1 having a narrow interval to the second pad portion PAD2 having a larger interval. Or it can be said that it is wiring for changing the space | interval between pad parts.
[0061]
The seed layer 45 below the rewiring 49 has a role of improving the adhesive strength between the Cu film 49 a and the polyimide resin film 43 below the Cu film 49 a and a role of preventing Cu from diffusing into the polyimide resin film 43. Fulfill.
[0062]
The reason why the Ni film 49b is laminated on the Cu film 49a is to prevent an undesired product from being formed when a solder bump electrode 55 described later and the Cu film 49a come into contact with each other. Further, the Ni film has good adhesion to the polyimide resin film to be formed later. In addition to Ni, Cr, Ti, TiN, Ta (tantalum), TaN (tantalum nitride), WN (tungsten nitride), or the like may be used.
[0063]
Next, as shown in FIG. 8, a polyimide resin film 51 having openings in the second pad portion PAD <b> 2, the groove 42, and the scribe region SA on the rewiring 49 is formed. The polyimide resin film 51 can be formed in the same manner as the polyimide resin film 43. That is, a photosensitive polyimide resin film is spin-coated and heat treatment is performed. Next, the polyimide resin film is exposed and developed to open the second pad portion PAD2 and the scribe area SA, and then heat treatment (post bake) at about 350 ° C. is performed to cure (cure) the polyimide resin film.
[0064]
Next, the Au film 53 is formed by the electroless plating method on the Ni film 49b exposed at the opening (second pad portion PAD2) of the polyimide resin film 51. First, ashing (ashing) treatment, Processing such as alkaline degreasing and acid cleaning is performed.
[0065]
That is, since an organic contamination layer such as an oxide film or a polyimide resin film residue is formed on the Ni film 49b of the second pad portion PAD2, the organic contamination layer is first formed by ashing using oxygen. Remove.
[0066]
Next, alkaline degreasing and acid cleaning are performed to remove the oxide film and activate the surface of the Ni film 49b. For the alkaline degreasing treatment, for example, a sodium metasilicate solution is used. The acid cleaning is performed using hydrochloric acid (HCl).
[0067]
Next, an Au film 53 is deposited on the Ni film 49b exposed from the second pad portion PAD2 by electroless plating. As the Au plating solution, for example, a sodium gold sulfite plating solution is used. This plating method uses the difference in the ionization tendency between Ni and Au and replaces them to form the Au film 53, which is called the substitution plating method among the electroless plating methods. At this time, the Au film 53 is also formed on the target T.
[0068]
The reason why the Au film 53 is formed on the Ni film 49b of the second pad portion PAD2 is to improve the wettability of the solder bump electrode 55 formed on the second pad portion PAD2. This “wetting property” means, for example, the degree of familiarity between the alloy solder and the Au film when an alloy solder of Sn (tin) and Pb (lead) is mounted on the second pad portion PAD2. Instead of the Au film 53, a barrier metal film may be formed between the Au film, such as using a laminated film of Ni film and Au film or a laminated film of NiCu (nickel copper) film and Au film.
[0069]
Next, for example, inspection (P inspection) is performed by contacting a probe needle on the Au film 53 on the second pad portion PAD2, and it is determined whether the memory cell electrically connected to the second pad portion PAD2 is good or defective. To do. From this determination result, the memory cell to be redundantly repaired is determined, and the fuse F to be cut is specified. The P inspection may be performed using the first pad portion PAD1.
[0070]
Next, the semiconductor wafer W is set in the laser relief machine, and as shown in FIG. 9, the target T is irradiated with the laser beam RB to recognize the position of the target T, and then the position of the fuse F is determined from the position of the target T. To do.
[0071]
For example, in order to recognize the position of the target T, as shown in FIG. 13, the laser is scanned in the X direction and the Y direction, and the change in the reflection intensity of the laser is measured. The intersection (coordinate) of the center line of the region where the reflection intensity in the X direction and the Y direction exceeds the threshold becomes the reference point RP. The target T is recognized twice for each chip area CA. It may be performed twice for each shot. A shot refers to one transfer area when each pattern constituting a semiconductor element is transferred.
[0072]
Next, the position (coordinates) of the fuse F determined to be cut by the P inspection is irradiated with laser light to cut the fuse F (FIG. 9).
[0073]
Thereafter, as shown in FIG. 10, a bump electrode 55 made of an alloy solder of Sn (tin) and Pb (lead) is formed on the Au film 53. The bump electrode 55 is formed by, for example, a printing method or a ball transfer method. In FIG. 10, the Au film 53 is shown for easy understanding, but after the solder is mounted, the Au film 53 is absorbed into the solder.
[0074]
Thereafter, the semiconductor wafer W is diced along the scribe area SA and divided into a plurality of chips (CA). Next, for example, individual chips (CA) are face-down bonded on the mounting substrate 60, the bump electrodes 55 are heated and reflowed, and then an underfill resin 62 is filled in the gap between the chip (CA) and the mounting substrate 60. Thus, the CSP is completed (FIG. 11).
[0075]
As described above, according to the present embodiment, the target T is composed of the same layer as the rewiring 49, and therefore, for example, the target is corroded by the etching solution for the seed layer 45 or the pretreatment liquid when the Au film 53 is formed. The position of the target T can be accurately recognized.
[0076]
Therefore, the fuse can be accurately cut. As a result, the product yield is improved by redundant relief of the memory cells. Further, it is possible to prevent the fuse from being cut erroneously and to improve the product yield. Further, the influence on adjacent fuses can be reduced, and the product performance can be improved.
[0077]
For example, as shown in FIG. 14, when the target T is formed of the same layer as the third layer wiring M3, an Al alloy film M3b (target T or third layer wiring M3) is interposed through an inorganic film such as the passivation film 41. The laser reflected light cannot be confirmed. That is, such an inorganic film can be said to be a film that attenuates the reflected light intensity of the Al alloy film M3b. Therefore, it is necessary to remove the passivation film 41 above the target T and form the opening OA. Further, similarly to the first pad portion PAD1, when the TiN film M3c exposed from the opening OA is removed and the Al alloy film M3b is exposed, the Al alloy film M3b is performed by the steps shown in FIGS. This surface is exposed to an etching solution for removing the seed layer 45, and the Al alloy film M3b is corroded.
[0078]
Further, as shown in FIGS. 19 and 20, the Al alloy film M3b is corroded on the surface of the second pad portion PAD2 by the pretreatment liquid before the Au film 53 is formed.
[0079]
FIG. 21 is a partially enlarged view of the vicinity of the target T portion in FIG. 14, and FIG. 22 is a plan view of the main part in the vicinity of the target T portion.
[0080]
As a result, the position of the target T cannot be recognized, and the fuse F cannot be cut accurately. 15 to 20 are principal part cross-sectional views or principal part plan views of the substrate showing the manufacturing process of the semiconductor integrated circuit device for explaining the effects of the present embodiment (also for FIGS. 23 to 28). the same).
[0081]
On the other hand, in the steps shown in FIGS. 23 to 25, the probe needle P is brought into contact with the first pad portion PAD1 to perform the P inspection (FIG. 23), and the position of the target T is recognized by the laser beam RB (FIG. 23). 24) The fuse F can be cut (FIG. 25) prior to the removal of the seed layer 45 and the pretreatment step when forming the Au film 53. In this case, however, the rewiring 49 and the polyimide resin are removed after the P inspection. There is a formation process of the film 51, the Au film 53, etc., and damage due to a thermal load (for example, post-baking of the polyimide resin film 51) during these formation processes is not reflected in the P inspection, and the redundant relief is incomplete. Become. As a result, the yield decreases. Examples of the damage caused by the thermal load include a decrease in refresh margin in the case of DRAM memory.
[0082]
26 to 28, for example, the target T is covered with the passivation film 41 (FIG. 26), and after the pretreatment process (FIG. 27) when removing the seed layer 45 and forming the Au film 53. A method of removing the passivation film 41 on the target T and forming the opening OA before the fuse F is cut (FIG. 28) can be considered, but in this case, the number of steps for removing the passivation film 41 is increased.
[0083]
On the other hand, in this Embodiment, the said effect can be acquired, avoiding these problems.
[0084]
(Embodiment 2)
In the first embodiment, the target T is formed on the passivation film 41 in the scribe region SA. However, after etching the passivation film 41 in the scribe region SA and the insulating film therebelow to form a groove, The target T may be formed by embedding a conductive film.
[0085]
The steps up to the formation of the third layer wiring M3 are the same as those in the first embodiment described with reference to FIGS. 4 and 5, and thus the description thereof is omitted.
[0086]
As shown in FIG. 29, the passivation film 41 is formed on the third-layer wiring M3 as in the first embodiment, and then the passivation film 41 on the third-layer wiring M3 is removed by dry etching. The first pad portion PAD1 on the three-layer wiring M3 is exposed.
[0087]
At this time, the passivation film 41 on the fuse F and the underlying insulating film (33 and the like) are removed to form the groove 42, and further, the groove 63 is formed on the scribe region SA. The pattern of the groove 63 is substantially L-shaped, and its width is about 10 μm (see FIG. 34).
[0088]
Next, as in the first embodiment, a polyimide resin film 43 having an opening is formed on the scribe region SA, the first pad portion PAD1, and the groove 42, and a seed layer 45 is further formed thereon.
[0089]
Next, as in the first embodiment, a resist film R having a long groove 47 and a substantially L-shaped groove 47t is formed (FIG. 30), and a Cu film 49a and a Ni film 49b are formed therein by electrolytic plating. Then, after removing the resist film R, the seed layer 45 is removed using the Cu film 49a and the like as a mask. As a result, the rewiring 49 and the target T made of the Cu film 49a, the Ni film 49b, and the seed layer 45 are formed (FIG. 31). This target T is formed in the groove 63. FIG. 33 is a partially enlarged view of the target T portion in FIG. FIG. 34 is a plan view of the main part of the target T portion.
[0090]
Next, as shown in FIG. 32, as in the first embodiment, a polyimide resin film 51 having an opening in the second pad portion PAD2 and the scribe region SA on the rewiring 49 is formed and exposed from the second pad portion PAD2. After the surface treatment (ashing treatment, alkali degreasing treatment, acid cleaning, etc.) of the Ni film 49b is performed, an Au film 53 is formed on the surface. At this time, the Au film 53 is also formed on the target T.
[0091]
Thereafter, as in the first embodiment, a P inspection is performed using the Au film 53 on the second pad portion PAD2, and after the target T is recognized by the laser rescue machine, the fuse F is cut.
[0092]
Next, the bump electrode 55 is formed on the Au film 53 in the same manner as in the first embodiment, and further mounted on the mounting substrate 60 or the like.
[0093]
As described above, according to the present embodiment, the target T is formed of the same layer as the rewiring and further formed inside the trench. For example, the pretreatment at the time of forming the seed layer etching solution or the Au film The target can be prevented from being corroded by the liquid, and the position of the target T can be accurately recognized.
[0094]
(Embodiment 3)
The seed layer 45 may be left in the groove 63 by reducing the pattern width of the groove 63 without growing a plating film in the groove 63 of the second embodiment, and this film may be used as a target.
[0095]
That is, as described in the second embodiment with reference to FIG. 29, the groove 63 is formed in the scribe area SA. However, the pattern of the groove 63 is substantially L-shaped, and its width is about 1 to 5 μm (see FIG. 38).
[0096]
Next, as in the second embodiment, a polyimide resin film 43 and a seed layer 45 are formed, and a resist film R having a long groove 47 is formed. At this time, as shown in FIG. Covered with R, plating films (Cu film 49a and Ni film 49b) are not formed.
[0097]
Next, as in the second embodiment, after forming a plating film in the groove 47, the resist film R is removed, the seed layer 45 is removed using the Cu film 49a and the like as a mask, and a rewiring 49 is formed (FIG. 36).
[0098]
At this time, since the width of the pattern of the groove 63 is small, the seed layer 45 is thickly deposited on the bottom thereof, and the etching is difficult to proceed. Therefore, as shown in FIG. Layer 45 (target T) remains. FIG. 37 is a partially enlarged view of the target T portion shown in FIG. FIG. 36 shows a plan view of the main part of the target T portion.
[0099]
Next, as in the second embodiment, the polyimide resin film 51 is formed, the Ni film 49b is subjected to surface treatment, and then the Au film 53 is formed on the surface.
[0100]
Thereafter, as in the second embodiment, a P inspection is performed using the Au film 53 on the second pad portion PAD2, and after the target T is recognized by the laser relief machine, the fuse F is cut.
[0101]
Next, a bump electrode 55 is formed on the Au film 53 in the same manner as in the second embodiment, and further mounted on the mounting substrate 60 or the like.
[0102]
Thus, according to the present embodiment, since the target T is configured by the seed layer 45, corrosion of the target can be prevented and position recognition of the target T can be performed accurately.
[0103]
In the present embodiment, as shown in FIG. 37, the surface of the target T can be made lower than the surface height of the passivation film 41, and the passivation film 41 is independent of the positional accuracy of the exposure machine used for forming the resist film. Position accuracy can be obtained.
[0104]
(Embodiment 4)
In the present embodiment, the polyimide resin film 51 is left on the upper part of the target of the second embodiment.
[0105]
As shown in FIG. 39, the rewiring 49 and the target T are formed as in the second embodiment.
[0106]
Next, as shown in FIG. 40, as in the first embodiment, a polyimide resin film 51 having openings in the second pad portions PAD2 and the like on the rewiring 49 is formed. At this time, the polyimide is covered so as to cover the target T. The resin film 51 is left. FIG. 42 is a partially enlarged view of the target T portion in FIG. FIG. 43 shows a plan view of the main part of the target T portion.
[0107]
Thereafter, the Ni film 49b exposed from the second pad portion PAD2 is subjected to surface treatment, and an Au film 53 is formed on the surface (FIG. 41).
[0108]
Thereafter, as in the first embodiment, a P inspection is performed using the Au film 53 on the second pad portion PAD2, and after the target T is recognized by the laser rescue machine, the fuse F is cut. At this time, since the organic film such as the polyimide resin film 51 transmits the reflected light of the target T, the target T underneath can be recognized.
[0109]
Thus, according to the present embodiment, as in the second embodiment, the target can be prevented from being corroded and the position of the target T can be accurately recognized.
[0110]
(Embodiment 5)
In the present embodiment, the target T is formed of the same layer as the third layer wiring M3, and the polyimide resin film 43 is left on the target.
[0111]
Since the second layer wiring M2 and the plug P3 are formed in the same manner as in the first embodiment described with reference to FIG. 4, the description thereof is omitted.
[0112]
As shown in FIG. 44, for example, a TiN film M3a, an Al alloy film M3b, and a TiN film M3c are sequentially deposited on the silicon oxide film 33 and the plug P3, and patterned into a desired shape to form a third layer wiring M3. To do. At this time, the target T is formed in the scribe region SA with a film in the same layer as the film constituting the third layer wiring M3. That is, the target T is composed of a TiN film M3a, an Al alloy film M3b, and a TiN film M3c. The pattern of the target T is substantially L-shaped, and its width is about 10 μm (see FIG. 48).
[0113]
Next, as in the first embodiment, a passivation film 41 is formed, and then the passivation film 41 on the third-layer wiring M3 is removed by dry etching to expose the first pad portion PAD1. At this time, the passivation film 41 covering the target T is also removed, and the opening OA is formed. Next, the TiN film M3c exposed from the first pad portion PAD1 and the opening OA is removed. Note that it is not necessary to remove all of the passivation film 41 and the like on the target T. For example, as shown in FIG. 48, the pattern of the opening OA may be an inverted L shape.
[0114]
Next, as shown in FIG. 45, a polyimide resin film 43 having an opening is formed on the first pad portion PAD1 and the groove 42 as in the first embodiment. At this time, the polyimide resin film 43 is left to cover the target T. FIG. 47 shows a partially enlarged view of the target T portion of FIG. FIG. 48 shows a plan view of the main part of the target T portion.
[0115]
Next, as shown in FIG. 46, as in the first embodiment, a resist film R having grooves 47 is formed, and after a plating film is formed therein, the resist film R is removed, and a Cu film 49a, etc. As a mask, the seed layer 45 is removed and a rewiring 49 is formed.
[0116]
Next, as in the first embodiment, after forming the polyimide resin film 51 and performing the surface treatment of the Ni film 49b, the Au film 53 is formed on the surface thereof.
[0117]
Thereafter, as in the first embodiment, a P inspection is performed using the Au film 53 on the second pad portion PAD2, and after the target T is recognized by the laser rescue machine, the fuse F is cut. At this time, since the polyimide resin film 43 transmits the reflected light of the target T, the target T in the lower layer can be recognized.
[0118]
Thus, according to the present embodiment, since the polyimide film is left on the target T made of an Al alloy film or the like, for example, the target layer formed by the seed layer etchant or the pretreatment liquid at the time of Au film formation is used. Corrosion can be prevented and the position of the target T can be accurately recognized.
[0119]
(Embodiment 6)
In the present embodiment, the target T is formed of the same layer as the third layer wiring M3, and the uppermost TiN film M3c is left.
[0120]
In the fifth embodiment, as described with reference to FIG. 44, the passivation film 41 is formed, and then the first pad portion PAD1 on the third-layer wiring M3 is exposed to cover the target T. After removing 41 and forming the opening OA, the exposed TiN film M3c is further removed, but in this embodiment, the TiN film M3c is left as shown in FIG. This TiN film is highly resistant to the etchant for the seed layer 45 and the pretreatment liquid when the Au film 53 is formed.
[0121]
FIG. 49 is a partially enlarged view of the target T portion, and FIG. 50 is a plan view of the main part of the target T portion.
[0122]
Thus, in the present embodiment, since the TiN film M3c on the target T is left, for example, an Al alloy film that constitutes the target T by the seed layer etching liquid or the pretreatment liquid during the formation of the Au film. Corrosion of M3b can be prevented and the position of the target T can be accurately recognized.
[0123]
The manufacturing process of the semiconductor device of the present embodiment is the same as that of the fifth embodiment except that the TiN film M3c on the target T is left and the polyimide resin film 43 on the target T is not formed. Therefore, the detailed description is abbreviate | omitted.
[0124]
Of course, as described in the fifth embodiment, the polyimide resin film 43 may be left on the target T where the TiN film M3c is left as shown in FIGS. 51 is a partially enlarged view of the target T portion, and FIG. 52 is a plan view of the main part of the target T portion.
[0125]
(Embodiment 7)
In the fifth and sixth embodiments, the target T is formed of the same layer as the third-layer wiring M3, and the TiN film M3c and the polyimide resin film 43 on the upper part thereof are left. However, as shown below, the third layer The wiring M3 may be formed using a copper film.
[0126]
Since the second layer wiring M2 and the plug P3 are formed in the same manner as in the first embodiment described with reference to FIG. 4, the description thereof is omitted.
[0127]
As shown in FIG. 53, for example, a silicon nitride film 35a and a silicon oxide film 35b are sequentially deposited on the silicon oxide film 33 and the plug P3, and then the insulating film on the plug P3 is removed to form a wiring groove 37a. At this time, a target groove 37b is also formed on the scribe area SA. The groove pattern is substantially L-shaped and has a width of about 10 μm (see FIG. 59).
[0128]
Next, as shown in FIG. 54, a copper film 39 is deposited on the silicon oxide film 35b including in the grooves 37a and 37b by using, for example, a plating method, a CVD method, a sputtering method, or the like.
[0129]
Next, as shown in FIG. 55, the copper film 39 outside the grooves 37a and 37b is removed by, for example, a CMP (Chemical Mechanical Polishing) method to form the target T and the third layer wiring M3.
[0130]
Next, as in the first embodiment, a passivation film 41 is formed on the third layer wiring M3 and the like, and the first pad portion PAD1 and the like on the third layer wiring M3 are exposed. A polyimide resin film 43 having an opening is formed on the pad portion PAD1 and the groove 42 (FIG. 56). At this time, the passivation film 41 remains on the target T. FIG. 58 is a partially enlarged view of the target T portion, and FIG. 59 is a plan view of the main part of the target T portion.
[0131]
Further, similarly to the first embodiment, after forming the Cu film 49a and the Ni film 49b, the seed layer 45 is etched using these films as a mask to form the rewiring 49. Next, a polyimide resin film 51 having openings in the second pad portion PAD2 and the scribe region SA on the rewiring 49 is formed, and surface treatment (ashing treatment, alkali degreasing treatment and the like) of the Ni film 49b exposed from the second pad portion PAD2 is formed. Acid cleaning or the like) is performed to form an Au film 53 on the surface (FIG. 57).
[0132]
Thereafter, as in the first embodiment, a P inspection is performed using the Au film 53 on the second pad portion PAD2, and after the target T is recognized by the laser rescue machine, the fuse F is cut. At this time, the reflected light of the copper film constituting the target T can also be detected through the passivation film 41. Therefore, the position of the target T can be recognized.
[0133]
Next, the bump electrode 55 is formed on the Au film 53 in the same manner as in the first embodiment, and further mounted on the mounting substrate 60 or the like.
[0134]
As described above, according to the present embodiment, the target T is made of copper wiring, and the passivation film 41 is left on the target T, so that, for example, a pretreatment at the time of forming an etchant for the seed layer or an Au film The target can be prevented from being corroded by the liquid, and the position of the target T can be accurately recognized.
[0135]
(Embodiment 8)
In the first embodiment and the like, the target T is substantially L-shaped, but the pattern shape of the target is not limited to such a shape. For example, as shown in FIG. It may be a shape (rectangular) pattern.
[0136]
Also in this case, the reference point RP can be determined by scanning the laser in the X direction and the Y direction and measuring the change in the reflection intensity of the laser.
[0137]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0138]
In particular, in the first embodiment and the like, a DRAM memory cell has been described as an example of a memory cell. However, in addition to this, the present invention can be widely applied to a semiconductor integrated circuit device that performs redundant relief of a memory cell such as an SRAM or a nonvolatile memory. is there. The fuse is not limited to a memory cell redundancy relief.
[0139]
In the first embodiment, the fuse F is formed of the same film as the gate electrode G. However, the fuse may be formed of the same layer as the wiring and the plug.
[0140]
In the first embodiment and the like, the target is formed in the scribe area SA, but the target formation position may be in the chip area CA. However, it is desirable to form in the scribe region SA from the viewpoint of high integration of elements.
[0141]
In addition, a wiring or a rewiring formed in the chip area CA may be used as a target.
[0142]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0143]
The target (alignment mark) is composed of a film in the same layer as the rewiring that extends from the first pad area to the second pad area, and the fuse and the fuse are cut based on the position. Therefore, the target recognition accuracy can be improved and the fuse cutting accuracy can be improved.
[0144]
Further, the yield of the semiconductor integrated circuit device can be improved and the characteristics thereof can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor wafer on which a semiconductor integrated circuit device according to a first embodiment of the present invention is formed.
FIG. 2 is a fragmentary cross-sectional view of a substrate showing a memory cell portion of the semiconductor integrated circuit device according to the first embodiment of the present invention;
3 is an enlarged view of the vicinity of a chip region in FIG. 1;
4 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention; FIG.
FIG. 5 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 6 is a cross-sectional view of the principal part of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 7 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 8 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 10 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 11 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 12 is a fragmentary cross-sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
FIG. 13 is a plan view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;
14 is a cross-sectional view of the principal part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention; FIG.
FIG. 15 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device, for illustrating the effect of the first embodiment of the present invention.
FIG. 16 is a cross-sectional view of the principal part of the substrate, for showing the manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention.
FIG. 17 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device, for illustrating the effect of the first embodiment of the present invention.
FIG. 18 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention.
FIG. 19 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention.
20 is a cross-sectional view of the principal part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention; FIG.
FIG. 21 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention.
FIG. 22 is a substantial part plan view of a substrate, showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 23 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention.
FIG. 24 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for showing the effect of the first embodiment of the present invention.
FIG. 25 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention.
FIG. 26 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device, for illustrating the effect of the first embodiment of the present invention.
27 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention; FIG.
FIG. 28 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device for showing the effect of the first embodiment of the present invention.
FIG. 29 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
30 is a cross-sectional view of the principal part of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention; FIG.
FIG. 31 is a cross-sectional view of the principal part of the substrate showing the manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
32 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention; FIG.
FIG. 33 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
34 is a substantial part plan view of a substrate, showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention; FIG.
FIG. 35 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 3 of the present invention;
FIG. 36 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 3 of the present invention;
FIG. 37 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 3 of the present invention;
FIG. 38 is a substantial part plan view of a substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 3 of the present invention;
FIG. 39 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 4 of the present invention;
40 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 4 of the present invention; FIG.
41 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 4 of the present invention; FIG.
FIG. 42 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 4 of the present invention;
43 is a substantial part plan view of a substrate, showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 4 of the present invention; FIG.
44 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 5 of the present invention; FIG.
45 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 5 of the present invention; FIG.
46 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 5 of the present invention; FIG.
47 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 5 of the present invention; FIG.
48 is a substantial part plan view of a substrate, showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 5 of the present invention; FIG.
49 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 6 of the present invention; FIG.
FIG. 50 is a substantial part plan view of a substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 6 of the present invention;
FIG. 51 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of another semiconductor integrated circuit device which is Embodiment 6 of the present invention;
52 is a substantial part plan view of a substrate, showing a manufacturing process of another semiconductor integrated circuit device according to the sixth embodiment of the present invention; FIG.
FIG. 53 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 7 of the present invention;
54 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 7 of the present invention; FIG.
FIG. 55 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 7 of the present invention;
56 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 7 of the present invention; FIG.
FIG. 57 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 7 of the present invention;
58 is a cross sectional view of the essential part of the substrate, for showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 7 of the present invention; FIG.
FIG. 59 is a substantial part plan view of a substrate, showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 7 of the present invention;
FIG. 60 is a substantial part plan view of a substrate showing a target part of a semiconductor integrated circuit device according to an eighth embodiment of the present invention;
[Explanation of symbols]
1 Semiconductor substrate (substrate)
3 element isolation
5 p-type well
7 Gate insulation film
9, 11 Source and drain regions
13a Polycrystalline silicon film
13b WN film
13c W film
15 Silicon nitride film
17 Silicon nitride film
21 Upper electrode
23 Capacitance insulation film
25 Lower electrode
27a-27e Silicon oxide film
31 Silicon oxide film
32 Silicon oxide film
33 Silicon oxide film
35a Silicon nitride film
35b Silicon oxide film
37a, 37b groove
39 Copper film
41 Passivation film
41a Silicon nitride film
41b Silicon oxide film
42 groove
43 Polyimide resin film
45 Seed layer
47, 47t groove
49 Rewiring
49a Cu film
49b Ni film
51 Polyimide resin film
53 Au film
55 Bump electrode
60 Mounting board
62 Underfill resin
63 groove
BL bit line
C Information storage capacitor
CA chip area
F fuse
FA fuse area
G Gate electrode
M1 first layer wiring
M2 Second layer wiring
M3 3rd layer wiring
M3a TiN film
M3b Al alloy film
M3c TiN film
MA memory area
OA opening
P probe needle
P1 plug
P1a plug
P1b plug
P2 plug
P2a plug
P2b plug
P3 plug
PA peripheral circuit area
PAD1 First pad part
PAD2 Second pad part
Qt MISFET for information transfer
R resist film
RB laser light
RA Redundant memory area
RP reference point
SA scribe area
T target
W Semiconductor wafer

Claims (5)

(A) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region;
(B) forming a second conductive film in the chip region, and forming a third conductive film in the same layer as the second conductive film on the scribe region;
(C) forming a first insulating film on the second and third conductive films;
(D) removing the first insulating film on the second and third conductive films to expose at least a part of the third conductive film, thereby forming a first pad region of the second conductive film; Exposing, and
(E) forming a second insulating film on the second and third conductive films;
(F) exposing the first pad region by removing the second insulating film on the second conductive film, the second conductive film covering the exposed region of the third conductive film; A step of leaving an insulating film;
(G) forming a fourth conductive film extending from the first pad region to the second pad region on the second conductive film;
(H) After the step (g), confirming the position of the exposed region of the third conductive film through the second insulating film, and cutting the first conductive film based on the position When,
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region;
(B) forming a first wiring having a second conductive film and an upper third conductive film in the chip region, and forming the second conductive film and an upper third conductive film in the scribe region; Forming a pattern having:
(C) forming a first insulating film on the first wiring and the pattern;
(D) removing the first insulating film on the first wiring and the pattern to expose the first pad region of the third conductive film constituting the first wiring, and the first constituting the pattern; 3 exposing at least part of the conductive film;
(E) forming a second wiring extending from the first pad region to the second pad region on the first wiring;
(F) After the step (e), cutting the first conductive film based on the position of the exposed region of the pattern;
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region;
(B) forming a groove in the chip region and the scribe region;
(C) forming a second conductive film mainly composed of copper in the groove;
(D) forming a first insulating film on the second conductive film;
(E) removing the first insulating film on the second conductive film in the chip region to expose the first pad region on the second conductive film, thereby exposing the second conductive property in the scribe region; Leaving the first insulating film on the film;
(F) forming a second insulating film on the first insulating film;
(G) exposing the first pad region by removing the second insulating film and exposing the first insulating film in the scribe region;
(H) forming a third conductive film extending from the first pad region to the second pad region on the second conductive film;
(I) After the step (h), confirming the position of the second conductive film in the scribe region through the first insulating film, and cutting the first conductive film based on the position. When,
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) a first conductive film formed in a chip region of a semiconductor substrate;
(B) a second conductive film formed in the chip region;
(C) a third conductive film formed on the outer peripheral portion of the chip region and composed of the same conductive film as the second conductive film;
(D) a first insulating film formed on the second and third conductive films and exposing a first pad region of the second conductive film and at least a part of the third conductive film;
(E) a second insulating film formed on the second and third conductive films and exposing the first pad region;
(F) a third conductive film formed on the second insulating film and extending from the first pad region to the second pad region on the second conductive film;
(G) a bump electrode formed on the second pad region of the third conductive film;
Have
2. The semiconductor integrated circuit device according to claim 1, wherein the second insulating film remains so as to expose the outer peripheral portion and cover an exposed region of the third conductive film. (A) a first conductive film formed in a chip region of a semiconductor substrate;
(B) a second conductive film mainly composed of copper formed in the chip region;
(C) a third conductive film formed on the outer peripheral portion of the chip region and composed of the same conductive film as the second conductive film;
(D) a first insulating film formed on the second and third conductive films, exposing the first pad region of the second conductive film, and covering the third conductive film When,
(E) a second insulating film formed on the second and third conductive films and exposing the first pad region and the outer periphery;
(F) a third conductive film formed on the second insulating film and extending from the first pad region to the second pad region on the second conductive film;
(G) a bump electrode formed on the second pad region of the third conductive film;
A semiconductor integrated circuit device comprising:

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