JP2007067087A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for preventing a fuse element from being affected when a plating bump is formed. <P>SOLUTION: The semiconductor device manufacturing method has a step to cut the required part of the fuse element onto the surface of a substrate 51 via an opening 56a of an insulating layer 56 covering the fuse element 55, a step to cover the fuse element 55 with an etching protection film 57, a step to form a base metal layer 58 for plating-bump formation on the whole face of the substrate 51, a step to remove the base metal layer 58 by etching while leaving an electrode pad forming region, and a step to form the plating bump on the electrode pad. The step to cover the fuse element 55 with the etching protection film 57 is executed prior to the step to remove the base metal layer 58 for plating-bump formation by etching. Consequently, it is possible to protect the fuse element 55 by preventing the fuse element 55 from being eroded with an etchant of the base metal layer 58. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention provides an insulating layer that covers a fuse element portion that forms part of a redundant circuit on a substrate surface, an electrode pad connected to an internal wiring layer via the insulating layer, and a base metal on the electrode pad. The present invention relates to a method for manufacturing a semiconductor device including a plating bump formed through a layer and a semiconductor device.

  For example, in an LSI (Large Scale Integrated Circuit) in which memory and logic of multi-layer wiring are integrated on one chip, a partial circuit failure may occur due to a defect in a manufacturing process. A defective circuit (defective bit) often occurs. Therefore, in order to replace this defective circuit, a redundant circuit (redundant bit) is provided in advance in the LSI. When a defective circuit is found by a test during the manufacturing process, the fuse or fuse connected to the defective circuit is cut to disconnect the defective circuit from the normal circuit, and a redundant circuit is newly created. Connect and substitute.

  On the other hand, as a mounting form of a semiconductor chip in recent years, flip chip mounting in a form of directly bonding onto a wiring board through solder bumps such as plating bumps formed on electrode pads has been adopted. As a method for forming the plating bump, a base metal layer is formed on the substrate surface (element formation surface), and this is used as a seed layer to grow solder plating on the electrode pad by electrolytic plating.

  In the conventional manufacturing method of this type of semiconductor device, after forming the fuse element part in the wafer process and before performing the wafer operation test, all the element regions (chips) are collectively formed on the base metal layer and the plating bump. Since the formation was performed, bump formation was performed not only for the non-defective chip but also for the defective chip, and the material cost could not be reduced and the production efficiency could not be improved.

  Therefore, recently, after forming a redundant circuit and electrode pads including a fuse element portion, and before forming a plating bump, a wafer test and a defective memory cell are inspected to determine a good / defective chip and a fuse blow. (See, for example, Patent Document 1 below). As a result, it is possible to determine whether the wafer is good or defective or to form bumps only on the non-defective chips, so that the production efficiency can be improved.

  FIG. 11A is a schematic cross-sectional view showing the fused fuse element portion. In the figure, 1 is a silicon substrate, 2 is an interlayer insulating film, 3 is a lower wiring layer, 4 is a through hole (interlayer connection hole), 5 is a fuse element portion, and 6 is an insulating film.

  The fuse element portion 5 is a metal wiring layer such as aluminum connected to the lower wiring layer 3 through the through hole 4 and constitutes a part of a redundant circuit that replaces a defective memory cell with a spare memory cell. An opening (window) 6 a for exposing the fuse element portion 5 to the outside is formed in the insulating film 6. In the fuse blow process, laser light is spot-irradiated to the fuse element portion 5 through the opening 6a of the insulating film 6, and the fuse element portion 5 is cut at the fusing portion 5m.

  In this state, a plating bump forming process is performed. Since the formation of the plating bump is performed by an electrolytic plating method, as shown in FIG. 11B, the base metal layer 8 is formed on the substrate surface. The base metal layer 8 is, for example, a Ti / Cu film. Thereafter, a plating resist forming step and a pattern etching step of the base metal layer 8 are performed, and plating bumps are formed on electrode pads (not shown).

JP 2002-110799 A

  However, the conventional plating bump forming method described above has a problem that the fuse element portion 5 is eroded by the etching solution (acid or alkali solution) of the base metal layer 8 during the etching process of the base metal layer 8. is there.

  As a result, as shown in FIG. 12, the fused fuse element portion 5 is corroded and deteriorated. Further, the fuse element portion 5, the through hole 4, the lower wiring layer 3 and the like are usually formed with a titanium film as a base, and these base layers also have an erosion portion 9 around the wiring portion due to the erosion action of the etching solution. Occurs and the wiring area is greatly damaged.

  On the other hand, even in the fuse element portion 5 that is not blown, the etchant of the base metal layer 8 enters through the opening 6a of the insulating film 6, and the fuse element portion is cut by the erosion action of this etchant, etc. There is also a possibility that the circuit configuration of the redundant circuit may vary.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device in which a fuse element portion is not affected when a plating bump is formed.

  In solving the above problems, the method of manufacturing a semiconductor device according to the present invention includes an insulating layer covering a fuse element portion forming a part of a redundant circuit on a substrate surface, and an internal wiring layer connected via the insulating layer. In a method for manufacturing a semiconductor device comprising a formed electrode pad and a plating bump formed on the electrode pad via a base metal layer, a step of cutting a necessary portion of the fuse element portion via the insulating layer A step of covering the fuse element portion with an etching protective film, a step of forming the base metal layer on the entire surface of the substrate, a step of etching away the base metal layer leaving an electrode pad formation region, and the base Forming a plating bump on the metal layer.

  In the present invention, the fuse element portion is eroded by the etching solution of the base metal layer by performing the step of covering the fuse element portion with the etching protective film before the step of etching away the base metal layer for forming the plating bump. The fuse element portion is prevented from being protected.

  When the surface of the fuse element portion is covered with an insulating layer and is processed together with the insulating layer when the fuse is blown, the etching protective film effectively acts on the fused fuse element portion. On the other hand, when an opening (window) is previously formed in the insulating layer corresponding to the fuse element portion, both the fused fuse element portion and the unfused fuse element portion are The etching protective film works effectively.

  Here, the “fuse” is determined depending on whether the electric conductor is set or disconnected, and represents a logical state “0” or “1”. For example, in a semiconductor memory, a defective memory cell is replaced with a spare memory cell. The present invention is applied to a semiconductor device or the like in which a fuse element portion of a redundant circuit that is substituted for is formed.

  As described above, according to the present invention, since the erosion of the fuse element portion during the formation of the plating bump can be prevented, the deterioration of the characteristics of the fuse element portion and the wiring circuit connected thereto can be avoided and the reliability can be improved. Can be planned.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]

  1 to 9 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention (particularly, a semiconductor memory device having memory cells in the present embodiment). In the example shown in the figure, a test electrode area A, a fuse area B, and a bump formation area C on the surface of the semiconductor wafer are shown. Each area includes a test electrode 10, a fuse element portion 20, and an electrode pad 30. It is drawn.

  The test electrode region A is a test electrode for wafer measurement such as evaluation of electrical characteristics of semiconductor elements and evaluation of good / bad of memory cells. The fuse region B constitutes a part of a redundant circuit for replacing a defective memory in the memory cell with a spare memory. The bump formation region C is a region where bumps serving as external terminals of the semiconductor chip are formed, and corresponds to the formation region of the electrode pads of the semiconductor chip.

  As shown in FIG. 1, in the test electrode region A and the bump formation region C, the test electrode 10 and the electrode pad 30 have the same configuration, and the first insulating film is formed on the semiconductor substrate (silicon substrate) 40. The internal wiring layer 44 formed via 41 is electrically connected to each other. The test electrode 10 and the electrode pad 30 are respectively formed on the second insulating film 42 covering the internal wiring layer 44. A third insulating film 43 is formed on the second wiring layer 42 so as to cover the peripheral edges of the test electrode 10 and the electrode pad 30.

  On the other hand, in the fuse region B, the fuse element portion 20 is made of aluminum and is formed as a part of the wiring portion of the internal wiring layer 44. After the fuse element portion 20 is entirely covered with the second insulating film 42 and the third insulating film 43, the fuse element portion 20 is exposed to the outside through an opening 42 a in which a part of the insulating films 42 and 43 is opened. The opening 42a is formed as a fuse blow window. In the illustrated example, an upper wiring layer 45 is formed around the fuse element portion 20, and adjacent wirings are insulated by the third insulating film 43.

  Next, from the state shown in FIG. 1, the plating bump forming process will be described below.

(Wafer test process)
In the present embodiment, an operation test of each element on the wafer is performed before the plating bump is formed. This test is performed by bringing a prober (not shown) into contact with the test electrode 10. By this step, good chips and defective chips on the wafer are specified. In FIG. 2, a recess 10a formed on the surface of the electrode pad 10 indicates a pressing mark of the prober.

  Further, in this wafer test process, the memory cells in each chip area are evaluated, and the fuse element portion 20 to be blown is specified in order to switch the determined defective memory cell to the alternative memory cell.

(Fuse blow process)
As shown in FIGS. 2 and 3, the fuse blow process irradiates the fuse element portion 20 exposed to the outside through the opening 42 a of the fuse region B with a laser beam L, so that a predetermined fuse element portion is formed. 20 is blown. The fuse element portion 20 is opened by forming the fusing portion 20m, and the previously determined defective memory cell is replaced with a predetermined spare memory cell.

(Etching protective film formation process)
Subsequently, an etching protective film 47 is formed on the fuse element portion 20 as shown in FIG. The etching protection film 47 is insoluble in an etching solution used in the etching process of the base metal layer 49 (FIG. 7) necessary for forming the plating bump, and is for protecting the fuse element portion 20 from this etching solution. Is provided. In the present embodiment, an insulating film such as a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film) is used for the etching protection film 47.

  The etching protective film 47 is formed by a vacuum thin film forming process such as a CVD method. The etching protection film 47 is formed along the step portion of the opening 42a in the fuse region B and covers the fuse element portion 20 facing the opening 42a. As a result, the fuse element portion 20 and its fusing portion 20m are shielded from the outside by the etching protection film 47. The film thickness of the etching protective film 47 is not particularly limited.

  Since the etching protection film 47 is formed of an insulating film and is intended to protect the fuse element portion 20, the etching protection film 47 in the region other than the opening 42a in the fuse region B is removed. In the patterning of the etching protective film 47, after applying a resist material to the substrate surface, as shown in FIG. 5, a resist pattern 48 is formed to mask the site where the opening 42a is formed. Then, the etching protection film 48 is removed by etching using the resist pattern 48 as a mask (FIG. 6), and then the resist pattern 48 is removed. As a result, only the opening 42 a in the fuse region B is covered with the etching protective film 47.

(Base metal layer formation process)
Next, as shown in FIG. 7, the base metal layer 49 of the plating bump 50 (FIG. 9) is formed on the substrate surface. In the present embodiment, the base metal layer 49 is formed of a laminated film of a Ti film and a Cu film. The base metal layer 49 is formed on the entire surface of the substrate by sputtering, electroless plating, or the like.

  Since the base metal layer 49 is formed as a seed layer (feeding layer) necessary for forming the plating bump 50, as shown in FIG. 8, only the base metal layer is formed on the electrode pad 30 in the bump formation region C. The underlying metal layer 49 on the other region is removed so that 49 remains. The base metal layer 49 is patterned by forming a resist pattern that masks the bump formation region C using a photolithography technique, and then wet etching using immersion in an etchant or spraying of an etchant onto the substrate surface. Adopted.

  The etching solution used for patterning the base metal layer 49 is not particularly limited, but an acid solution and alkaline peroxide water are used in this embodiment. The former is used for removing the Cu layer constituting the base metal layer 49, and the latter is used for removing the Ti layer.

  According to the present embodiment, since the opening 42a of the fuse region B is covered with the etching protection film 47, the fuse element portion 20 made of aluminum is protected from the etching solution when the base metal layer 49 is patterned. Therefore, the fuse element portion 20 is prevented from being eroded or corroded by contact with the etching solution, and the etching solution is not eroded to the internal wiring layer 44 via the fuse element portion 20. As a result, the fuse element portion 20 and the redundant circuit including the fuse element portion 20 are not affected during the plating bump formation process, and reliability is ensured.

(Plating bump formation process)
Subsequently, as shown in FIG. 9, a step of forming the plating bump 50 in the bump forming region C is performed. The plating bump 50 is made of solder plating, and is formed on the electrode pad 30 via the base metal layer 49 by an electrolytic plating method.

  As described above, according to the present embodiment, the fuse element portion 20 can be effectively protected from the etching solution during the patterning etching of the base metal layer 49, so that deterioration due to corrosion of the fuse element portion can be prevented. Can do. Thereby, the reliability of the redundant circuit including the fuse element portion can be improved.

  In addition, since all the openings 42a in the fuse region B are covered with the etching protection film 47, the fuse element portion 20 can be protected from the etching solution regardless of whether the fuse element portion 20 is blown or not blown.

  Further, since the fuse element portion 20 is covered with the etching protection film 20 even after the plating bump 50 is formed, the fuse element portion 20 is protected by etching even when it is separated into individual chips and mounted on the wiring board. It can be protected by the film 47. Thereby, for example, it is avoided that the underfill resin or the mold resin directly contacts the fuse element portion 20. In particular, when an insulating film having a high moisture barrier property such as a SiN film is applied as the etching protection film 47, the fuse element portion 20 can be effectively shielded from moisture in the resin.

  According to the present embodiment, since the plating bump is formed after the wafer test and the fuse blow, it is possible to form the plating bump 50 only on the non-defective chip. It is possible to shorten the formation process time, improve the yield and productivity.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. 10A and 10B show a second embodiment of the present invention.

  FIG. 10A shows a state in which an etching protective film is formed on the fuse element portion that has been blown. In the figure, 51 is a silicon substrate, 52 is an interlayer insulating film, 53 is a lower wiring layer, 54 is a through hole, 55 is a fuse element portion, 56 is an insulating film, and 57 is an etching protective film.

  When the plating bump is formed, both the fusing part 55m of the fuse element part 55 and the opening part 56a of the insulating film 56 that opens the fuse element part 55 are covered with the etching protective film 57 (FIG. 10A). Thereafter, the base metal layer 58 of the plating bump is formed on the substrate surface as described above (FIG. 10B), and the base metal layer 58 on the formation region of the fuse element portion 55 is removed by etching.

  In this embodiment, the etching protection film 57 is formed of a planarizing film such as photosensitive polyimide, and the fusing part 55m of the fuse element part 55 and the opening part 56a of the insulating film 56 are filled with the etching protection film 57. At the same time, the substrate surface is flattened. As a result, it is possible to eliminate the level difference of the base metal layer 58 immediately above the opening 56a, thereby achieving flattening. Therefore, it is possible to shorten the etching time of the subsequent base metal layer 58 and to facilitate and ensure the etching process. It becomes possible. Then, it is possible to prevent the film residue of the base metal layer 58 around the opening 56a and to optimize the process.

  The embodiments of the present invention have been described above. Of course, the present invention is not limited to these embodiments, and various modifications can be made based on the technical idea of the present invention.

  For example, in the above embodiment, a silicon oxide film or a silicon nitride film is used as the etching protective film, but the present invention is not limited to this, and can be appropriately changed according to the type of the etchant for the underlying metal layer.

  The etching protective film according to the present invention is not limited to being formed of a material that is insoluble in the etching solution for the underlying metal layer, and a material that dissolves in the etching solution but has a relatively low etching rate can be used. That is, it is possible to obtain the same effect as described above by using a material that can exhibit selectivity with respect to the etching solution regardless of whether it is soluble or insoluble.

  In the above embodiment, the constituent material of the fuse element portion is aluminum, but other conductive materials can be used. Then, the constituent material of the etching protective film may be appropriately selected according to the combination of the base metal layer and the etching solution.

  Further, in the above embodiment, the example in which the present invention is applied to the fuse element portion constituting a part of the redundant circuit that replaces the defective cell of the memory cell with the spare memory cell has been described. The present invention is also applicable to the manufacture of a semiconductor device having a fuse and a fuse element portion used for encoding information such as a fuse and ID.

It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the fuse blow process. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the state after a fuse blow process. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the formation process of an etching protective film. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the patterning process of the etching protective film. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the patterning process of the etching protective film. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the formation process of the base metal layer of a plating bump. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the patterning process of a base metal layer. It is process drawing explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and has shown the formation process of a plating bump. It is process drawing explaining the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. It is process drawing explaining the manufacturing method of the conventional semiconductor device. It is a cross-sectional schematic diagram of the fuse part explaining the problem of a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Test electrode 20, 55 ... Fuse element part, 20m, 55m ... Fusing part, 30 ... Electrode pad, 40 ... Board | substrate, 42, 43 ... Insulating layer, 42a, 56a ... Opening part, 44 ... Internal wiring layer, 47 , 57 ... Etching protective film, 49 and 58 ... Under metal layer, 50 ... Plating bump, A ... Test electrode area, B ... Fuse area, C ... Bump formation area

Claims (7)

An insulating layer that covers the fuse element portion forming a part of the redundant circuit on the surface of the substrate, an electrode pad connected to the internal wiring layer through the insulating layer, and a base metal layer on the electrode pad In the manufacturing method of the semiconductor device provided with the formed plating bump,
Cutting a necessary portion of the fuse element portion through the insulating layer;
Coating the fuse element portion with an etching protective film;
Forming the base metal layer on the entire surface of the substrate;
Etching away the underlying metal layer leaving the electrode pad formation region;
Forming the plating bump on the base metal layer. A method for manufacturing a semiconductor device. The fuse element portion is partially exposed through an opening formed in the insulating layer, and the etching protection film is formed so as to cover the opening. Item 14. A method for manufacturing a semiconductor device according to Item 1. The method for manufacturing a semiconductor device according to claim 1, wherein the etching protection film is formed as a planarization film filling the opening. The method for manufacturing a semiconductor device according to claim 1, wherein an insulating material that is insoluble in an etching solution for the base metal layer is used for the etching protection film. An insulating layer that covers the fuse element portion forming a part of the redundant circuit on the surface of the substrate, an electrode pad connected to the internal wiring layer through the insulating layer, and a base metal layer on the electrode pad In a semiconductor device provided with formed plating bumps,
The insulating layer has an opening for cutting the fuse element portion,
The opening is covered with a protective film that shields the fuse element portion from the outside. The semiconductor device according to claim 5, wherein the protective film is formed along a step portion of the opening. The semiconductor device according to claim 5, wherein the protective film is formed as a planarizing film that fills a step portion of the opening.

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