KR101055857B1

KR101055857B1 - Method for manufacturing a semiconductor device having a fuse and a pad

Info

Publication number: KR101055857B1
Application number: KR1020080066618A
Authority: KR
Inventors: 이상도
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-07-09
Filing date: 2008-07-09
Publication date: 2011-08-09
Also published as: KR20100006407A

Abstract

The present invention relates to a method of manufacturing a semiconductor device having a fuse and a pad. The method of manufacturing a semiconductor device including a fuse and a pad of the present invention provides a method for forming a first insulating film on a substrate having a fuse area and a pad area. step; Etching the first insulating layer of the pad opening predetermined region exposed by at least a mask pattern for repair / pad etching among the pad regions; Forming a conductive film for metal wiring on the first insulating layer and patterning the conductive film to form a pad in the pad area, the pad being located lower than the fuse in the fuse area; Forming a second insulating film on the entire structure of the resultant product including the fuse and the pad; Etching the second insulating layer until the pad is not exposed while the fuse is exposed as an etching barrier using the mask pattern for the repair / pad etching; Removing a predetermined thickness of an upper portion of the exposed fuse; And etching the second insulating layer until the pad is exposed as an etching barrier using the mask pattern for the repair / pad etching, wherein the fuse and the pad according to the present invention are provided. By adjusting the thickness of the fuse and the pad to the desired thickness while performing repair / pad etching using the same mask, it is possible to facilitate the subsequent laser repair process and the wire bonding process and to prevent an increase in the process cost.

Fuses, Pads, Repair / Pad Etching, Laser Repair, Wire Bonding

Description

The manufacturing method of the semiconductor device provided with a fuse and a pad {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH FUSE AND PAD}

TECHNICAL FIELD This invention relates to the manufacturing technique of a semiconductor element. Specifically, It is related with the manufacturing method of the semiconductor element provided with fuse and pad.

In the manufacture of a semiconductor memory device, if any one of a number of fine cells is defective, it does not function as a memory and thus is treated as a defective product. However, even though only a few cells in the memory have failed, discarding the entire device as defective is very inefficient in terms of yield.

Therefore, the current yield is improved by replacing the defective cells by using the redundancy cells pre-installed in the memory. In more detail, a test is performed to determine whether the cells formed on the substrate are defective, and as a result, the cells determined to be defective are removed by fuse cutting by a laser beam through a repair process and the redundancy in the chip is removed. Replaced by a Duncy cell. Here, the fuse is not formed by using separate wiring, but is formed by using general circuit wiring (for example, word line, bit line, plate line, etc.), and in recent years, it is particularly formed using metal wiring. .

On the other hand, the etching process for forming an opening that exposes the fuse, that is, a fuse box for irradiating a laser beam to the fuse, and the etching process for exposing the pad for signal input and output of the semiconductor device are one etching process. This is called a repair / pad etching process.

1A and 1B are cross-sectional views illustrating a repair / pad etching process according to the prior art. In particular, in this figure, the case where a fuse and a pad are formed using the same metal wiring is demonstrated.

As shown in FIG. 1A, a metal wiring metal film (for example, Al) is formed on a substrate 10 having a fuse region and a pad region, and a predetermined lower structure is formed, and then patterned by a mask and an etching process. The first metal wiring 11 is formed.

Subsequently, the first interlayer insulating film 12 is formed on the entire structure of the resultant product including the first metal wiring 11, and then connected to the first metal wiring 11 through the first interlayer insulating film 12. The metal contact 13 is formed.

Subsequently, a metal film for metal wiring (for example, Al) is formed on the first interlayer insulating layer 12 on which the metal contact 13 is formed, and then patterned by a mask and an etching process to form a second metal wiring. Here, the portion formed in the fuse region of the second metal wiring is hereinafter referred to as fuse 14A, and the portion formed in the pad region of the second metal wiring is hereinafter referred to as pad 14B.

Subsequently, the second interlayer insulating film 15 is formed on the entire structure of the resultant product in which the fuse 14A and the pad 14B are formed. The second interlayer insulating film 15 may be formed of an oxide film. Although not shown, a protective film made of polyimide may be further formed on the second interlayer insulating film 15.

Subsequently, a mask pattern 16 for repair / pad etching is formed on the second interlayer insulating layer 15.

As shown in FIG. 1B, the insulating layers below (the second interlayer insulating layer 15 and the first interlayer insulating layer 12) are exposed until the fuse 14A and the pad 14B are exposed to the mask pattern 16 as an etch barrier. Repair / pad etching to etch a portion) to form a pad opening B for exposing the pad 14B to the pad area while forming a fuse opening A for exposing the fuse 14A to the fuse area. . In particular, as shown in this figure, it is preferable that the fuse 14A is completely opened during repair / pad etching.

Subsequently, the upper portion of the fuse 14A is partially etched and removed until the exposed fuse 14A remains at a predetermined thickness (see " t1 "). This is because the subsequent laser repair efficiency can be increased only by reducing the thickness of the fuse 14A. In this case, since the fuse 14A as well as the pad 14B in the pad region are exposed together with the repair / pad etching, the fuse 14A and the pad 14B are formed using the same metal wire, and thus the fuse 14A may be formed. The top of the pad 14B is also etched and removed at the same time.

However, in general, when the thickness of the pad 14B becomes thin, problems such as cracking occur in a subsequent wire bonding process, and therefore, the thickness of the pad 14B exposed by the pad opening B is thick. It is preferable.

In summary, a technique is required in which the thickness of the fuse 14A is relatively thin and the thickness of the pad 14B is relatively thick. However, when repair / pad etching is performed using the same mask as described above, it is very difficult to adjust the thicknesses of the fuse 14A and the pad 14B, respectively. As such, it is not desirable to perform repair and pad etching separately using different masks because this increases process costs.

The present invention has been proposed to solve the above problems of the prior art, by performing the repair / pad etching using the same mask while adjusting the thickness of the fuse and the pad to the desired thickness, respectively, subsequent laser repair process and wire bonding process To provide a method for manufacturing a semiconductor device having a fuse and a pad that can facilitate the increase and prevent the increase of the process cost.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a fuse and a pad, the method including: forming a first insulating film on a substrate having a fuse region and a pad region; Etching the first insulating layer of the pad opening predetermined region exposed by at least a mask pattern for repair / pad etching among the pad regions; Forming a conductive film for metal wiring on the first insulating layer and patterning the conductive film to form a pad in the pad area, the pad being located lower than the fuse in the fuse area; Forming a second insulating film on the entire structure of the resultant product including the fuse and the pad; Etching the second insulating layer until the pad is not exposed while the fuse is exposed as an etching barrier using the mask pattern for the repair / pad etching; Removing a predetermined thickness of an upper portion of the exposed fuse; And etching the second insulating layer until the pad is exposed as an etching barrier using the mask pattern for the repair / pad etching.

In the method of manufacturing a semiconductor device having a fuse and a pad according to the present invention, a laser repair process and a wire are performed by adjusting the thicknesses of the fuse and the pad to a desired thickness while performing repair / pad etching using the same mask. The bonding process can be facilitated and the increase in process cost can be prevented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device including a fuse and a pad according to an embodiment of the present invention.

As shown in FIG. 2A, a metal wiring metal film (for example, Al) is formed on a substrate 20 having a fuse region and a pad region, and a predetermined lower structure is formed, and then patterned by a mask and an etching process. The first metal wiring 21 is formed.

Subsequently, a first interlayer insulating film 22 is formed on the entire structure of the resultant product including the first metal wiring 21. It is preferable that the 1st interlayer insulation film 22 consists of an oxide film.

Next, a metal contact 23 is formed to penetrate through the first interlayer insulating film 22 and to be connected to the first metal wiring 21. In more detail, the first interlayer insulating layer 22 may be selectively etched to form a first opening (see “h1”) exposing the first metal wiring 21, and then the first opening h1 may be formed. The metal contact 23 is formed by filling the conductive material in the.

In addition, the first interlayer insulating layer 22 of the pad region exposed by the mask pattern for at least subsequent repair / pad etching is etched to a predetermined depth to form a second opening (see “h2”). Hereinafter, the pad area exposed by the mask pattern for repair / pad etching is referred to as a 'pad opening predetermined area', which is shown in FIG. 2B. Here, the width W2 of the second opening h2 may have a value equal to or larger than the width of the pad opening predetermined region, and may have various shapes such as a hole type or a quadrangle.

The etching process for forming the first opening h1 and the second opening h2 may be simultaneously performed, and in this case, the depths of the first opening h1 and the second opening h2 may have the same value. have.

As shown in FIG. 2B, a metal film for metal wiring (for example, Al) is formed along the lower profile on the resultant product in which the second opening h2 is formed, and then patterned by a mask and an etching process to form a second film. Form metal wiring. Here, a part formed in the fuse region of the second metal wiring is hereinafter referred to as fuse 24A, and a part formed in the pad region of the second metal wiring is hereinafter referred to as pad 24B. At this time, a step d occurs between at least the pad 24B and the fuse 24A in the pad opening predetermined region by the second opening h2. That is, the fuse 24A exists at a higher position than the pad 24B in the pad opening predetermined region.

Next, a second interlayer insulating film 25 is formed on the entire structure of the resultant product in which the fuse 24A and the pad 24B are formed. The second interlayer insulating film 25 may be formed of an oxide film. Although not shown in the drawing, a protective film made of polyimide may be further formed on the second interlayer insulating film 25.

Subsequently, a mask pattern 26 for repair / pad etching is formed on the second interlayer insulating layer 25. The pad area exposed by the mask pattern 26 becomes the pad opening predetermined area described above. The width of the pad opening predetermined area is denoted as W1, and W1 has a value smaller than or equal to the width W2 of the second opening h2 as described above.

As shown in FIG. 2C, the second interlayer insulating layer 25 may be formed by performing a first repair / pad etching on the mask pattern 26 as an etch barrier, but not to expose the pad 24B while the fuse 24A is exposed. To etch). As a result, the primary fuse opening C1 and the primary pad opening D1 are formed. In particular, the pad 24B is not exposed by the primary pad opening D1. Such etching is possible because the fuse 24A is located at a higher position than the pad 24B as described above. Primary repair / pad etching may be performed using a mixed plasma of CF ₄ / CHF ₃ / O ₂ / Ar.

As shown in Fig. 2D, the upper portion of the fuse 24A is partially etched and removed until the exposed fuse 24A remains at the desired predetermined thickness t2. This is because the subsequent laser repair efficiency can be increased only by reducing the thickness of the fuse 24A. Here, since the second interlayer insulating film 25 remains on the pad 24B, the thickness of the pad 24B is maintained despite the etching process of the fuse 24A. The etching of the fuse 24A may be performed using a mixed plasma of Cl ₂ / Ar.

As a result, the thickness of the fuse 24A can be adjusted separately from the thickness of the pad 24B.

As shown in Fig. 2E, the mask pattern 26 is subjected to secondary repair / pad etching as an etching barrier, which is performed until the pad 24B is exposed. As a result, a secondary fuse opening C2 exposing the fuse 24A and a secondary pad opening D2 exposing the pad 24B are finally formed. Such secondary repair / pad etching may be performed using a mixed plasma of CF ₄ / CHF ₃ / O ₂ / Ar.

As a result of this process, the fuse 24A in the fuse area can have a relatively thin thickness, and the pad 24B in the pad area can have a relatively thick thickness. Accordingly, it is possible to prevent a problem such as cracking during wire bonding while increasing the laser repair efficiency. In addition, since repair / pad etching is performed using the same mask pattern 26, an increase in process cost may be prevented.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B are cross-sectional views illustrating a repair / pad etching process according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a fuse and a pad according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: substrate 21: first metal wiring

22: first interlayer insulating film 23: metal contact

24A: Fuse 24B: Pad

25 second interlayer insulating film 26 mask pattern

Claims

Forming a first insulating film on the substrate having a fuse region and a pad region;

Etching the first insulating layer of a predetermined area of the pad opening to be exposed by a mask pattern for repair / pad etching of the pad area to form an opening;

Forming a conductive layer for metal wiring on the first insulating layer having the opening and patterning the conductive layer to form a pad in the pad region, the pad being positioned lower than the fuse in the fuse region;

Forming a second insulating film on the entire structure of the resultant product including the fuse and the pad;

Etching the second insulating layer until the pad is not exposed while the fuse is exposed as an etching barrier using the mask pattern for the repair / pad etching;

Removing a predetermined thickness of an upper portion of the exposed fuse; And

Etching the second insulating layer until the pad is exposed as an etching barrier using a mask pattern for etching the repair / pad

Method of manufacturing a semiconductor device having a fuse and a pad comprising a.

Claim 2 has been abandoned due to the setting registration fee.

The method of claim 1,

Before the first insulating film forming step,

Method for manufacturing a semiconductor device comprising a fuse and a pad further comprising.

Claim 3 was abandoned when the setup registration fee was paid.

The method of claim 2,

After the first insulating film forming step,

Selectively etching the first insulating layer of the pad region to form a contact hole exposing the predetermined wiring; And

Embedding a conductive film in the contact hole to form a contact for connecting the predetermined wire and the pad;

A manufacturing method of a semiconductor device having a fuse and a pad.

Claim 4 was abandoned when the registration fee was paid.

The method of claim 3, wherein

The forming of the contact hole and the etching of the first insulating layer of the pad opening predetermined region are simultaneously performed.

A manufacturing method of a semiconductor device having a fuse and a pad.

Claim 5 was abandoned upon payment of a set-up fee.

The method of claim 1,

The etching step of using the mask pattern for the repair / pad etching as an etching barrier is performed using a mixed plasma of CF ₄ / CHF ₃ / O ₂ / Ar.

A manufacturing method of a semiconductor device having a fuse and a pad.

Claim 6 was abandoned when the registration fee was paid.

The method of claim 1,

The metal conductive film includes Al,

Removing the upper portion of the fuse by a predetermined thickness may be performed using a mixed plasma of Cl ₂ / Ar.

A manufacturing method of a semiconductor device having a fuse and a pad.