KR100675296B1 - Semiconductor device having fuse pattern and methods of fabricating the same - Google Patents

Abstract

Provided are a semiconductor device having a fuse pattern and methods of manufacturing the same. These methods include preparing a semiconductor substrate having a fuse region, a wiring region and a pad region. A conductive film is formed on the semiconductor substrate. The conductive film in the fuse region is partially etched to form a fuse conductive film having a thickness thinner than that of the conductive film. The conductive layer and the fuse conductive layer are patterned to form a first conductive pattern in the fuse region and to form a second conductive pattern in the wiring region.

Fuse pattern, partial etching, fuse conductive film, conductive pattern, fuse window, pad window, metal wiring

Description

Semiconductor device having fuse pattern and methods of fabricating the same

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2 is a plan view of a semiconductor device according to example embodiments.

3A to 3F are cross-sectional views taken along the line II ′ of FIG. 2 to explain a method of manufacturing a semiconductor device according to example embodiments.

4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with other embodiments of the present invention.

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a fuse pattern and a manufacturing method thereof.

The semiconductor memory devices formed on the semiconductor substrate are electrically tested before the assembly process. As a result, the semiconductor memory devices are classified as bad chips or good chips. If the defective chips malfunction by at least one defective cell, the defective cell is replaced with a redundant cell using a repair process. The repair process includes a laser beam irradiation step of blowing certain fuses in write mode and read mode to ensure that the spare cell has the address of the defective cell. The fuses are generally formed at the same time as the bit lines or the metal wires of the semiconductor memory device.

As semiconductor devices become highly integrated and multi-layered, the thickness of an oxide film to be etched to form a fuse window increases. Therefore, it is difficult to form a fuse at the same time as the bit line, and recently, a metal fuse formed at the same time as the metal wiring has been studied. The metal wiring is formed thicker than the bit line to lower the resistance. Therefore, since the metal fuse formed by being patterned at the same time as the metal wire is also formed thicker than the bit line fuse, high energy is required to blow the metal fuse. In addition, due to the thick thickness of the metal fuse, there is a problem that the blown remaining material of the metal fuse may cause a bridge with an adjacent metal fuse after blowing. Therefore, a thin metal fuse is required to reduce the bridge with the adjacent metal fuse and to reduce the energy required for blowing.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art. 1A to 1D, portions denoted by reference numerals “I0”, “F0” and “P0” represent wiring regions, fuse regions, and pad regions, respectively.

Referring to FIG. 1A, an interlayer insulating film 115 is formed on a semiconductor substrate 110. A barrier layer 120, a metal layer 123, and a capping layer 125 are sequentially formed on the interlayer insulating layer 115. The barrier film 120 may be formed of a titanium nitride film or a titanium film and a titanium nitride film stacked in sequence. The metal film 123 is formed of an aluminum film. The capping film 125 may be formed of a titanium film or a titanium film and a titanium nitride film that are sequentially stacked.

Referring to FIG. 1B, the capping layer 125, the metal layer 123, and the barrier layer 120 are sequentially patterned to sequentially stack the barrier pattern 120a and the metal pattern 123a in the fuse region F0. ) And the preliminary fuse patterns 127a including the capping pattern 125a and the barrier pattern 120b, the metal pattern 123b, and the capping pattern 125b that are sequentially stacked in the wiring region I0. The configured first metal wires 127b are formed.

A metal interlayer insulating film 133 is formed on the semiconductor substrate having the preliminary fuse patterns 127a and the first metal wires 127b. Via contact plugs 134 may be formed through the metal interlayer insulating layer 133 to be electrically connected to the first metal wires 127b. An upper barrier layer, an upper metal layer, and an upper capping layer are sequentially formed on the substrate having the via contact plugs 134. The upper capping layer, the upper metal layer, and the upper barrier layer are sequentially patterned to form second metal interconnections 140 on the metal interlayer insulating layer 133 in the interconnection region 10. A pad 140p is formed on the metal interlayer insulating film 133 in P0).

The second metal wires 140 may include an upper barrier pattern 135, an upper metal pattern 137, and an upper capping pattern 139 that are sequentially stacked. The second metal wires are electrically connected to the first metal wires 127b through the via contact plugs 134, respectively. The pad 140p includes a pad conductive pattern 138p and a pad capping pattern 139p that are sequentially stacked, and the pad conductive pattern 138p is a pad barrier pattern 135p and a pad metal pattern 137p that are sequentially stacked. It consists of.

A passivation layer 143 is formed on the substrate having the second metal wires 140 and the pad 140p. The passivation film 143 may be formed of a plasma oxide film 141 and a plasma nitride film 142 that are sequentially stacked.

Referring to FIG. 1C, the passivation layer 143 in the fuse region F0 is etched using a photolithography process and an etching process, and the metal interlayer dielectric layer 133 below is partially etched to form the capping patterns. A fuse window 145f exposing 125a is formed. Subsequently, the exposed capping patterns 125a are etched and removed, and the metal patterns 123a under the capping patterns 125a are partially etched to have a thickness thinner than that of the preliminary fuse patterns 127a. Patterns 127a 'are formed. The fuse patterns 127a 'may include the barrier pattern 120a and the partially etched metal pattern 123a' that are sequentially stacked. At the same time, the passivation layer 143 and the predetermined region of the pad capping pattern 139p in the pad region P0 are sequentially etched to form a pad window 145p exposing the pad conductive pattern 138p. In this case, the pad metal pattern 137p may be partially etched.

A conformal fuse protection film 147 is formed on a substrate having the fuse patterns 127a '. As a result, the fuse protection layer 147 is formed to cover the entire surface of the passivation layer 143, the inside of the fuse window 145f, and the inside of the pad window 145p. The fuse protection layer 147 may be formed of a silicon nitride layer. The fuse protection layer 147 is formed to protect the exposed fuse patterns 127a '.

Referring to FIG. 1D, the fuse protection layer 147 is selectively patterned to expose the pad conductive pattern 138p under the pad window 145p. Subsequently, after forming a polyimide film on the substrate on which the pad conductive pattern 138p is exposed, an exposure process and a development process are performed to expose the fuse window 145f and the pad window 145p, respectively. Polyimide pattern 150 having 150f and pad window opening 150p is formed. The semiconductor device is electrically tested before the assembly process. In this case, the defective cells undergo a repair process by irradiating a laser through the fuse window opening 150f and the fuse window 145f. Then, in the assembly process, the pad bonding operation is performed through the pad window opening 150p and the pad window 145p.

According to the above-described conventional technique, the preliminary fuse patterns 127a may be unevenly etched while the metal interlayer insulating layer 133 is etched. As a result, as shown in FIG. 1C, upper surfaces of the fuse patterns 127a ′ may have a nonuniform upper surface due to the non-uniform etching, and may have a nonuniform thickness. In addition, the fuse patterns 127a ′ may have different thicknesses in the same wafer due to non-uniform etching between the preliminary fuse patterns 127a. For example, a reference 'A0' fuse pattern may be thicker than a reference 'B0' fuse pattern. As a result, even when the fuses are blown with the same energy, even though the 'B0' fuse pattern is blown, the 'A0' fuse pattern is thicker than the 'B0' fuse pattern. Can also be.

In addition, after the fuse patterns 127a 'are formed, as the fuse protection layer 147 is formed, a photoresist process for exposing the pad conductive pattern 138p is added. In addition, the polyimide pattern 150 process is also performed separately. As a result, the fuse window, the pad window, and the polyimide pattern process are separately performed, and the production cost increases because the photo process is performed three times.

Therefore, there is a need for a method of fabricating a semiconductor device having a fuse pattern in which each fuse pattern has a flat top surface and improves the thickness uniformity of the fuse patterns in the same wafer and can simplify the photo process. .

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device having a fuse pattern having a flat top surface and having a fuse pattern suitable for improving thickness uniformity of the fuse patterns in the same wafer and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device having a fuse pattern suitable for shortening a photo process in forming a fuse pattern, a fuse window, and a pad window, and a method of manufacturing the same.

According to one aspect of the present invention, a semiconductor device having a fuse pattern is provided. The semiconductor device includes a semiconductor substrate having a fuse region and a wiring region. A fuse pattern including a first metal pattern and a first capping pattern sequentially stacked on the fuse region of the semiconductor substrate is disposed. A metal wiring including a second metal pattern and a second capping pattern, which are sequentially stacked in the wiring region of the semiconductor substrate, is disposed. The first metal pattern has a thickness thinner than the second metal pattern.

In some embodiments of the present invention, the first and second capping patterns may be anti-reflection films.

In other embodiments, the first metal pattern and the second metal pattern may be at least one material film selected from a group consisting of an aluminum film, a tungsten film, and a copper film.

In still other embodiments, the thickness of the second capping pattern may be equal to or thicker than the first capping pattern.

In other embodiments, the first capping pattern and the second capping pattern may be titanium nitride (TiN).

In another embodiment, the fuse pattern may further include a first interface pattern interposed between the first metal pattern and the first capping pattern.

In other embodiments, the metal wire may further include a second interface pattern interposed between the second metal pattern and the second capping pattern.

In still other embodiments, the fuse pattern and the metal wire may further include first and second barrier patterns respectively disposed below the first and second metal patterns.

In other embodiments, the fuse pattern and the metal line may be disposed on the same level.

In another example embodiment, the semiconductor device may further include an oxide layer covering the fuse pattern and the fuse patterns of the fuse area and having a flat upper surface.

According to another aspect of the present invention, methods of manufacturing a semiconductor device having a fuse pattern are provided. These methods include preparing a semiconductor substrate having a fuse region, a wiring region and a pad region. A conductive film is formed on the semiconductor substrate. The conductive film in the fuse region is partially etched to form a fuse conductive film having a thickness thinner than that of the conductive film. The conductive layer and the fuse conductive layer are patterned to form a first conductive pattern in the fuse region and to form a second conductive pattern in the wiring region.

In some embodiments of the present disclosure, further comprising forming a lower capping layer on the conductive layer before partially etching the conductive layer, wherein the lower capping layer in the fuse region is removed in the step of partially etching the conductive layer. The lower capping layer in the wiring region may be patterned to form the lower capping pattern in the forming of the second conductive pattern. Forming a lower interface film between the conductive film and the lower capping film, wherein the lower interface film in the fuse region is removed in the step of partially etching the conductive film, and the lower interface film in the wiring region is the second In the step of forming the conductive pattern may be patterned to form a lower interface pattern.

In another embodiment, after forming the fuse conductive layer, the method may further include forming an upper capping layer on the substrate having the fuse conductive layer, wherein the upper capping layer is patterned in forming the first and second conductive patterns. Thus, first and second upper capping patterns may be formed on the first and second conductive patterns, respectively. The upper capping layer may be formed of a titanium nitride layer TiN. The upper capping layer may be an antireflection layer. Before forming the upper capping layer, the method may further include forming an upper interface layer on the substrate having the fuse conductive layer, wherein the upper interface layer is patterned in the forming of the first and second conductive patterns. First and second upper interface patterns may be formed on the second conductive patterns, respectively.

In still other embodiments, the conductive film may be formed of a metal film or a barrier film and a metal film that are sequentially stacked. The metal film may be formed of at least one material film selected from a group consisting of an aluminum film, a tungsten film, and a copper film.

In still other embodiments, a pad including a pad conductive pattern and a pad capping pattern may be formed on a substrate having the first and second conductive patterns, and then sequentially stacked on the metal interlayer insulating layer in the pad region. Can be formed. The passivation film can be formed on the substrate having the pad. Subsequently, the passivation layer, the pad capping pattern, and the metal interlayer insulating layer are etched to form a fuse window in the fuse region so that a predetermined thickness of the metal interlayer insulating layer remains on the first conductive pattern. A pad window exposing the pad conductive pattern may be formed.

In still other embodiments, the forming of the fuse window and the pad window may include forming a polyimide film on the passivation film, and exposing and developing the polyimide film to a predetermined area of the fuse area and the pad area. The method may include forming a polyimide pattern having openings exposing the portions, and etching the passivation layer, the pad capping pattern, and the metal interlayer insulating layer using the polyimide pattern as an etching mask.

In example embodiments, the forming of the fuse window and the pad window may etch the passivation layer to expose the pad capping pattern of the interlayer insulating layer and the wiring area of the fuse area, and expose the exposed pad capping pattern. Etching to expose the pad conductive pattern of the wiring area, and partially etching the exposed metal interlayer insulating film of the fuse area.

In another embodiment, the metal interlayer insulating film is a group consisting of a tetra ethyl ortho silicate (TEOS) film, a flowable oxide (FOX) film, a plasma enhanced-TEOS (PE-TEOS) film and a boron phosphorous silicate glass (BPSG) film. It may be formed of at least one material film selected from among.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 is a plan view of a semiconductor device according to some embodiments of the present invention, and FIGS. 3A to 3F are cut lines I-I 'of FIG. 2 for explaining methods of manufacturing semiconductor devices according to embodiments of the present invention. Are cross-sectional views according to. 2, 3A to 3F, portions denoted by reference numerals " I1 ", " F1 " and " P1 " represent wiring regions, fuse regions and pad regions, respectively.

2 and 3A, an interlayer insulating film 15 is formed on the semiconductor substrate 10. Before forming the interlayer insulating layer 15, various discrete devices such as transistors and resistors may be formed on the semiconductor substrate 10. A conductive film 24 is formed on the interlayer insulating film 15. The conductive layer 24 may be formed of a barrier layer 20 and a metal layer 23 sequentially stacked. The barrier layer 20 may be omitted. The barrier film 20 may be formed of a titanium nitride film or a titanium film and a titanium nitride film stacked in sequence. The metal film 23 may be formed of at least one material film selected from a group consisting of an aluminum film, a tungsten film, and a copper film.

 The lower interface layer 25 and the lower capping layer 26 may be sequentially formed on the conductive layer 24. The lower interface layer 25 may be formed of a titanium layer, and the lower capping layer 26 may be formed of a titanium nitride layer. The lower capping layer 26 may be an anti-reflection layer.

2 and 3B, a photoresist pattern exposing the fuse region F1 is formed on a substrate having the lower capping layer 26. The lower capping layer 26 and the lower interface layer 25 in the fuse region F1 are sequentially etched and removed using the photoresist pattern as an etching mask, and the conductive layer 24 is partially etched to remove the conductive layer 24. A fuse conductive film 24a having a thickness thinner than the conductive film 24 is formed. The fuse conductive layer 24a may be formed of the barrier layer 20 and the partially etched metal layer 23a sequentially stacked. The fuse conductive layer 24a may have a uniform thickness by partially etching the photoresist pattern as an etching mask.

Subsequently, the photoresist pattern is removed. An upper capping layer 27 may be formed on the substrate having the fuse conductive layer 24a. The upper capping layer 27 may be formed of the same material layer as the lower capping layer 26. The upper capping layer 27 may be used as an anti-reflection film in a patterning process. The upper capping layer 27 forming process may be omitted.

2 and 3C, the upper capping layer 27 and the fuse conductive layer 24a are sequentially patterned in the fuse region F1 by using a photolithography process and an etching process to fuse patterns 31a. To form. The fuse patterns 31a may include a first conductive pattern 24a ′ and a first upper capping pattern 27a that are sequentially stacked. The first conductive pattern 24a 'may be formed of a first barrier pattern 20a and a first metal pattern 23a' that are sequentially stacked. The fuse patterns 31a may be formed to a thickness of about 3000 kW or less.

At the same time, the upper capping layer 27, the lower capping layer 26, the interface layer 25, and the conductive layer 24 are sequentially patterned in the wiring region I1 to form the first metal lines 31b. ). The first metal lines 31b may include a second conductive pattern 24b, a lower interface pattern 25b, and a capping pattern 30b that are sequentially stacked. The second conductive pattern 24b may include a second barrier pattern 20b and a second metal pattern 23b that are sequentially stacked. The capping pattern 30b may include a lower capping pattern 26b and a second upper capping pattern 27b that are sequentially stacked. The fuse patterns 31a may have a thickness thinner than that of the first metal wires 31b, and the fuse patterns 31a may be formed by patterning through photolithography and etching processes to have a flat upper surface. .

2 and 3D, a metal interlayer insulating film 33 is formed on a substrate having the fuse patterns 31a and the first metal wires 31b. The metal interlayer insulating film 33 is at least one selected from the group consisting of a tetra ethyl ortho silicate (TEOS) film, a flowable oxide (FOX) film, a plasma enhanced-TEOS (PE-TEOS) film, and a boron phosphorous silicate glass (BPSG) film. It can be formed of one material film. For example, the metal interlayer insulating film 33 may be formed of a TEOS film, a FOX film, and a TEOS film that are sequentially stacked. The top surface of the metal interlayer insulating layer 33 may be planarized by filling the gaps between the patterns 31a and 31b by the FOX layer.

Via holes 34h may be formed through the metal interlayer insulating layer 33 in the wiring region I1 to expose predetermined regions of the first metal wirings 31b. Subsequently, the via contact plugs 34 may be formed to fill the via holes 34h to be electrically connected to the first metal wires 31b. Subsequently, an upper barrier layer, an upper metal layer, and an upper capping layer are sequentially formed on the substrate having the via contact plugs 34. The upper capping layer, the upper metal layer, and the upper barrier layer are sequentially patterned to form second metal interconnections 40 on the metal interlayer insulating layer 33 in the interconnection region 11, and at the same time, the pad region ( A pad 40p is formed on the metal interlayer insulating film 33 in P1).

The second metal wires 40 may include an upper barrier pattern 35, an upper metal pattern 37, and an upper capping pattern 39 that are sequentially stacked. The second metal wires 40 may be electrically connected to the first metal wires 31b through the via contact plugs 34. The pad 40p may include a pad conductive pattern 38p and a pad capping pattern 39p that are sequentially stacked, and the pad conductive pattern 38p may be a pad barrier pattern 35p and a pad metal pattern that are sequentially stacked. 37p).

2 and 3E, a passivation layer 43 is formed on the substrate having the second metal wires 40 and the pad 40p. The passivation film 43 may be formed of a plasma oxide film 41 and a plasma nitride film 42 that are sequentially stacked. Subsequently, after the polyimide film is formed on the substrate having the passivation film 43, an exposure process and a development process are performed to expose a predetermined region of the fuse region F1 and a predetermined region of the pad region P1, respectively. The polyimide pattern 50 having the fuse window opening 50f and the pad window opening 50p is formed.

2 and 3F, the passivation layer 43 in the fuse region F1 is etched through the fuse window opening 50f by using the polyimide pattern 50 as an etching mask, and a lower portion thereof. The metal interlayer insulating layer 33 is partially etched so that a predetermined thickness remains on the fuse patterns 31a to form a fuse window 53f. As a result, a thin metal interlayer insulating film 33a is formed in the fuse region F1. Since the thin metal interlayer insulating film 33a covering the fuse patterns 31a is formed of an oxide film such as a TEOS film, a FOX film, or a BPSG film, the fuse patterns 31a are compared with a silicon nitride film used as a fuse protection film in the related art. Low energy is required to blow At the same time, a pad which exposes the pad conductive pattern 38p by etching a predetermined region of the passivation layer 43 and the pad capping pattern 39p in the pad region P1 through the pad window opening 50p. The window 53p can be formed.

In some embodiments, the passivation layer 43 may be formed in one step through the fuse window opening 50f and the pad window opening 50p when the fuse window 53f and the pad window 53p are formed. May be selectively etched to expose the interlayer dielectric layer 33 of the fuse region F1 and the pad capping pattern 39p of the pad region P1. Subsequently, the exposed pad capping pattern 39p is etched to expose the pad conductive pattern 38p of the pad region I1, and then the exposed metal interlayer insulating layer 33 of the fuse region F1 is exposed. It can be partially etched.

The semiconductor device is electrically tested before the assembly process. At this time, a repair process is performed by irradiating a laser through the fuse window opening 50f and the fuse window 53f. Thereafter, in the assembly process, the pad bonding operation is performed through the pad window opening 50p and the pad window 53pp.

As described above, the fuse patterns 31a have a thickness thinner than that of the first metal wires 31b, and the fuse patterns 31a are formed by patterning through photolithography and etching processes. You can have In addition, as described with reference to FIG. 3B, the fuse conductive layer 24a having a thin thickness is formed in advance by partial etching using the photoresist pattern as an etching mask, thereby forming the thickness of the fuse patterns 31a in the same wafer. Uniformity can be improved. Therefore, it is possible to reduce the error occurrence rate in the fuse blowing operation.

In addition, by forming the fuse window 53f and the pad window 53p using the polyimide pattern 50 as a mask, the three photo process steps in the related art can be shortened to one time in the present invention. As a result, when considering the one photo process added in the partial etching of the conductive film 24 in FIG. 3B, the present invention can shorten one photo process in comparison with the prior art.

4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with other embodiments of the present invention. 4A to 4C, portions denoted by reference numerals " I1 ", " F1 " and " P1 " represent wiring regions, fuse regions, and pad regions, respectively.

Referring to FIG. 4A, an interlayer insulating film 15 is formed on the semiconductor substrate 10. Before forming the interlayer insulating layer 15, various discrete devices such as transistors and resistors may be formed on the semiconductor substrate 10. A conductive film 24 is formed on the interlayer insulating film 15. The conductive layer 24 may be formed of a barrier layer 20 and a metal layer 23 sequentially stacked. The barrier layer 20 may be omitted. The barrier film 20 may be formed of a titanium nitride film or a titanium film and a titanium nitride film stacked in sequence. The metal film 23 may be formed of at least one material film selected from a group consisting of an aluminum film, a tungsten film, and a copper film.

Referring to FIG. 4B, a photoresist pattern exposing the fuse region F1 is formed on a substrate having the conductive layer 24. Using the photoresist pattern as an etching mask, the conductive layer 24 in the fuse region F1 is partially etched to form a fuse conductive layer 24a having a thickness thinner than that of the conductive layer 24. The fuse conductive layer 24a may include the barrier layer 20 and the partially etched metal layer 23a that are sequentially stacked. The fuse conductive layer 24a may have a uniform thickness by partially etching the photoresist pattern as an etching mask.

Subsequently, the photoresist pattern is removed. The upper interface layer 28 and the upper capping layer 29 may be sequentially formed on the substrate having the fuse conductive layer 24a. The upper interface layer 28 may be formed of a titanium film, and the upper capping layer 29 may be formed of a titanium nitride film. The upper capping layer 29 may be used as an anti-reflection film in a patterning process.

 Referring to FIG. 4C, the upper capping layer 29, the upper interface layer 28, and the fuse conductive layer 24a ′ may be sequentially patterned in the fuse region F1 using a photolithography process and an etching process. Patterns 31a 'are formed. The fuse patterns 31a 'may include a first conductive pattern 24a', a first upper interface pattern 28a, and a first upper capping pattern 29a that are sequentially stacked. The first conductive pattern 24a 'may be formed of a first barrier pattern 20a and a first metal pattern 23a' that are sequentially stacked. The fuse patterns 31a ′ may be formed to a thickness of about 3000 kΩ or less.

At the same time, the upper capping layer 29, the upper interface layer 28, and the conductive layer 24 are sequentially patterned in the wiring region I1 to form first metal lines 31b ′. The first metal wires 31b ′ may include a second conductive pattern 24b, a second upper interface pattern 28b, and a second upper capping pattern 29b that are sequentially stacked. The second conductive pattern 24b may include a second barrier pattern 20b and a second metal pattern 23b that are sequentially stacked.

The fuse patterns 31a 'have a thickness thinner than the first metal wires 31b', and the fuse patterns 31a 'are formed by patterning through photolithography and etching processes to have a flat top surface. It becomes possible. Further, as described with reference to FIG. 4B, by using the photoresist pattern as an etching mask, the fuse conductive layer 24a having a thin thickness is formed in advance by partial etching so that the thicknesses of the fuse patterns 31a 'in the same wafer are formed. Uniformity can be improved. Therefore, it is possible to reduce the error occurrence rate in the fuse blowing operation.

Subsequently, the same process as illustrated in FIGS. 3D to 3F may be performed to form a fuse window and a pad window.

Referring to FIGS. 2 and 3F again, a semiconductor device according to example embodiments will be described. 2 and 3F, portions denoted by reference numerals " I1 ", " F1 " and " P1 " represent wiring regions, fuse regions and pad regions, respectively.

2 and 3F, an interlayer insulating film 15 is disposed on the semiconductor substrate 10. Various discrete devices such as transistors and resistors may be disposed between the semiconductor substrate 10 and the interlayer insulating layer 15. Fuse patterns 31a are disposed on the interlayer insulating layer 15 in the fuse region F1. The fuse patterns 31a may include a first conductive pattern 24a ′ and a first upper capping pattern 27a that are sequentially stacked. The first conductive pattern 24a 'may be formed of a first barrier pattern 20a and a first metal pattern 23a' that are sequentially stacked. The first upper capping pattern 27a may be omitted. The fuse patterns 31a may have a thickness of about 3000 kW or less.

First metal interconnections 31b having a thickness greater than that of the fuse patterns 31a are disposed on the interlayer insulating layer 15 in the interconnection region I1. The first metal lines 31b may include a second conductive pattern 24b, a lower interface pattern 25b, and a capping pattern 30b that are sequentially stacked. The second conductive pattern 24b may include a second barrier pattern 20b and a second metal pattern 23b that are sequentially stacked. The capping pattern 30b may include a lower capping pattern 26b and a second upper capping pattern 27b that are sequentially stacked. The second upper capping pattern 27b may be omitted.

The first conductive pattern 24a ′ has a thickness thinner than that of the second conductive pattern 24b. The first metal pattern 23a ′ and the second metal pattern 23b may be the same material layer. The first metal pattern 23a ′ and the second metal pattern 23b may be at least one material film selected from a group consisting of an aluminum film, a tungsten film, and a copper film. The first and second upper capping patterns 27a and 27b may have the same thickness and may be the same material layer. The lower capping pattern 26b may be formed of the same material layer as the second upper capping pattern 27b. The capping patterns 26b, 27a, and 27b may be titanium nitride layers. The capping patterns 26b, 27a, and 27b may be anti-reflection films. The lower interface pattern 25b may be a titanium film. The first and second barrier patterns 20a and 20b may be the same material layer and have the same thickness. The first and second barrier patterns 20a and 20b may be a titanium nitride layer or a titanium layer and a titanium nitride layer that are sequentially stacked. The first and second barrier patterns 20a and 20b may be omitted.

Since the first metal pattern 23a ′ has a thickness thinner than that of the second metal pattern 23b, the fuse patterns 31a may have a thickness smaller than that of the first metal lines 31b. The fuse patterns 31a may each have a substantially flat upper surface. In addition, the fuse patterns 31a may have a substantially uniform thickness in the same wafer. Therefore, it is possible to reduce the error occurrence rate in the fuse blowing operation.

Alternatively, as illustrated in FIG. 4C, a fuse pattern including a first conductive pattern 24a ′, a first upper interface pattern 28a, and a first upper capping pattern 29a sequentially stacked in the fuse region F1. The fields 31a 'may be arranged. The first conductive pattern 24a 'may be formed of a first barrier pattern 20a and a first metal pattern 23a' that are sequentially stacked. The fuse patterns 31a ′ may have a thickness of about 3000 μm or less. In addition, the first metal wires 31b 'including the second conductive pattern 24b, the second upper interface pattern 28b, and the second upper capping pattern 29b that are sequentially stacked in the wiring region I1 are disposed. Can be. The second conductive pattern 24b may include a second barrier pattern 20b and a second metal pattern 23b that are sequentially stacked. The first conductive pattern 24a ′ has a thickness thinner than that of the second conductive pattern 24b. The fuse patterns 31a 'have a thickness thinner than that of the first metal wires 31b'. The first and second upper capping patterns 29a and 29b may be anti-reflection films.

A metal interlayer insulating film 33 is disposed on the substrate having the fuse patterns 31a and the first metal wires 31b. The metal interlayer insulating film 33 is at least one selected from the group consisting of a tetra ethyl ortho silicate (TEOS) film, a flowable oxide (FOX) film, a plasma enhanced-TEOS (PE-TEOS) film, and a boron phosphorous silicate glass (BPSG) film. It may be one material film. For example, the metal interlayer insulating layer 33 may be a tetra ethyl ortho silicate (TEOS) film, a flowable oxide (FOX) film, and a TEOS film sequentially stacked. The FOX layer may fill the gaps between the patterns 31a and 31b so that the metal interlayer insulating layer 33 may have a planarized upper surface.

Via holes 34h may be disposed to penetrate the metal interlayer insulating layer 33 in the wiring region I1 to expose predetermined regions of the first metal wirings 31b. Via contact plugs 34 may be disposed to fill the via holes 34h. The via holes 34h may expose the inside of the capping pattern 30b or may pass through the capping pattern 30b to expose the lower interface pattern 25b.

Second metal wires 40 may be disposed on the metal interlayer insulating layer 33 in the wiring area 11. The second metal wires 40 may include an upper barrier pattern 35, an upper metal pattern 37, and an upper capping pattern 39 that are sequentially stacked. The second metal wires 40 may be electrically connected to the first metal wires 31b through the via contact plugs 34, respectively.

The pad 40p is disposed on the metal interlayer insulating film 33 in the pad region P1. The pad 40p may include a pad conductive pattern 38p and a pad capping pattern 39p that are sequentially stacked, and the pad conductive pattern 38p may be a pad barrier pattern 35p and a pad metal pattern that are sequentially stacked. 37p).

A passivation layer 43 is disposed on the substrate having the second metal wires 40 and the pad 40p. The passivation film 43 may be a plasma oxide film 41 and a plasma nitride film 42 that are sequentially stacked. Poly having a fuse window opening 50f and a pad window opening 50p exposing a predetermined region of the fuse region F1 and a predetermined region of the pad region P1 on the substrate having the passivation film 43, respectively. The mid pattern 50 may be disposed.

A fuse window 53f penetrating the passivation film 43 under the fuse window opening 50f in the fuse region F1 and penetrating a predetermined depth of the metal interlayer insulating film 33 thereunder is disposed. . A thin metal interlayer insulating layer 33a covering the fuse patterns 31a is disposed under the fuse window 53f. Since the thin metal interlayer insulating film 33a covering the fuse patterns 31a is an oxide film, low energy is required to blow the fuse patterns 31a as compared to a silicon nitride film, which is a fuse protection film material in the related art.

The pad window 53p exposing the pad conductive pattern 38p through a predetermined area of the passivation film 43 and the pad capping pattern 39p under the pad window opening 50p in the pad area P1. ) Is placed.

As described above, according to the present invention, after the conductive film is formed, a fuse conductive film having a thickness thinner than the conductive film is formed by partial etching, and the conductive film and the fuse conductive film are patterned to respectively form the first metal wires and the fuse. Form patterns simultaneously. As a result, the fuse patterns may have a thickness thinner than that of the first metal wires, and the fuse patterns may be formed by patterning through photolithography and etching processes to have a flat top surface. In addition, since the fuse conductive film having a thickness thinner than the conductive film is previously formed by partial etching, the thickness uniformity of the fuse patterns may be improved in the same wafer. Therefore, the fuse patterns can be blown with a constant low energy, and since the fuse patterns are formed thin, the bridge with adjacent metal fuses can be reduced by reducing the amount of remaining material of the fuse patterns due to blowing.

In addition, by forming the fuse window and the pad window using the polyimide pattern as an etching mask, it is possible to shorten the three photo process steps in the prior art to one. As a result, one photo process can be shortened compared to the prior art, thereby reducing the production cost.

Claims (23)

A semiconductor substrate having a fuse region and a wiring region; A fuse pattern comprising a first metal pattern and a first capping pattern disposed in the fuse area of the semiconductor substrate and sequentially stacked; And And a metal wiring disposed in the wiring region of the semiconductor substrate, the metal wiring including a second metal pattern and a second capping pattern sequentially stacked, wherein the first metal pattern has a thickness thinner than that of the second metal pattern. The method of claim 1, The first and second capping pattern is a semiconductor device, characterized in that the anti-reflection film. The method of claim 1, And the first metal pattern and the second metal pattern are at least one material film selected from a group consisting of an aluminum film, a tungsten film, and a copper film. The method of claim 1, The thickness of the second capping pattern is a semiconductor device, characterized in that the same or thicker than the first capping pattern. The method of claim 1, The first capping pattern and the second capping pattern is a semiconductor device, characterized in that the titanium nitride film (TiN). The method of claim 1, The fuse pattern may further include a first interface pattern interposed between the first metal pattern and the first capping pattern. The method of claim 1, The metal wire further comprises a second interface pattern interposed between the second metal pattern and the second capping pattern. The method of claim 1, And the fuse pattern and the metal wire further include first and second barrier patterns respectively disposed under the first and second metal patterns. The method of claim 1, And the fuse pattern and the metal wiring are disposed on the same level. The method of claim 1, And an oxide layer covering the fuse pattern and the fuse patterns in the fuse region and having a flat upper surface. Preparing a semiconductor substrate having a fuse region, a wiring region, and a pad region; A conductive film is formed on the semiconductor substrate, Partially etching the conductive film in the fuse region to form a fuse conductive film having a thickness thinner than that of the conductive film, And patterning the conductive film and the fuse conductive film to form a first conductive pattern in the fuse region and a second conductive pattern in the wiring region. The method of claim 11, Before partially etching the conductive film, And forming a lower capping layer on the conductive layer, wherein the lower capping layer in the fuse region is removed in the step of partially etching the conductive layer, and the lower capping layer in the wiring region forms the second conductive pattern. Patterning at the step to form a lower capping pattern. The method of claim 12, Forming a lower interface film between the conductive film and the lower capping film, wherein the lower interface film in the fuse region is removed in the step of partially etching the conductive film, and the lower interface film in the wiring region is the second Patterning in the step of forming the conductive pattern to form a lower interface pattern, characterized in that the semiconductor device manufacturing method. The method of claim 11, After forming the fuse conductive film, And forming an upper capping layer on the substrate having the fuse conductive layer, wherein the upper capping layer is patterned in forming the first and second conductive patterns to form a first upper portion on the first and second conductive patterns, respectively. A method for manufacturing a semiconductor device, comprising forming first and second upper capping patterns. The method of claim 14, The upper capping film is a semiconductor device manufacturing method, characterized in that formed by a titanium nitride film (TiN). The method of claim 14, The upper capping film is a semiconductor device manufacturing method, characterized in that the anti-reflection film. The method of claim 14, Before forming the upper capping layer, The method may further include forming an upper interface layer on the substrate having the fuse conductive layer, wherein the upper interface layer is patterned in the forming of the first and second conductive patterns so as to be formed on top of the first and second conductive patterns, respectively. A method for manufacturing a semiconductor device, comprising forming first and second upper interface patterns. The method of claim 11, And the conductive film is formed of a metal film or a barrier film and a metal film that are sequentially stacked. The method of claim 18, The metal film is a semiconductor device manufacturing method, characterized in that formed of at least one material film selected from the group consisting of aluminum film, tungsten film and copper film. The method of claim 11, Forming a metal interlayer insulating film on the substrate having the first and second conductive patterns, Forming a pad including a pad conductive pattern and a pad capping pattern sequentially stacked on the metal interlayer insulating film in the pad region, Forming a passivation film on the substrate having the pad, The passivation layer, the pad capping pattern, and the metal interlayer insulating layer are etched to form a fuse window in the fuse region so that a predetermined thickness of the metal interlayer insulating layer remains on the first conductive pattern. And forming a pad window exposing the conductive pattern. The method of claim 20, Forming the fuse window and the pad window Forming a polyimide film on the passivation film, Exposing and developing the polyimide film to form a polyimide pattern having openings exposing predetermined areas of the fuse region and the pad region, And etching the passivation layer, the pad capping pattern, and the metal interlayer insulating layer using the polyimide pattern as an etching mask. The method of claim 20, Forming the fuse window and the pad window Etching the passivation layer to expose the interlayer dielectric layer of the fuse region and the pad capping pattern of the pad region; Etching the exposed pad capping pattern to expose the pad conductive pattern of the pad region; And partially etching the exposed metal interlayer dielectric layer of the fuse region. The method of claim 20, The metal interlayer insulating film is at least one selected from the group consisting of a tetra ethyl ortho silicate (TEOS) film, a flowable oxide (FOX) film, a plasma enhanced-TEOS (PE-TEOS) film, and a boron phosphorous silicate glass (BPSG) film. A method of manufacturing a semiconductor device, characterized in that formed into a film.

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