KR20020027696A - Method of making fuse box - Google Patents

Method of making fuse box Download PDF

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Publication number
KR20020027696A
KR20020027696A KR1020000058271A KR20000058271A KR20020027696A KR 20020027696 A KR20020027696 A KR 20020027696A KR 1020000058271 A KR1020000058271 A KR 1020000058271A KR 20000058271 A KR20000058271 A KR 20000058271A KR 20020027696 A KR20020027696 A KR 20020027696A
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South Korea
Prior art keywords
metal
fuse
etching
pattern
polysilicon
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KR1020000058271A
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Korean (ko)
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박상수
이상도
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000058271A priority Critical patent/KR20020027696A/en
Publication of KR20020027696A publication Critical patent/KR20020027696A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE: A method for fabricating a fuse box is provided to shorten a fabricating interval of time, by forming a fuse line composed of polysilicon and a metal layer and by simultaneously performing a pad etch process and a repair etch process while using only a pad etching target. CONSTITUTION: A polysilicon pattern(22a,22b) of which the center portion is cut is formed on a semiconductor substrate(21). A metal layer pattern(24) which connects the cut polysilicon patterns with each other is fabricated to form the fuse line composed of the polysilicon pattern and a metal layer pattern. A metal pad(26) is formed on a part of the fuse line so that the upper portion of the fuse line is opened in etching a subsequent insulation layer. An insulation layer is formed on the metal pad. The insulation layer is selectively etched by using only the metal pad etching target to open the metal pad. A predetermined thickness of the insulation layer for a subsequent repair process is left on the fuse line.

Description

퓨즈박스의 제조 방법{METHOD OF MAKING FUSE BOX}Manufacturing method of fuse box {METHOD OF MAKING FUSE BOX}

본 발명은 반도체소자의 제조 방법에 관한 것으로, 패드/리페어(Pad/Repair)식각공정을 단순화시키도록 한 퓨즈박스(Fuse box)의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a fuse box for simplifying a pad / repair etching process.

일반적으로 반도체 장치 제조를 위한 설계시 수율을 증가시키기 위한 목적으로, 결함있는 소자 또는 회로를 대체하기 위하여 여분의 회로를 메모리 설계시 부가한다. 상기 여분의 회로는 메모리 어레이(Memory array)에 인접하여 형성되는 예비의 로 및 칼럼(Row and Column)으로 이루어지며, 불량 메모리 단위가 발생하면 불량 회로를 구성하는 로 및 칼럼이 예비의로 및 칼럼으로 대체된다.In general, for the purpose of increasing the yield in the design for semiconductor device manufacturing, extra circuitry is added in the memory design to replace defective devices or circuits. The redundant circuit includes a preliminary row and column formed adjacent to a memory array, and when a bad memory unit occurs, the furnace and column constituting the bad circuit are reserved. Replaced by

이러한 불량 메모리의 대체는 메모리 소자에 형성된 퓨즈(Fuse)를 선택적으로 끊음(blowing)으로써 이루어진다. 대체로 퓨즈는 폴리실리콘막으로 형성되며, 과도한 전류를 흘리거나 레이저 빔(Laser beam)을 조사하여 퓨즈를 끊는다.The replacement of the defective memory is made by selectively blowing a fuse formed in the memory device. In general, the fuse is formed of a polysilicon film and blows excessive current or irradiates a laser beam to blow the fuse.

도 1은 종래기술에 따라 제조된 퓨즈박스를 도시한 도면으로서, 반도체기판(11)상에 폴리실리콘막을 형성한 후, 상기 폴리실리콘막을 선택적으로 패터닝하여 퓨즈라인(12)을 형성한다. 이어서, 상기 퓨즈라인을 포함한 전면에 제1절연막(13)을 형성하고, 상기 제 1 절연막(13)상에 폴리실리콘막을 형성한 후, 상기 폴리실리콘막을 선택적으로 패터닝하여 상기 퓨즈라인(12)상부에 블록킹막(14)을 형성한다. 이 때, 상기 블록킹막(14)은 후속 레이저빔이 퓨즈라인(12)에 입사될 수 있도록 그 중심부가 오픈되며, 후속 리페어식각시 퓨즈라인(12) 상부에 잔류하는 제 1 절연막(13)을 균일하게 잔류시키기 위한 식각방지막으로 이용된다.FIG. 1 is a view illustrating a fuse box manufactured according to the prior art, in which a polysilicon film is formed on a semiconductor substrate 11, and then the polysilicon film is selectively patterned to form a fuse line 12. Subsequently, a first insulating film 13 is formed on the entire surface including the fuse line, a polysilicon film is formed on the first insulating film 13, and then the polysilicon film is selectively patterned to form an upper portion of the fuse line 12. A blocking film 14 is formed on the substrate. In this case, the blocking layer 14 has a central portion thereof open so that a subsequent laser beam may be incident on the fuse line 12, and the first insulating layer 13 remaining on the fuse line 12 during the subsequent repair etching may be formed. It is used as an etch stopper for remaining uniformly.

이어서, 상기 블록킹막(14)을 포함한 전면에 제 2 절연막(15)을 형성한 후, 상기 제 2 절연막상(15)에 금속막을 형성하고, 상기 금속막을 선택적으로 패터닝하여 상기 퓨즈라인(12)에 오버랩되지 않도록 금속패드(16)를 형성한다.Subsequently, after the second insulating film 15 is formed on the entire surface including the blocking film 14, a metal film is formed on the second insulating film 15, and the metal film is selectively patterned to form the fuse line 12. The metal pad 16 is formed so as not to overlap.

이어서, 상기 금속패드(16)를 포함한 전면에 제 3 절연막(17)을 형성한 후, 상기 퓨즈라인(12) 상부에 제 1 절연막(13)을 소정두께(d1)만큼 잔류시키기 위한 리페어 식각 및 금속패드(16)를 노출시키기 위한 패드식각을 진행한다.Subsequently, after the third insulating layer 17 is formed on the entire surface including the metal pad 16, the repair etching is performed to leave the first insulating layer 13 on the fuse line 12 by a predetermined thickness d 1 . And etching the pad to expose the metal pad 16.

즉, 각각의 식각타겟으로 제 3 절연막(17), 제 2 절연막(15) 및 제 1 절연막 (13)을 식각하여 상기 퓨즈라인(12) 상부에 제 1 절연막(13)을 1000Å∼3000Å만큼 잔류시키고, 제 3 절연막(17)을 식각하여 금속패드(16)를 완전히 오픈시킨다.That is, the third insulating film 17, the second insulating film 15, and the first insulating film 13 are etched by the respective etching targets, and the first insulating film 13 is left on the fuse line 12 by 1000 m to 3000 m. The third insulating layer 17 is etched to completely open the metal pad 16.

이와 같이, 종래기술에서는 패드/리페어 식각공정을 각각의 식각타겟으로 진행하며, 소자가 0.18㎛이하로 고집적화됨에 따라 절연막의 적층후 화학적기계적평탄화(Chemical Mechanical Polishing; CMP)공정으로 주변회로영역의 총 절연막의 두께가 증가하고 있는 추세이며, 이를 해결하고자 균일도개선 등 공정 안정화를 위해 중간에 블록킹막(14)을 추가한다.As described above, in the prior art, the pad / repair etching process is performed to each etching target, and as the device is highly integrated to 0.18 μm or less, the total mechanical thickness of the peripheral circuit area is changed by chemical mechanical polishing (CMP) process after lamination of the insulating film. The thickness of the insulating film is increasing, and in order to solve the problem, a blocking film 14 is added in the middle to stabilize the process such as improving the uniformity.

그러나, 금속패드(16)를 노출시키는 패드식각은 문제가 없지만 퓨즈라인상부에 다층의 절연막이 형성되어 있으므로 2000Å두께의 절연막을 잔류시키는 리페어 식각의 공정시간이 점점 증가하는 문제점이 있다. 또한, 상기 패드식각 및 리페어 식각시 C4F8, CHF3, C2F6가스를 사용함에 따라 폴리머가 다량 생성된다.However, although the pad etching exposing the metal pad 16 is not a problem, the multilayer insulating film is formed on the fuse line, so that the process time for the repair etching for leaving the insulating film having a thickness of 2000 mV increases. In addition, a large amount of polymer is produced by using C 4 F 8 , CHF 3 , C 2 F 6 gas in the pad etching and repair etching.

특히 0.18㎛급 소자에서 로트(Lot)당 공정시간이 5시간(10분/1장)이 소요되므로 생산성이 낮으며, 또한 제 3 절연막 식각을 위한 감광막 두께가 3.0㎛정도로 감광막 베링(Buring)이 빈번이 발생하고 식각율 증가를 위한 신규 장비가 요구되는 문제점이 있다.In particular, the productivity is low because the process time per lot takes 5 hours (10 minutes / 1 sheet) in a 0.18㎛ class device, and the photoresist film has a thickness of about 3.0㎛ for the etching of the third insulating film. Frequently, there is a problem that new equipment for increasing the etching rate is required.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 리페어 식각으로 인한 공정시간을 단축시키고, 감광막 베링을 방지하고 감광막 제거를 위한 공정시간을 감소시키는데 적합한 퓨즈박스의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, to provide a method of manufacturing a fuse box suitable for shortening the process time due to repair etching, preventing the photoresist bearing and reducing the process time for removing the photoresist. There is a purpose.

도 1은 종래기술에 따라 제조된 퓨즈박스를 도시한 도면,1 is a view showing a fuse box manufactured according to the prior art,

도 2a 내지 도 2b는 본 발명의 실시예에 따른 퓨즈박스의 제조 방법을 도시한 도면,2a to 2b is a view showing a manufacturing method of a fuse box according to an embodiment of the present invention,

도 3은 도 2b에 따른 퓨즈박스의 평면도.Figure 3 is a plan view of the fuse box according to Figure 2b.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체기판 22a, 22b : 폴리실리콘패턴21: semiconductor substrate 22a, 22b: polysilicon pattern

23 : 제 1 절연막 24 : 금속막패턴23: first insulating film 24: metal film pattern

25 : 제 2 절연막 26 : 금속패드25 second insulating film 26 metal pad

27 : 제 3 절연막27: third insulating film

상기의 목적을 달성하기 위한 본 발명의 퓨즈박스의 제조 방법은 반도체기판상에 중심부분이 절단된 폴리실리콘패턴을 형성하는 단계; 상기 절단된 폴리실리콘패턴을 서로 연결시키는 금속막패턴을 형성하여 상기 폴리실리콘패턴과 금속막패턴으로 이루어지는 퓨즈라인을 형성하는 단계; 후속 절연막 식각시 상기 퓨즈라인 상부가 오픈되도록 상기 퓨즈라인의 일측 상부에 금속패드를 형성하는 단계; 상기 금속패드상에 절연막을 형성하는 단계; 및 상기 금속패드 식각 타겟만으로 상기 절연막을 선택적으로 식각하여 상기 금속패드를 오픈시키고 상기 퓨즈라인의 상부에 후속 리페어를 위한 소정두께의 절연막을 잔류시키는 단계를 포함하여 이루어짐을 특징으로 한다.Method for manufacturing a fuse box of the present invention for achieving the above object comprises the steps of forming a polysilicon pattern is cut central portion on the semiconductor substrate; Forming a metal film pattern connecting the cut polysilicon patterns to each other to form a fuse line including the polysilicon pattern and the metal film pattern; Forming a metal pad on one side of the fuse line to open the fuse line at the time of subsequent insulating layer etching; Forming an insulating film on the metal pad; And selectively etching the insulating film using only the metal pad etching target to open the metal pad and leaving an insulating film having a predetermined thickness for subsequent repair on the fuse line.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2b는 본 발명의 실시예에 따른 퓨즈박스의 제조 방법을 도시한 도면이다.2A to 2B are views illustrating a method of manufacturing a fuse box according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체기판(21)상에 폴리실리콘막을 형성하고, 상기 폴리실리콘막을 선택적으로 패터닝하여 폴리실리콘패턴(22a, 22b)을 형성한다. 즉, 후속 퓨즈라인을 폴리실리콘 패터닝시 미리 절단하여 중심부분이 d2의 폭만큼 오픈되도록 한다.As shown in FIG. 2A, a polysilicon film is formed on the semiconductor substrate 21, and the polysilicon film is selectively patterned to form polysilicon patterns 22a and 22b. That is, the subsequent fuse lines are cut in advance during polysilicon patterning so that the central portion is opened by the width of d 2 .

이어서, 상기 폴리실리콘패턴(22a, 22b)을 포함한 전면에 제 1 절연막(23)을 형성한 후, 상기 제 1 절연막(23)을 선택적으로 패터닝하여 상기 폴리실리콘패턴()의 소정 부분이 노출되는 콘택홀을 형성한다.Subsequently, after the first insulating film 23 is formed on the entire surface including the polysilicon patterns 22a and 22b, the first insulating film 23 is selectively patterned to expose a predetermined portion of the polysilicon pattern. A contact hole is formed.

이어서 상기 콘택홀을 포함한 전면에 금속막을 형성한 후, 상기 금속막을 선택적으로 패터닝하여 상기 콘택홀을 통해 상기 폴리실리콘패턴(22a, 22b)에 접속되는 금속막패턴(24)을 형성한다.Subsequently, after forming a metal film on the entire surface including the contact hole, the metal film is selectively patterned to form a metal film pattern 24 connected to the polysilicon patterns 22a and 22b through the contact hole.

즉, 상기 금속막패턴(24)은 중심부분이 d2만큼 오픈된 폴리실리콘패턴(22a, 22b)을 서로 연결시켜 폴리실리콘패턴(22a, 22b)과 금속막패턴(24)으로 이루어지는 퓨즈라인을 형성한다.That is, the metal film pattern 24 connects the polysilicon patterns 22a and 22b whose center portions are opened by d 2 to each other to form a fuse line formed of the polysilicon patterns 22a and 22b and the metal film pattern 24. Form.

이와 같이, 퓨즈라인을 형성하기 위한 폴리실리콘 식각시 미리 절단하고, 금속막패턴(24)을 이용하여 절단된 폴리실리콘패턴(22a, 22b)을 접속시켜 퓨즈라인을 상승시키므로 통상의 폴리실리콘 블록킹막을 형성하기 위한 공정을 생략할 수 있다.As such, when the polysilicon etching to form the fuse line is cut in advance, the polysilicon patterns 22a and 22b cut using the metal film pattern 24 are connected to raise the fuse line. The step for forming can be omitted.

도 2b에 도시된 바와 같이, 상기 금속막패턴(24)을 포함한 전면에 제 2 절연막(25)을 형성하고, 상기 제 2 절연막(25)상에 금속패드(26)를 형성하되, 상기 퓨즈라인과 오버랩되지 않도록 한다. 즉, 후속 리페어를 위한 레이점 빔의 입사를 막지않도록 상기 퓨즈라인 상부에는 절연막만이 존재하도록 한다.As shown in FIG. 2B, a second insulating film 25 is formed on the entire surface including the metal film pattern 24, and a metal pad 26 is formed on the second insulating film 25. Do not overlap with That is, only the insulating film is present on the fuse line so as to prevent the incident of the ray point beam for the subsequent repair.

이어서, 상기 금속패드(26)상에 제 3 절연막(27) 또는 보호막을 형성하고, 상기 제 3 절연막(27)을 선택적으로 식각하여 상기 금속패드(26)의 소정 부분이 노출되는 패드식각을 실시한다. 여기서, 상기 제 3 절연막(27) 또는 보호막은 질화막을 이용할 수 있다.Subsequently, a third insulating film 27 or a protective film is formed on the metal pad 26, and the third insulating film 27 is selectively etched to perform a pad etching to expose a predetermined portion of the metal pad 26. do. In this case, a nitride film may be used as the third insulating film 27 or the protective film.

이 때, 상기 패드식각시 제 3 절연막(27)을 과도식각하여 상기 금속막패턴 (24) 상부에 제 2 절연막(25)이 소정 두께(d3)만큼 잔류하도록 하는데, 즉 패드식각의 식각타겟으로만 패드식각 및 리페어식각을 동시에 진행한다.At this time, the third insulating film 27 is over-etched during the pad etching so that the second insulating film 25 remains on the metal film pattern 24 by a predetermined thickness d 3 , that is, the etching target of the pad etching. Only pad etching and repair etching are performed simultaneously.

그리고, 상기 금속패드(26)를 오픈시키기 위한 제 3 절연막(27) 식각시 CF4와 O2에 CHF3를 추가하거나 또는 SF6와 He 가스를 주반응가스로 사용한다.In addition, when etching the third insulating layer 27 to open the metal pad 26, CHF 3 is added to CF 4 and O 2 , or SF 6 and He gases are used as main reaction gases.

한편, 퓨즈라인 특히, 금속막패턴(24) 상부에 제 2 절연막(25)을 소정두께만큼 잔류시키는 리페어식각에서는 과도식각조건으로 CF4를 주가스로 하고 Ar 가스를 첨가하여 퓨즈라인상부의 잔류 절연막 두께(d3)를 조절하며, 식각율을 증가시키기 위해 NF3를 첨가한다.On the other hand, in the repair etching in which the second insulating film 25 is left to the predetermined thickness on the fuse line, especially the metal film pattern 24, CF 4 is the main gas under the transient etching condition and Ar gas is added to retain the upper portion of the fuse line. The insulating film thickness d 3 is adjusted and NF 3 is added to increase the etching rate.

상술한 것처럼, 제 3 절연막(27) 식각시, 통상의 블록킹막을 생략함에 따라 폴리머 생성이 억제되어 수직프로파일(Vertical profile)(28)을 구현하여 퓨즈박스의 설계상 마진을 확보할 수 있다.As described above, when the third insulating layer 27 is etched, since the conventional blocking layer is omitted, the generation of the polymer is suppressed to implement a vertical profile 28 to secure a margin in the design of the fuse box.

도 3은 도 2a 및 도 2b에 따른 퓨즈박스의 평면도로서, 절단된 폴리실리콘패턴(22a, 22b)을 서로 접속시키는 금속막패턴(24)이 형성하여 통상의 블록킹막의 높이만큼 폴리실리콘패턴과 금속막패턴의 퓨즈라인을 상승시키고, 도면에 도시되지 않았지만, 상기 금속막패턴(24)의 상부에는 레이저빔을 이용한 리페어를 위해 절연막이 잔류한다.3 is a plan view of the fuse box according to FIGS. 2A and 2B, wherein the metal film pattern 24 connecting the cut polysilicon patterns 22a and 22b to each other is formed so that the polysilicon pattern and the metal are as large as a normal blocking film. Although not shown in the figure, the fuse line of the film pattern is raised, and an insulating film remains on the metal film pattern 24 for repair using a laser beam.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명의 퓨즈박스의 제조 방법은 폴리실리콘과 금속막으로 이루어진 퓨즈라인을 형성한 후, 패드식각 타겟으로만 패드식각 및 리페어식각을 동시에 진행하므로써 공정시간을 단축시킬 수 있는 효과가 있으며, 블록킹막을 생략하고 패드식각 및 리페어식각을 위한 감광막의 두께를 낮추므로써 감광막 베링방지 및 감광막 제거를 위한 공정시간을 단축시킬 수 있는 효과가 있다.The method of manufacturing a fuse box according to the present invention as described above has the effect of shortening the process time by forming a fuse line made of polysilicon and a metal film, and simultaneously performing pad etching and repair etching only with a pad etching target. In addition, by omitting the blocking film and lowering the thickness of the photoresist film for pad etching and repair etching, there is an effect that the process time for preventing the photoresist film bering and removing the photoresist film can be shortened.

Claims (6)

반도체소자의 제조 방법에 있어서,In the manufacturing method of a semiconductor device, 반도체기판상에 중심부분이 절단된 폴리실리콘패턴을 형성하는 단계;Forming a polysilicon pattern with a central portion cut on the semiconductor substrate; 상기 절단된 폴리실리콘패턴을 서로 연결시키는 금속막패턴을 형성하여 상기 폴리실리콘패턴과 금속막패턴으로 이루어지는 퓨즈라인을 형성하는 단계;Forming a metal film pattern connecting the cut polysilicon patterns to each other to form a fuse line including the polysilicon pattern and the metal film pattern; 후속 절연막 식각시 상기 퓨즈라인 상부가 오픈되도록 상기 퓨즈라인의 일측 상부에 금속패드를 형성하는 단계;Forming a metal pad on one side of the fuse line to open the fuse line at the time of subsequent insulating layer etching; 상기 금속패드상에 절연막을 형성하는 단계; 및Forming an insulating film on the metal pad; And 상기 금속패드 식각 타겟만으로 상기 절연막을 선택적으로 식각하여 상기 금속패드를 오픈시키고 상기 퓨즈라인의 상부에 후속 리페어를 위한 소정두께의 절연막을 잔류시키는 단계Selectively etching the insulating layer using only the metal pad etching target to open the metal pad and leaving an insulating layer having a predetermined thickness for subsequent repair on the fuse line; 를 포함하여 이루어짐을 특징으로 하는 퓨즈박스의 제조 방법.Method for manufacturing a fuse box, characterized in that comprises a. 제 1 항에 있어서,The method of claim 1, 상기 금속패드를 오픈시키기 위한 절연막 식각시, CF4와 O2에 CHF3를 추가하거나 또는 SF6와 He 가스를 주반응가스로 사용하는 것을 특징으로 하는 퓨즈박스의 제조 방법.When the insulating film for opening the metal pad, CHF 3 is added to CF 4 and O 2 or SF 6 and He gas as a main reaction gas manufacturing method of the fuse box characterized in that used. 제 1 항에 있어서,The method of claim 1, 상기 퓨즈라인 상부에 절연막을 잔류시키는 단계는,Remaining an insulating film on the fuse line, CF4와 Ar의 혼합가스를 이용하는 것을 특징으로 하는 퓨즈박스의 제조 방법.Method for producing a fuse box, characterized in that using a mixed gas of CF 4 and Ar. 제 3 항에 있어서,The method of claim 3, wherein 상기 CF4와 Ar가스의 혼합가스에 NF3를 첨가하는 것을 특징으로 하는 퓨즈박스의 제조 방법.The manufacturing method of the fuse box, characterized in that NF 3 is added to the mixed gas of CF 4 and Ar gas. 제 1 항에 있어서,The method of claim 1, 상기 절연막 식각시,When etching the insulating film, 상기 퓨즈라인 상부는 수직 프로파일로 형성되는 것을 특징으로 하는 퓨즈박스의 제조 방법.A fuse box manufacturing method, characterized in that the upper portion of the fuse line is formed in a vertical profile. 제 1 항에 있어서,The method of claim 1, 상기 금속막패턴을 형성하는 단계는,Forming the metal film pattern, 상기 절단된 폴리실리콘패턴상에 절연막을 형성하는 단계;Forming an insulating film on the cut polysilicon pattern; 상기 절연막을 선택적으로 식각하여 상기 절단된 폴리실리콘패턴의 소정 부분이 노출되는 콘택홀을 형성하는 단계;Selectively etching the insulating layer to form a contact hole exposing a predetermined portion of the cut polysilicon pattern; 상기 콘택홀에 매립되는 금속콘택을 형성하는 단계; 및Forming a metal contact embedded in the contact hole; And 상기 금속콘택을 통해 하부의 상기 폴리실리콘패턴을 서로 연결시키는 상기 금속막패턴을 형성하는 단계Forming the metal layer pattern connecting the polysilicon patterns below each other through the metal contact; 를 포함하여 이루어짐을 특징으로 하는 퓨즈박스의 제조 방법.Method for manufacturing a fuse box, characterized in that comprises a.
KR1020000058271A 2000-10-04 2000-10-04 Method of making fuse box KR20020027696A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100513304B1 (en) * 2002-12-10 2005-09-07 삼성전자주식회사 A fuse box of a semiconductor device and a fabrication method thereof
KR100889336B1 (en) * 2002-12-30 2009-03-18 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100513304B1 (en) * 2002-12-10 2005-09-07 삼성전자주식회사 A fuse box of a semiconductor device and a fabrication method thereof
KR100889336B1 (en) * 2002-12-30 2009-03-18 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same

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