KR20020001350A - manufacturing method of semiconductor devices - Google Patents

manufacturing method of semiconductor devices Download PDF

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Publication number
KR20020001350A
KR20020001350A KR1020000035990A KR20000035990A KR20020001350A KR 20020001350 A KR20020001350 A KR 20020001350A KR 1020000035990 A KR1020000035990 A KR 1020000035990A KR 20000035990 A KR20000035990 A KR 20000035990A KR 20020001350 A KR20020001350 A KR 20020001350A
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South Korea
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layer
insulating film
film
wiring
oxide layer
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KR1020000035990A
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Korean (ko)
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KR100342098B1 (en
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이대근
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황인길
아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to form uniformly an oxide layer on an upper portion of lines formed on a semiconductor substrate by using an etch ratio of the oxide layer and a nitride layer. CONSTITUTION: The first metal layer(121-124) including the first to the fourth line(121-124) is formed on a semiconductor substrate(110) including a sub line. The first oxide layer(130) and a nitride layer(140) are formed on an upper portion of the first metal layer(121-124). An SOG(Spin-On-Glass) layer(150) and the second oxide layer(160) are formed thereon. A via hole for exposing the second and the fourth lines(122,124) is formed by patterning the second oxide layer(160), the SOG layer(150), the nitride layer(140), and the first oxide layer(130). A plug(170) is formed by inserting metal material into the via hole. The second metal layer(180) is formed on the second oxide layer(160). The third oxide layer(190) is formed on the second metal layer(180). A photo-resist pattern is formed on the third oxide layer(190). The third oxide layer(190), the second oxide layer(160), the SOG layer(150), and the nitride layer(140) are etched by using the photo-resist layer pattern as a mask.

Description

반도체 소자의 제조 방법{manufacturing method of semiconductor devices}Manufacturing method of semiconductor devices

본 발명은 반도체 소자 제조 공정에 관한 것으로서, 더욱 상세하게는 배선 형성후 여분의 배선을 단선시키기 위한 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing process, and more particularly, to a process for disconnecting excess wiring after wiring formation.

최근, 반도체 회로는 그 크기가 더욱 감소됨에 따라, 집적 회로에서의 배선을 다층화하고, 이 배선들을 접촉구를 통해 연결하는 다층 배선 방법이 주로 사용되고 있는데, 이때 여분의 배선을 형성하여 배선의 손상을 보호하기 위해 레이저 수리 공정을 실시한다. 레이저 수리 공정시 금속 찌꺼기에 의해 발생할 수 있는 단락 등의 문제를 방지하기 위해 수리할 배선 위에 절연막을 일정하게 형성하는데 이 경우 절연막의 두께가 일정하지 않아 레이저 수리가 되지 않을 수 있다.Recently, as the size of a semiconductor circuit is further reduced, a multilayer wiring method of multilayering wirings in an integrated circuit and connecting the wirings through contact holes is mainly used. At this time, an excess wiring is formed to prevent damage to the wiring. Perform laser repair process to protect. In order to prevent problems such as short circuits caused by metal debris in the laser repair process, an insulating film is formed on the wiring to be repaired in this case. In this case, the thickness of the insulating film may not be constant, so laser repair may not be performed.

그러면, 첨부한 도면을 참조하여 반도체 소자의 제조 방법에 대해 설명한다.Next, the manufacturing method of a semiconductor element is demonstrated with reference to attached drawing.

먼저, 도 1a에 도시한 바와 같이 반도체 소자 및 하부 배선층(도시하지 않음)을 포함하는 반도체 기판(10) 위에 제1 내지 제4 배선(21, 22, 23, 24)으로 이루어진 제1 금속층(21, 22, 23, 24)을 형성한 후, 그 위에 제1 산화막(31), SOG(spin-on-glass)막(32), 그리고 제2 산화막(33)으로 이루어진 층간 절연막(inter-metal dielectric)(30)을 형성하고 패터닝하여 제2 배선 및 제4 배선(22, 24)을 드러내는 비아 홀을 형성한 다음, 비아 홀 내부를 금속 물질로 채워 플러그(40)를 형성한다. 이어, 제2 산화막(33) 상부에 플러그(40)를 통해 제1 금속층(22, 24)과 각각 연결되어 있는 제2 금속층(50)을 형성하고 그 위에 제3 산화막(60)을 형성한다. 다음, 제3 산화막(60) 상부에 제2 금속층(50)과 제3 배선(23)을 드러내기 위해 감광막 패턴(70)을 형성한다.First, as shown in FIG. 1A, a first metal layer 21 including first to fourth wirings 21, 22, 23, and 24 on a semiconductor substrate 10 including a semiconductor device and a lower wiring layer (not shown). , 22, 23, and 24, and then an inter-metal dielectric composed of a first oxide film 31, a spin-on-glass (SOG) film 32, and a second oxide film 33. The via 30 is formed and patterned to form a via hole exposing the second and fourth wires 22 and 24, and then the plug 40 is formed by filling the via hole with a metal material. Subsequently, a second metal layer 50 connected to the first metal layers 22 and 24, respectively, is formed on the second oxide layer 33 through the plug 40, and a third oxide layer 60 is formed thereon. Next, a photosensitive film pattern 70 is formed on the third oxide film 60 to expose the second metal layer 50 and the third wiring 23.

다음, 도 1b에 도시한 바와 같이 감광막 패턴(70)을 마스크로 제3 산화막(60)과 층간 절연막(30)을 식각한다. 이때, 제2 금속층(50)은 상부의 제3 산화막(60)이 제거되어 제2 금속층(50)이 드러나고, 제3 배선(23)은 상부에 층간 절연막(30)이 2,000 Å 내지 3,000 Å 정도 남도록 한다.Next, as illustrated in FIG. 1B, the third oxide layer 60 and the interlayer insulating layer 30 are etched using the photoresist pattern 70 as a mask. At this time, the second metal layer 50 is removed, the upper third oxide film 60 is removed, the second metal layer 50 is exposed, the third wiring 23 has an interlayer insulating film 30 on the top of about 2,000 ~ 3,000 3,000 To remain.

다음, 레이저를 이용하여 제3 배선(23)을 절단하는 수리 공정을 실시하고, 생성된 금속 찌꺼기(slag)를 습식 식각으로 제거할 수 있다.Next, a repair process of cutting the third wiring 23 using a laser may be performed, and the generated metal slag may be removed by wet etching.

그런데, 이와 같은 공정에서 제3 배선(23) 상부의 층간 절연막(30)을 제거하는 공정시 층간 절연막(30)의 두께가 20,000Å 정도의 두께로 매우 두꺼우므로 남기고자 하는 층간 절연막(30)의 두께가 일정하지 않아 레이저 수리시 레이저 빔이남아있는 층간 절연막(30)을 통과하지 못할 수도 있다.However, in the process of removing the interlayer insulating film 30 on the upper part of the third wiring 23 in this process, the thickness of the interlayer insulating film 30 is about 20,000 Å, which is very thick. Since the thickness is not constant, the laser beam may not pass through the interlayer insulating layer 30 remaining in the laser repair.

한편, 제3 배선(23) 상부를 덮는 절연막의 두께를 일정하게 하기 위해 제3 배선(23) 상부의 층간 절연막(30)을 모두 제거한 다음, 그 위에 산화막을 형성할 수도 있으나, 이 경우에는 도 1c에 도시한 바와 같이 제3 배선(23)의 양쪽 가장자리 부분이 제거되어 모양이 일정하지 않으므로 레이저 빔을 맞추기 어려운 문제가 있다.Meanwhile, in order to make the thickness of the insulating film covering the upper part of the third wiring 23 constant, the interlayer insulating film 30 on the upper part of the third wiring 23 may be removed, and then an oxide film may be formed thereon. As shown in 1c, since both edge portions of the third wiring 23 are removed and the shape is not constant, it is difficult to match the laser beam.

본 발명의 과제는 레이저 수리를 위한 공정시 불량이 발생하는 것을 방지하는 것이다.An object of the present invention is to prevent the occurrence of defects in the process for laser repair.

본 발명의 다른 과제는 여분의 배선 상부를 덮는 절연막의 두께를 일정하게 제어하는 방법을 제시하는 것이다.Another object of the present invention is to provide a method for controlling the thickness of the insulating film covering the upper part of the excess wiring constantly.

도 1a 내지 도 1c는 종래의 기술에 따른 반도체 소자의 제조 방법을 공정 순서에 따라 도시한 단면도이고,1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, according to a process sequence;

도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 제조 방법을 공정 순서에 따라 도시한 단면도이며,2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention in a process sequence.

도 3은 도 2f에서 A 부분을 확대한 도면이다.FIG. 3 is an enlarged view of a portion A in FIG. 2F.

이러한 과제를 해결하기 위해 본 발명에서는 여분의 배선을 덮는 절연막 중간에 질화막을 형성한다.In order to solve this problem, in the present invention, a nitride film is formed in the middle of the insulating film covering the excess wiring.

본 발명에 따른 반도체 소자의 제조 방법에서는 하부 배선을 포함하는 기판 위에 여분의 배선을 적어도 하나 이상 포함하는 제1 금속층을 형성하고, 그 위에 제1 절연막, 제2 절연막, 제3 절연막을 형성한다. 다음, 제1 금속층의 일부와 연결되어 있는 제2 금속층을 형성한 후, 제4 절연막을 형성하고, 제4 절연막, 제3 절연막, 제2 절연막을 식각한다. 이때, 제2 절연막은 질화막으로 형성한다.In the method of manufacturing a semiconductor device according to the present invention, a first metal layer including at least one or more extra wirings is formed on a substrate including lower wirings, and a first insulating film, a second insulating film, and a third insulating film are formed thereon. Next, after forming the second metal layer connected to part of the first metal layer, a fourth insulating film is formed, and the fourth insulating film, the third insulating film, and the second insulating film are etched. At this time, the second insulating film is formed of a nitride film.

여기서, 제2 절연막의 두께는 1,000 Å 내지 1,500 Å로 이루어질 수 있다.Here, the thickness of the second insulating film may be made of 1,000 kPa to 1,500 kPa.

한편, 제1 절연막은 산화막으로 이루어질 수 있으며, 제1 절연막의 두께는 2,000 Å 내지 3,000 Å일 수도 있다.On the other hand, the first insulating film may be formed of an oxide film, the thickness of the first insulating film may be 2,000 kPa to 3,000 kPa.

또한, 제3 절연막은 SOG막과 산화막으로 이루어질 수 있다.In addition, the third insulating film may be formed of an SOG film and an oxide film.

본 발명은 여분의 배선을 레이저 수리하는 단계를 더 포함할 수도 있다.The invention may further comprise laser repairing the excess wiring.

이와 같이 본 발명에 따른 반도체 소자의 제조 방법에서는 여분의 배선을 덮는 산화막 사이에 질화막을 형성하여 레이저 수리를 위해 여분의 배선 상부의 절연막을 제거할 때 질화막과 산화막의 식각 선택비 차이를 이용하여 식각하고 질화막을 제거함으로써 질화막 하부의 산화막이 일정한 두께를 가지도록 한다. 따라서 레이저 수리시 불량이 발생하지 않도록 한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, when the nitride film is formed between the oxide films covering the excess wiring, the etching is performed using the difference in the etching selectivity between the nitride film and the oxide film when the insulating film on the upper part of the wiring is removed for laser repair. By removing the nitride film, the oxide film under the nitride film has a constant thickness. Therefore, no defects occur during laser repair.

그러면, 첨부한 도면을 참조하여 본 발명에 따른 실시예에 대하여 상세히 설명하도록 한다.Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 도 2a에 도시한 바와 같이 반도체 소자 및 하부 배선층(도시하지 않음)을 포함하는 반도체 기판(110) 위에 제1 내지 제4 배선(121, 122, 123, 124)으로 이루어진 제1 금속층(121, 122, 123, 124)을 형성한 후, 그 위에 제1 산화막(130)과 질화막(140)을 각각 2,000 Å 내지 3,000 Å, 1,000 Å 내지 1,500 Å 정도의 두께로 형성한다.First, as shown in FIG. 2A, a first metal layer 121 including first to fourth wirings 121, 122, 123, and 124 on a semiconductor substrate 110 including a semiconductor device and a lower wiring layer (not shown). , 122, 123, and 124, and then, the first oxide film 130 and the nitride film 140 are formed thereon at a thickness of 2,000 kPa to 3,000 kPa and 1,000 kPa to 1,500 kPa, respectively.

다음, 도 2b에 도시한 바와 같이 표면을 평평하게 하기 위해 SOG(spin-on-glass)막(150)을 형성하고, 제2 산화막(160)을 형성한다. 다음, 제2 산화막(160), SOG막(150), 질화막(140) 그리고 제1 산화막(130)을 패터닝하여 제2 배선 및 제4 배선(122, 124)을 드러내는 비아 홀을 형성한 다음, 비아 홀 내부를 금속 물질로채워 플러그(170)를 형성한다. 이어, 제2 산화막(160) 상부에 플러그(170)를 통해 제1 금속층(122, 124)과 각각 연결되어 있는 제2 금속층(180)을 형성한다.Next, as shown in FIG. 2B, a spin-on-glass (SOG) film 150 is formed to flatten the surface, and a second oxide film 160 is formed. Next, the second oxide film 160, the SOG film 150, the nitride film 140, and the first oxide film 130 are patterned to form via holes exposing the second wiring lines and the fourth wirings 122 and 124. The plug 170 is formed by filling the via hole with a metal material. Subsequently, a second metal layer 180 connected to the first metal layers 122 and 124, respectively, is formed on the second oxide layer 160 through the plug 170.

이어, 도 2c에 도시한 바와 같이 제2 금속층(180) 상부에 제3 산화막(190)을 형성하고, 그 위에 제2 금속층(180)과 제3 배선(123)을 드러내기 위해 감광막 패턴(200)을 형성한다.Subsequently, as shown in FIG. 2C, the third oxide film 190 is formed on the second metal layer 180, and the photoresist pattern 200 is exposed to expose the second metal layer 180 and the third wiring 123 thereon. ).

다음, 감광막 패턴(200)을 마스크로 제3 산화막(190)과 제2 산화막(160), SOG막(150) 및 질화막(140)을 순차적으로 식각한다. 이때, 산화막(150, 160, 190)과 질화막(140)은 식각 선택비가 7 내지 8 : 1이 되도록 하여 도 2d에 도시한 바와 같이 산화막(150, 160, 190)이 위치에 따라 식각되는 정도가 다르더라도 질화막(140)에 의해 과도 식각(over etch)되지 않도록 한다.Next, the third oxide film 190, the second oxide film 160, the SOG film 150, and the nitride film 140 are sequentially etched using the photoresist pattern 200 as a mask. In this case, the oxide films 150, 160, 190 and the nitride film 140 may have an etching selectivity of 7 to 8: 1 so that the degree of etching of the oxide films 150, 160 and 190 according to the position is shown in FIG. 2D. Even if different, it is not to be over etched by the nitride film 140.

다음, 도 2e에 도시한 바와 같이 남아 있는 질화막(140)을 제거하여 제3 배선(123) 상부에 일정한 두께를 가지는 제1 산화막(130)을 남긴다.Next, as shown in FIG. 2E, the remaining nitride film 140 is removed to leave the first oxide film 130 having a predetermined thickness on the third wiring 123.

다음, 도 2f에 도시한 바와 같이 레이저 빔을 이용하여 제3 배선(123)을 수리한다. 도 2f는 레이저 수리한 부분만을 나타내는 단면도로써 도시한 바와 같이 제3 배선(123)은 제거되어 없어지고 제1 산화막(130)만 남게 된다.Next, as illustrated in FIG. 2F, the third wiring 123 is repaired using the laser beam. 2F is a cross-sectional view showing only the repaired portion of the laser, and as shown in the drawing, the third wiring 123 is removed and only the first oxide film 130 remains.

도 3은 도 2f에서 A 부분을 도시한 평면도로써 제3 배선(123)이 잘려진 모습을 나타낸다.3 is a plan view illustrating a portion A in FIG. 2F, in which the third wiring 123 is cut off.

다음, 레이저 수리시 생성된 금속 찌꺼기를 습식 식각 방법으로 제거한다.Next, the metal residue generated during laser repair is removed by a wet etching method.

이와 같이 본 발명에서는 질화막을 사용하여 여분의 배선 상부에 일정한 두께를 가지는 산화막을 형성할 수 있다.As described above, in the present invention, an oxide film having a constant thickness can be formed on the excess wiring by using a nitride film.

본 발명에서는 여분의 배선을 덮는 산화막 중간에 질화막을 형성하고 배선을 수리하기 위한 식각 공정시 질화막과 산화막의 식각 선택비를 이용하여 식각되는 정도를 제어함으로써 여분의 배선 상부에 남기는 산화막의 두께를 균일하게 할 수 있다. 따라서, 레이저 수리시 불량이 발생하는 것을 방지할 수 있다.In the present invention, by forming a nitride film in the middle of the oxide film covering the excess wiring and controlling the degree of etching using the etching selectivity of the nitride film and the oxide film during the etching process for repairing the wiring, the thickness of the oxide film left on the excess wiring is uniform. It can be done. Therefore, it is possible to prevent the occurrence of defects during laser repair.

Claims (6)

하부 배선을 포함하는 기판 위에 여분의 배선을 적어도 하나 이상 포함하는 제1 금속층을 형성하는 단계,Forming a first metal layer including at least one extra wiring on the substrate including the lower wiring; 상기 제1 금속층 상부에 제1 절연막, 제2 절연막, 제3 절연막을 형성하는 단계,Forming a first insulating film, a second insulating film, and a third insulating film on the first metal layer; 상기 제1 금속층의 일부와 연결되어 있는 제2 금속층을 형성하는 단계,Forming a second metal layer connected to a portion of the first metal layer, 제4 절연막을 형성하는 단계,Forming a fourth insulating film, 상기 제4 절연막, 제3 절연막, 제2 절연막을 식각하는 단계Etching the fourth insulating film, the third insulating film, and the second insulating film 를 포함하며,Including; 상기 제2 절연막은 질화막으로 이루어진 반도체 소자의 제조 방법.The second insulating film is a manufacturing method of a semiconductor device consisting of a nitride film. 제1항에서,In claim 1, 상기 제2 절연막의 두께는 1,000 Å 내지 1,500 Å인 반도체 소자의 제조 방법.The thickness of the second insulating film is a semiconductor device manufacturing method of 1,000 to 1,500 kPa. 제2항에서,In claim 2, 상기 제1 절연막은 산화막으로 이루어진 반도체 소자의 제조 방법.The first insulating film is a manufacturing method of a semiconductor device consisting of an oxide film. 제3항에서,In claim 3, 상기 제1 절연막의 두께는2,000 Å 내지 3,000 Å인 반도체 소자의 제조 방법.The first insulating film has a thickness of 2,000 kPa to 3,000 kPa. 제3항에서,In claim 3, 상기 제3 절연막은 SOG막과 산화막으로 이루어진 반도체 소자의 제조 방법.The third insulating film is a manufacturing method of a semiconductor device consisting of a SOG film and an oxide film. 제1항에서,In claim 1, 상기 여분의 배선을 레이저 수리하는 단계를 더 포함하는 반도체 소자의 제조 방법.And laser repairing the excess wiring.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040002286A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100800937B1 (en) * 2006-09-11 2008-02-04 동부일렉트로닉스 주식회사 Method for controlling thickness of fuse oxide layer in a semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040002286A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100800937B1 (en) * 2006-09-11 2008-02-04 동부일렉트로닉스 주식회사 Method for controlling thickness of fuse oxide layer in a semiconductor devices

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