KR20080013184A - Method for forming metal contact in semiconductor device - Google Patents

Method for forming metal contact in semiconductor device Download PDF

Info

Publication number
KR20080013184A
KR20080013184A KR1020060074345A KR20060074345A KR20080013184A KR 20080013184 A KR20080013184 A KR 20080013184A KR 1020060074345 A KR1020060074345 A KR 1020060074345A KR 20060074345 A KR20060074345 A KR 20060074345A KR 20080013184 A KR20080013184 A KR 20080013184A
Authority
KR
South Korea
Prior art keywords
interlayer insulating
semiconductor substrate
forming
region
interlayer dielectric
Prior art date
Application number
KR1020060074345A
Other languages
Korean (ko)
Inventor
조한우
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060074345A priority Critical patent/KR20080013184A/en
Publication of KR20080013184A publication Critical patent/KR20080013184A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

A method for forming a metal contact of a semiconductor device is provided to expose a metal electrode layer in a peripheral unit in an etching process for forming a contact hole by using a difference between etch rates in a central unit and the peripheral unit of a semiconductor substrate. An isolation layer(302) is formed on a semiconductor substrate(300) having a cell region and a peripheral region. A word line is arranged on an upper portion of the semiconductor substrate. A bit line is formed on an upper portion of the word line. A dielectric is arranged between the bit lines. A capacitor(310) is formed on the bit line and the dielectric only in the cell region. The capacitor includes a node-separated storage node(311), an insulating layer(312), and a plate node(313). An interlayer dielectric(320) is formed on the whole surface of the semiconductor substrate. The interlayer dielectric is a laminated structure of a first interlayer dielectric(321) arranged on the peripheral region and a second interlayer dielectric(322) arranged on the cell region and the peripheral region. A photoresist is applied to the semiconductor substrate where the interlayer dielectric is formed to form a photoresist pattern(325). An ion implantation process is performed on the interlayer dielectric in the peripheral region exposed by the photoresist pattern.

Description

반도체소자의 금속컨택 형성방법{Method for forming metal contact in semiconductor device}Method for forming metal contact in semiconductor device

도 1은 종래의 반도체소자의 금속컨택 형성방법을 설명하기 위하여 나타내 보인 단면도이다.1 is a cross-sectional view illustrating a metal contact forming method of a conventional semiconductor device.

도 2 및 도 3은 본 발명에 의한 반도체소자의 금속컨택 형성방법을 설명하기 위하여 나타내보인 단면도들이다.2 and 3 are cross-sectional views illustrating a method for forming a metal contact of a semiconductor device according to the present invention.

도 4는 주입된 불순물의 농도에 따른 여러 가지 산화막의 식각율을 나타낸 그래프이다.4 is a graph illustrating etching rates of various oxide layers according to concentrations of implanted impurities.

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자의 금속컨택 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a metal contact of a semiconductor device.

반도체소자의 금속컨택은 현재 대부분의 디램(DRAM) 소자에서 금속층과 비트라인, 커패시터의 플레이트 전극과 연결되어 소자들에 전력(power)과 신호를 전달하는 역할을 한다.The metal contact of the semiconductor device is currently connected to the metal layer, the bit line, and the plate electrode of the capacitor in most DRAM devices to transfer power and signals to the devices.

도 1은 종래의 반도체소자의 금속컨택 형성방법을 설명하기 위하여 나타내 보인 단면도이다.1 is a cross-sectional view illustrating a metal contact forming method of a conventional semiconductor device.

도 1을 참조하면, 셀영역 및 주변회로영역을 갖는 반도체기판(100)에 소자분리막(102)을 형성하여 활성영역을 한정한다. 다음에 반도체기판(100) 위에 통상의 방법을 사용하여 트랜지스터를 형성하고, 이에 따라 반도체기판(100) 상부에는 워드라인이 배치된다. 워드라인을 포함하는 트랜지스터를 형성한 후에는, 워드라인 상부에 비트라인을 형성한다. 비트라인 사이에는 절연막이 배치된다. 다음에 비트라인 및 절연막 위에 커패시터(110)를 형성하는데, 이 커패시터(110)는 셀영역에만 형성한다. 커패시터(110)는 노드 분리된 스토리지 노드(111), 유전체막(112) 및 플레이트 노드(113)를 포함한다.Referring to FIG. 1, an isolation region 102 is formed in a semiconductor substrate 100 having a cell region and a peripheral circuit region to define an active region. Next, a transistor is formed on the semiconductor substrate 100 using a conventional method, and thus a word line is disposed on the semiconductor substrate 100. After forming the transistor including the word line, a bit line is formed over the word line. An insulating film is disposed between the bit lines. Next, a capacitor 110 is formed over the bit line and the insulating film. The capacitor 110 is formed only in the cell region. The capacitor 110 may include a node separated storage node 111, a dielectric layer 112, and a plate node 113.

다음에 층간절연막(120)을 형성하는데, 주변회로영역에 배치되는 제1 층간절연막(121)과, 셀영역 및 주변회로영역에 배치되는 제2 층간절연막(122)이 순차적으로 적층되는 구조로 형성한다. 소정의 마스크막패턴(미도시)을 이용해 층간절연막(120)의 일부를 식각하여 금속컨택을 위한 컨택홀(130)을 형성한다. 그러면 셀영역에서는 커패시터(110)의 플레이트노드(113)가 노출되며, 주변회로영역에서는 비트라인 도전막이 노출된다. 이후에 컨택홀(130)을 금속막으로 채우면 금속컨택이 만들어진다.Next, an interlayer insulating film 120 is formed. The first interlayer insulating film 121 disposed in the peripheral circuit region and the second interlayer insulating layer 122 disposed in the cell region and the peripheral circuit region are sequentially stacked. do. A portion of the interlayer insulating layer 120 is etched using a predetermined mask layer pattern (not shown) to form a contact hole 130 for metal contact. Then, the plate node 113 of the capacitor 110 is exposed in the cell region, and the bit line conductive layer is exposed in the peripheral circuit region. Thereafter, when the contact hole 130 is filled with a metal film, a metal contact is made.

금속컨택을 형성하기 위한 컨택홀(130)은 매우 높은 어스펙트비(aspect ratio)를 갖는 것으로, 약 20,000Å 정도의 스토리지 노드와, 비트라인 상부에 형성된 층간절연막을 식각하여 비트라인이 노출되도록 해야 한다. 따라서, 스토리지 노드의 높이가 계속 높아지고 있는 현 상황에서 금속컨택 공정은 많은 문제점을 가 지고 있다. 그 중 하나가 컨택홀을 형성하기 위한 식각공정시 반응가스의 흐름(flow)의 차이에 의해 반도체기판의 중심부에 배치되는 셀영역과 주변부에 배치되는 주변회로영역 사이에 식각율이 서로 달라서 주변회로영역의 컨택홀이 제대로 형성되지 않는다는 것이다. 즉, 반도체기판의 중심부를 기준으로 식각율을 조절하면 주변부에서는 층간절연막의 식각이 덜 이루어져, 도 1에 도시된 바와 같이 비트라인이 노출되지 않는 문제점이 발생하게 된다. 이러한 문제를 해결하기 위하여 주변부의 패턴의 크기(critical dimension)를 중심부보다 크게 하여 공정을 진행하고 있다. 그러나, 이렇게 중심부와 주변부의 패턴의 크기를 다르게 할 경우 금속컨택과 비트라인 사이의 오버레이 불량(overlay fail)이 발생하여 누설전류가 야기되는 문제점이 있다.The contact hole 130 for forming a metal contact has a very high aspect ratio, and a bit line is exposed by etching a storage node of about 20,000 와 and an interlayer insulating layer formed on the bit line. do. Therefore, the metal contact process has many problems in the current situation where the height of the storage node continues to increase. One of them is the peripheral circuit because the etching rate is different between the cell region disposed in the center of the semiconductor substrate and the peripheral circuit region disposed in the peripheral portion due to the difference in the flow of reaction gas during the etching process for forming the contact hole. The contact holes in the area are not formed properly. That is, if the etching rate is adjusted based on the center of the semiconductor substrate, the etching of the interlayer insulating layer is less performed at the periphery, resulting in a problem that the bit line is not exposed as shown in FIG. 1. In order to solve this problem, the process is performed by making the critical dimension of the pattern of the periphery larger than the center. However, when the size of the pattern of the center portion and the periphery is different, there is a problem in that an overlay failure occurs between the metal contact and the bit line, causing leakage current.

본 발명이 이루고자 하는 기술적 과제는, 반도체기판 중심부와 주변부에서의 층간절연막의 식각율의 차이로 인해 컨택홀 형성을 위한 식각공정에서 주변부의 금속전극막이 노출되지 않는 현상을 방지할 수 있는 반도체소자의 금속컨택 형성방법을 제공하는 것이다.The technical problem to be achieved by the present invention is to provide a semiconductor device capable of preventing the metal electrode film from being exposed in the etching process for forming the contact hole due to the difference in the etching rate of the interlayer insulating film at the center and the peripheral portion of the semiconductor substrate. It is to provide a method for forming a metal contact.

상기 기술적 과제를 이루기 위하여 본 발명에 의한 반도체소자의 금속컨택 형성방법은, 반도체기판 상에 형성된 금속전극막을 덮는 층간절연막을 형성하는 단계와, 주변회로영역의 층간절연막 상에 금속컨택이 형성될 영역을 노출시키는 마스크패턴을 형성하는 단계와, 노출된 층간절연막에 불순물이온을 주입하는 단계, 및 마스크패턴을 식각 마스크로 하여 층간절연막을 식각하여 금속전극막을 노출시키는 컨택홀을 형성하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of forming a metal contact of a semiconductor device, the method including: forming an interlayer insulating film covering a metal electrode film formed on a semiconductor substrate; Forming a mask pattern exposing the insulating film, implanting impurity ions into the exposed interlayer insulating film, and forming a contact hole exposing the metal electrode film by etching the interlayer insulating film using the mask pattern as an etch mask. .

본 발명에 있어서, 셀영역의 금속전극막은 플레이트노드이고, 주변회로영역의 금속전극막은 비트라인이며, 층간절연막은 산화막으로 형성한다.In the present invention, the metal electrode film in the cell region is a plate node, the metal electrode film in the peripheral circuit region is a bit line, and the interlayer insulating film is formed of an oxide film.

이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 2 및 도 3은 본 발명에 의한 반도체소자의 금속컨택 형성방법을 설명하기 위하여 나타내보인 단면도들이다.2 and 3 are cross-sectional views illustrating a method for forming a metal contact of a semiconductor device according to the present invention.

도 2를 참조하면, 셀영역 및 주변회로영역을 갖는 반도체기판(300)에 소자분리막(302)을 형성하여 활성영역을 정의한다. 다음에 반도체기판(300) 상에 통상의 방법을 사용하여 트랜지스터를 형성하고, 이에 따라 반도체기판(300) 상부에는 워드라인이 배치된다. 워드라인을 포함하는 트랜지스터를 형성한 후에는, 워드라인 상부에 비트라인을 형성한다. 비트라인 사이에는 절연막이 배치된다. 다음에 비트라인 및 절연막 위에 커패시터(310)를 형성하는데, 이 커패시터(310)는 셀영역에만 형성한다. 커패시터(310)는 노드 분리된 스토리지 노드(311), 유전체막(312) 및 플레이트 노드(313)를 포함한다. Referring to FIG. 2, an isolation region 302 is formed in a semiconductor substrate 300 having a cell region and a peripheral circuit region to define an active region. Next, a transistor is formed on the semiconductor substrate 300 using a conventional method, and thus a word line is disposed on the semiconductor substrate 300. After forming the transistor including the word line, a bit line is formed over the word line. An insulating film is disposed between the bit lines. Next, a capacitor 310 is formed over the bit line and the insulating film, which is formed only in the cell region. The capacitor 310 includes a node separated storage node 311, a dielectric film 312 and a plate node 313.

다음에, 반도체기판의 전면에 층간절연막(320)을 형성한다. 이 층간절연막(320)은 주변회로영역에 배치되는 제1 층간절연막(321)과, 셀영역 및 주변회로영 역에 배치되는 제2 층간절연막(322)이 순차적으로 적층되는 구조로 형성한다. Next, an interlayer insulating film 320 is formed over the entire surface of the semiconductor substrate. The interlayer insulating film 320 is formed in such a manner that a first interlayer insulating film 321 disposed in the peripheral circuit region and a second interlayer insulating film 322 disposed in the cell region and the peripheral circuit region are sequentially stacked.

이어서, 층간절연막(320)이 형성된 반도체기판 상에 포토레지스트를 도포한 후 노광 및 현상을 실시하여 주변회로영역의 금속컨택이 형성될 영역을 노출시키도록 포토레지스트 패턴(325)을 형성한다. Subsequently, after the photoresist is coated on the semiconductor substrate on which the interlayer insulating layer 320 is formed, the photoresist pattern 325 is formed to expose the region where the metal contact of the peripheral circuit region is to be formed by performing exposure and development.

다음에, 포토레지스트 패턴(325)에 의해 노출된 주변회로영역의 상기 층간절연막(320)에 소정의 이온주입 공정을 실시한다. 이렇게 주변회로영역의 층간절연막(320)에 주입된 불순물이온들은 층간절연막의 격자(lattice)의 결합을 약화시키는 결함(defect)으로 작용한다. 따라서, 후속되는 컨택홀 형성을 위한 식각공정에서 주변회로영역의 층간절연막의 식각속도가 이온주입되지 않은 셀영역의 층간절연막의 식각속도에 비해 빠르게 하는 역할을 한다. 상기 이온주입 공정에서 주입되는 불순물의 농도와 주입 에너지는 층간절연막(320)의 종류나 두께 등에 따라 달라질 수 있다.Next, a predetermined ion implantation process is performed on the interlayer insulating film 320 in the peripheral circuit region exposed by the photoresist pattern 325. The impurity ions implanted into the interlayer insulating film 320 in the peripheral circuit region act as a defect that weakens the bonding of the lattice of the interlayer insulating film. Therefore, in the subsequent etching process for forming the contact hole, the etching speed of the interlayer insulating film in the peripheral circuit region is faster than the etching rate of the interlayer insulating film in the cell region where the ion is not implanted. The concentration of the impurity implanted in the ion implantation process and the implantation energy may vary depending on the type or thickness of the interlayer insulating layer 320.

도 3을 참조하면, 포토레지스트 패턴을 제거한 다음 상기 층간절연막(320) 위에 셀영역 및 주변회로영역의 컨택영역을 노출시키는 포토레지스트 패턴(도시되지 않음)을 형성하고, 이를 이용해 층간절연막(320)의 일부를 식각하여 금속컨택을 위한 컨택홀(330)을 형성한다. 그러면 셀영역에서는 커패시터(310)의 플레이트노드(313)가 노출되며, 주변회로영역에서는 비트라인 도전막이 노출된다. 상기 층간절연막(320)을 식각하는 공정에서 셀영역과 주변회로영역에서 식각가스의 흐름의 차이로 인해 식각율이 다르게 되는 문제가 발생하나, 주변회로영역의 층간절연막은 이미 이온주입에 의해 격자들의 결합이 약화되어 있기 때문에 도시된 바와 같이 컨 택홀이 성공적으로 형성된다. 이후에 컨택홀(330)을 금속막으로 매립하여 금속컨택을 형성한다.Referring to FIG. 3, after removing the photoresist pattern, a photoresist pattern (not shown) is formed on the interlayer insulating layer 320 to expose the contact regions of the cell region and the peripheral circuit region. The interlayer insulating layer 320 is then used. A portion of the portion is etched to form a contact hole 330 for the metal contact. Then, the plate node 313 of the capacitor 310 is exposed in the cell region, and the bit line conductive layer is exposed in the peripheral circuit region. In the process of etching the interlayer dielectric layer 320, the etching rate is different due to the difference in the flow of the etching gas in the cell region and the peripheral circuit region. Since the bond is weakened, the contact hole is successfully formed as shown. Thereafter, the contact hole 330 is filled with a metal film to form a metal contact.

도 4는 산화막에 주입된 불순물의 농도에 따른 여러 가지 산화막의 식각율을 나타낸 그래프로서, 이온주입 에너지가 40KeV일 때의 고온산화막(HTO), 고밀도플라즈마산화막(HDP) 및 열산화막(thermal oxide)의 식각율을 각각 나타낸다. 도시된 바와 같이, 산화막의 식각율은 불순물의 농도가 높을수록 크다는 것을 알 수 있다.4 is a graph showing the etching rate of various oxide films according to the concentration of impurities implanted in the oxide film. The etching rate of each is shown. As shown, it can be seen that the etching rate of the oxide film is larger as the concentration of impurities is higher.

이와 같이 이온주입에 따른 산화막의 식각율의 차이를 이용하면 금속컨택 형성공정뿐만 아니라, 층간절연막의 높이 균일도(uniformity)를 높이는 평탄화 공정에 적용할 수 있다. 즉, 단차가 높은 산화막에 선택적으로 이온주입을 실시하여 후속 식각공정에서의 식각율을 높임으로써 층간절연막의 평탄화를 이룰 수 있다.By using the difference in the etching rate of the oxide film according to the ion implantation as described above, it can be applied not only to the metal contact forming process but also to the planarization process to increase the height uniformity of the interlayer insulating film. In other words, by selectively implanting ions into the oxide film having a high level of difference, the etch rate can be increased in a subsequent etching process to planarize the interlayer insulating film.

상술한 본 발명에 의한 반도체소자의 금속컨택 형성방법에 따르면, 이온주입된 산화막의 식각율이 그렇지 않은 산화막의 식각율보다 빠른 성질을 이용하여 주변회로영역의 층간절연막에만 선택적으로 불순물이온을 주입함으로써, 컨택홀을 형성하기 위한 식각공정에서 주변회로영역의 층간절연막의 식각이 덜 이루어져 컨택홀이 제대로 형성되지 않은 문제점을 해소할 수 있다. 따라서, 반도제소자의 제조수율을 향상시킬 수 있으며, 식각공정의 마진(margin)을 증가시킬 수 있다.According to the method for forming a metal contact of a semiconductor device according to the present invention, by implanting impurity ions only in the interlayer insulating film of the peripheral circuit region by using the property that the etching rate of the ion implanted oxide film is faster than the etching rate of the oxide film that is not In the etching process for forming the contact hole, the etching of the interlayer insulating layer in the peripheral circuit area is less etched. Therefore, the manufacturing yield of the semiconductor device can be improved, and the margin of the etching process can be increased.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않으며 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형 및 개량이 가능함은 명백하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and improvements can be made by those skilled in the art within the technical spirit of the present invention. Is obvious.

Claims (3)

반도체기판 상에 형성된 금속전극막을 덮는 층간절연막을 형성하는 단계;Forming an interlayer insulating film covering the metal electrode film formed on the semiconductor substrate; 주변회로영역의 상기 층간절연막 상에 금속컨택이 형성될 영역을 노출시키는 마스크패턴을 형성하는 단계;Forming a mask pattern on the interlayer insulating film in a peripheral circuit area to expose a region where a metal contact is to be formed; 상기 노출된 층간절연막에 불순물이온을 주입하는 단계; 및Implanting impurity ions into the exposed interlayer dielectric film; And 상기 마스크패턴을 식각 마스크로 하여 상기 층간절연막을 식각하여 상기 금속전극막을 노출시키는 컨택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 금속컨택 형성방법.Forming a contact hole for exposing the metal electrode film by etching the interlayer insulating layer using the mask pattern as an etch mask. 제1항에 있어서, 셀영역의 상기 금속전극막은 플레이트노드이고, 주변회로영역의 상기 금속전극막은 비트라인인 것을 특징으로 하는 반도체소자의 금속컨택 형성방법.The method of claim 1, wherein the metal electrode film in the cell region is a plate node, and the metal electrode film in the peripheral circuit region is a bit line. 제1항에 있어서, 상기 층간절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체소자의 금속컨택 형성방법.The method of claim 1, wherein the interlayer insulating film is formed of an oxide film.
KR1020060074345A 2006-08-07 2006-08-07 Method for forming metal contact in semiconductor device KR20080013184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060074345A KR20080013184A (en) 2006-08-07 2006-08-07 Method for forming metal contact in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060074345A KR20080013184A (en) 2006-08-07 2006-08-07 Method for forming metal contact in semiconductor device

Publications (1)

Publication Number Publication Date
KR20080013184A true KR20080013184A (en) 2008-02-13

Family

ID=39340974

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060074345A KR20080013184A (en) 2006-08-07 2006-08-07 Method for forming metal contact in semiconductor device

Country Status (1)

Country Link
KR (1) KR20080013184A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997400B2 (en) 2015-12-11 2018-06-12 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997400B2 (en) 2015-12-11 2018-06-12 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US10347527B2 (en) 2015-12-11 2019-07-09 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same

Similar Documents

Publication Publication Date Title
JP2005079576A (en) Semiconductor device and manufacturing method therefor
JP2000058482A (en) Self-aligned contact and manufacture thereof
JP2009060074A (en) Method for forming contact of semiconductor device
JP5090667B2 (en) Method for forming metal wiring and contact plug of flash memory device
KR20080013184A (en) Method for forming metal contact in semiconductor device
KR20080086692A (en) Method for manufacturing semiconductor device
KR20080002487A (en) Method for forming landing plug of semiconductor device
KR100506050B1 (en) Contact formation method of semiconductor device
KR100910868B1 (en) Method for fabrication of semiconductor device
KR100319169B1 (en) Fabricating method for storage node of semiconductor device
KR100390999B1 (en) A method for forming of a semiconductor device
KR100546210B1 (en) Bit line contact formation method of semiconductor device
KR20010056239A (en) Apparatus of semiconductor device attaining improved overlay margin and manufacturing method thereof
KR20040008600A (en) Method for forming a contact hole in semiconductor memory device
KR100244266B1 (en) method for fabricating isolation rejoin of semiconductor device
KR100624947B1 (en) Flash memory device and method of manufacturing the same
KR0144922B1 (en) Manufacturing method of high density semiconductor memory device
KR20020025351A (en) method for manufacturing of semiconductor device
KR20060105291A (en) Method for manufacturing semiconductor device
KR20080069428A (en) Method for fabricating semiconductor device
KR20050056353A (en) Method for forming landing plug poly of semiconductor device
KR20030003306A (en) Method for fabricating a landing plug of semiconductor device
KR20050002479A (en) method for forming landing plug
KR20060118734A (en) Manufacturing method of flash memory device
KR20060000898A (en) Method for fabrication of semiconductor device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid