KR100303317B1 - Method for forming fuse box of semiconductor device - Google Patents
Method for forming fuse box of semiconductor device Download PDFInfo
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- KR100303317B1 KR100303317B1 KR1019980024426A KR19980024426A KR100303317B1 KR 100303317 B1 KR100303317 B1 KR 100303317B1 KR 1019980024426 A KR1019980024426 A KR 1019980024426A KR 19980024426 A KR19980024426 A KR 19980024426A KR 100303317 B1 KR100303317 B1 KR 100303317B1
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- etching
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 30
- 229920005591 polysilicon Polymers 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 description 6
- 238000002161 passivation Methods 0.000 description 4
- 238000007664 blowing Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
본 발명은 퓨즈(fuse) 상에 잔류하는 절연막 두께의 편차를 줄일 수 있는 퓨즈박스(fuse box) 형성 방법에 관한 것으로, 퓨즈 상의 절연막 사이에 식각정지층을 삽입시켜 식각 대상막의 두께를 감소시키고, 식각 속도를 조절함으로써 퓨즈 상에 잔류하는 절연막 두께의 편차를 감소시키는 방법이다. 이에 의해, 반도체 장치의 리페어(repair) 수율을 향상시킬 수 있다.The present invention relates to a method for forming a fuse box that can reduce the variation in the thickness of the insulating film remaining on the fuse, and inserts an etch stop layer between the insulating film on the fuse to reduce the thickness of the etching target film, By controlling the etching rate, the thickness of the insulating film remaining on the fuse is reduced. Thereby, the repair yield of a semiconductor device can be improved.
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 퓨즈(fuse) 상에 잔류하는 절연막 두께의 편차를 줄일 수 있는 퓨즈박스(fuse box) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of forming a fuse box that can reduce variation in thickness of an insulating film remaining on a fuse.
일반적으로, 반도체 장치 제조를 위한 설계시 수율을 증가시키기 위한 목적으로, 결함있는 소자 또는 회로를 대체하기 위하여 여분의 회로를 메모리 설계시 부가한다. 여분의 회로는 메모리 어레이(memory array)에 인접하여 형성되는 예비의 로 및 칼럼(row and column)으로 이루어지며, 불량 메모리 단위가 발생하면 불량 회로를 구성하는 로 및 칼럼이 예비의 로 및 칼럼으로 대체된다. 불량 메모리의 대체는 메모리 소자에 형성된 퓨즈(fuse)를 선택적으로 끊음(blowing)으로써 이루어진다. 대체로 퓨즈는 폴리실리콘막으로 형성되며, 과도한 전류를 흘리거나 레이저 빔을 조사하여 퓨즈를 끊는다.Generally, extra circuitry is added in memory design to replace defective devices or circuits for the purpose of increasing yield in designing for semiconductor device fabrication. The spare circuit is made up of spare rows and columns formed adjacent to a memory array, and when a bad memory unit occurs, the rows and columns constituting the bad circuit are converted into spare rows and columns. Replaced. Replacement of the bad memory is accomplished by selectively blowing a fuse formed in the memory element. Usually, the fuse is formed of a polysilicon film, and blows excessive current or irradiates a laser beam to blow the fuse.
도1a 및 도1b는 종래기술에 따른 반도체 장치의 퓨즈박스 형성 공정 단면도이다.1A and 1B are cross-sectional views of a fuse box forming process of a semiconductor device according to the related art.
도1a는 반도체 기판(10) 상에 형성된 제1 절연막(11) 상에 폴리실리콘막으로 퓨즈(fuse)(12)를 형성한 후, 제2 절연막(13) 및 보호막(passivation layer)(14)을 형성하고, 보호막(14) 상에 감광막 패턴(20)을 형성한 상태를 보이고 있다.FIG. 1A illustrates a fuse 12 formed of a polysilicon film on a first insulating film 11 formed on a semiconductor substrate 10, followed by a second insulating film 13 and a passivation layer 14. And the photosensitive film pattern 20 is formed on the protective film 14.
도1b는 감광막 패턴(20)을 식각마스크로 보호막(14) 및 제2 절연막(13)을 식각하여, 레이저(laser)로 블로잉(blowing)을 용이하게 할 수 있도록 퓨즈(12) 상에 수백 내지 수천 Å 두께의 제2 절연막(13)을 잔류시킨 것을 나타내고 있다.FIG. 1B shows the protective film 14 and the second insulating film 13 by using the photoresist pattern 20 as an etch mask, and thus, on the fuse 12 to facilitate blowing with a laser. It shows that the 2nd insulating film 13 of several thousand micrometers thick was left.
이후에 퓨즈 블로잉을 용이하게 하기 위해서 퓨즈(12) 상에 잔류하는 제2 절연막(13) 두께(d)의 편차를 ±1000 Å 이하가 되도록 조절하는 것이 필요하다. 그러나, 퓨즈(12) 상에 형성되는 제2 절연막(13) 및 보호막(14)의 총 두께는 소자에 따라 20000 Å 내지 30000 Å에 달하는데, 그와 같은 두께를 한 번에 식각하는 공정에서는 식각시 절연막의 재증착과 식각 균일도(uniformity) 문제 때문에, 퓨즈(12) 상에 잔류하는 제2 절연막 두께의 편차를 ±1000 Å 이하가 되도록 조절하는 것이 용이하지 않다. 그 예로써, 제2 절연막(13) 및 보호막(14)의 총 두께가 30000 Å일 때, 식각 균일도가 5 % 이면, 퓨즈(12) 상에 잔류하는 제2 절연막(13) 두께의 편차는 ±1500 Å이 된다.Afterwards, in order to facilitate fuse blowing, it is necessary to adjust the deviation of the thickness d of the second insulating film 13 remaining on the fuse 12 to be ± 1000 kPa or less. However, the total thicknesses of the second insulating film 13 and the protective film 14 formed on the fuse 12 may range from 20000 kPa to 30000 kPa depending on the device, and in the process of etching such thickness at once, Because of the problem of redeposition and etching uniformity of the insulating film, it is not easy to adjust the variation of the thickness of the second insulating film remaining on the fuse 12 to be less than or equal to ± 1000 GPa. As an example, when the total thickness of the second insulating film 13 and the protective film 14 is 30000 mm, if the etching uniformity is 5%, the deviation of the thickness of the second insulating film 13 remaining on the fuse 12 is ± 1500 kW.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 퓨즈 상에 잔류하는 절연막의 두께 편차를 보다 줄일 수 있는 반도체 장치의 퓨즈박스 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for forming a fuse box of a semiconductor device that can further reduce the thickness variation of the insulating film remaining on the fuse.
도1a 및 도1b 종래 기술에 따른 반도체 장치의 퓨즈박스 형성 공정 단면도1A and 1B are cross-sectional views of a fuse box forming process of a semiconductor device according to the related art.
도2a 내지 도2d는 본 발명의 일실시예에 따른 반도체 장치의 퓨즈박스 형성 공정 단면도2A to 2D are cross-sectional views of a fuse box forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
10: 반도체 기판 11, 13: 산화막10: semiconductor substrate 11, 13: oxide film
12: 퓨즈 14: 보호막12: fuse 14: protective film
상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 형성된 절연막 상에 퓨즈를 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 제1 절연막, 식각정지막 및 제2 절연막을 형성하는 제2 단계; 상기 제2 절연막을 선택적으로 식각하여 상기 식각정지막을 노출시키는 제3 단계; 및 상기 식각정지막 및 제1 절연막의 일부를 선택적으로 제거하여 상기 퓨즈 상에 제1 절연막의 일부를 잔류시키는 제4 단계를 포함하는 반도체 장치의 퓨즈박스 형성 방법을 제공한다.The present invention for achieving the above object is a first step of forming a fuse on an insulating film formed on a semiconductor substrate; A second step of forming a first insulating film, an etch stop film, and a second insulating film on the entire structure in which the first step is completed; Selectively etching the second insulating layer to expose the etch stop layer; And selectively removing a portion of the etch stop layer and the first insulating layer to leave a portion of the first insulating layer on the fuse.
본 발명은 퓨즈 상의 절연막 사이에 식각정지층을 삽입시켜 식각 대상막의 두께를 감소시키고, 식각 속도를 조절함으로써 퓨즈 상에 잔류하는 절연막 두께의 편차를 감소시키는 방법이다.The present invention is a method of reducing the thickness of the insulating film remaining on the fuse by inserting the etch stop layer between the insulating film on the fuse to reduce the thickness of the etching target film, the etching rate.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.
도2a 내지 도2d는 본 발명의 일실시예에 따른 반도체 장치의 퓨즈박스 형성 공정 단면도이다.2A to 2D are cross-sectional views of a fuse box forming process of a semiconductor device according to an embodiment of the present invention.
도2a는 반도체 기판(30) 상에 형성된 절연막(31) 상에 폴리실리콘막으로 퓨즈(fuse)(32)를 형성한 후, 제1 산화막(33), 폴리실리콘막(34), 제2 산화막(35) 및 보호막(36)을 차례로 형성한 상태를 보이고 있다.FIG. 2A shows a fuse 32 formed of a polysilicon film on an insulating film 31 formed on the semiconductor substrate 30, followed by a first oxide film 33, a polysilicon film 34, and a second oxide film. (35) and the protective film 36 are shown in order.
상기 폴리실리콘막(34)은 이후의 상기 제2 산화막(35) 식각 공정에서 식각정지층으로 역할한다. 상기 폴리실리콘막(34)을 대신하여 실리사이드(silicide)를 형성할 수도 있다. DRAM의 경우에는 상기 퓨즈(32)를 트랜지스터의 게이트 전극 형성 단계에서 형성하고, 상기 폴리실리콘막(34)을 비트라인, 캐패시터의 하부전극 또는 캐패시터의 상부전극 형성 단계에서 형성하고, SRAM 또는 플래시 메모리(flash memory) 소자 제조 공정의 경우에는 퓨즈(12) 형성과 보호막(13) 형성 중간에 증착되는 임의의 폴리실리콘막으로 상기 식각정지막을 형성할 수 있다.The polysilicon layer 34 serves as an etch stop layer in the subsequent etching process of the second oxide layer 35. Silicide may be formed in place of the polysilicon layer 34. In the case of DRAM, the fuse 32 is formed in the gate electrode forming step of the transistor, and the polysilicon film 34 is formed in the bit line, the lower electrode of the capacitor or the upper electrode forming of the capacitor, and the SRAM or flash memory (flash memory) In the device fabrication process, the etch stop layer may be formed of any polysilicon layer deposited between the fuse 12 and the passivation layer 13.
도2b는 상기 보호막(36) 상에 감광막 패턴(40)을 형성하고, 감광막 패턴(40)을 식각마스크로 상기 폴리실리콘막(34)이 노출될 때까지 보호막(36) 및 제2 산화막(35)을 선택적으로 식각한 것을 보이고 있다. 이때, 폴리실리콘막(34)에 대한 제2 산화막(35)의 식각선택비(SA)가 큰 조건으로 식각을 실시하여 제2 산화막(35) 식각시 폴리실리콘막(34)에서 식각이 정지되도록 함으로써 비균일 문제를 해결한다. 또한, 상기 폴리실리콘막(34) 상에 제2 산화막(35)이 남는 것을 방지하기 위하여 과도식각을 실시한다.FIG. 2B shows the photoresist pattern 40 on the passivation layer 36 and the passivation layer 36 and the second oxide layer 35 until the polysilicon layer 34 is exposed using the photoresist layer pattern 40 as an etch mask. ) Is selectively etched. At this time, etching is performed under the condition that the etching selectivity S A of the second oxide layer 35 to the polysilicon layer 34 is large, so that the etching is stopped in the polysilicon layer 34 when the second oxide layer 35 is etched. By doing so, the non-uniform problem is solved. In addition, transient etching is performed to prevent the second oxide layer 35 from remaining on the polysilicon layer 34.
상기 제2 산화막(35) 식각이 완료된 시점에서 실제적으로는 식각선택비(SA)의 한계로 인하여 폴리실리콘막(34)의 손상이 발생하며, 이때 남아있는 폴리실리콘막(34) 두께의 편차(t1)는 폴리실리콘막(34) 상에 남아있는 산화막의 두께(h), 비균일도(U) 및 식각선택비(SA)에 대해 다음의 수학식1과 같은 관계에 있다.When the etching of the second oxide layer 35 is completed, the polysilicon layer 34 may be damaged due to the limitation of the etching selectivity S A , and the thickness of the remaining polysilicon layer 34 may be varied. (t 1 ) has the following relationship with respect to the thickness h, the nonuniformity U, and the etching selectivity S A of the oxide film remaining on the polysilicon film 34 as shown in Equation 1 below.
도2c는 상기 Cl2또는 CF4가스 중 적어도 어느 하나가 포함된 가스의 플라즈마로 폴리실리콘막(34)을 식각하여 제1 산화막(33)을 노출시킨 상태를 보이고 있다. 이때, 폴리실리콘막(34)에 대한 제1 산화막(33)의 식각선택비(SB)가 작은 조건으로 폴리실리콘막(34)을 식각한다. 상기 식각가스로 CF4및 O2의 혼합가스를 사용하기도 한다.FIG. 2C illustrates a state in which the polysilicon layer 34 is etched with a plasma of at least one of the Cl 2 and CF 4 gases to expose the first oxide layer 33. In this case, the polysilicon film 34 is etched under the condition that the etching selectivity S B of the first oxide film 33 with respect to the polysilicon film 34 is small. A mixed gas of CF 4 and O 2 may also be used as the etching gas.
상기 폴리실리콘막(34) 제거된 시점에서 잔류하는 제1 산화막(33) 두께의 편차(t2)는 식각된 폴리실리콘막 두께의 편차(t1) 및 식각선택비(SB)에 대해 다음의 수학식2와 같은 관계에 있다.The deviation t 2 of the thickness of the first oxide layer 33 remaining at the time when the polysilicon layer 34 is removed is next to the deviation t 1 and the etching selectivity S B of the etched polysilicon layer. Is in the same relationship as
도2d는 상기 제1 산화막(34)의 일부를 선택적으로 제거하여 퓨즈(32) 상에 제1 산화막(35)을 500 Å 내지 5000 Å 두께로 잔류시킨 것을 나타내고 있다.2D shows that a portion of the first oxide film 34 is selectively removed to leave the first oxide film 35 on the fuse 32 at a thickness of 500 kV to 5000 kV.
상기 수학식1 및 수학식2로부터 제1 산화막(32) 식각 후 잔류하는 제1 산화막(32) 두께의 편차(t2)는의 값에 비례함을 알 수 있다. 따라서, 폴리실리콘막(34)에 대한 제2 산화막(35)의 식각선택비(SA)는 크게하고, 폴리실리콘막(34)에 대한 제1 산화막(33)의 식각선택비(SB)는 작게한다.From the equations 1 and 2, the deviation t 2 of the thickness of the first oxide film 32 remaining after the first oxide film 32 is etched is It can be seen that it is proportional to the value of. Accordingly, the etching selectivity S A of the second oxide film 35 with respect to the polysilicon film 34 is increased, and the etching selectivity S B of the first oxide film 33 with respect to the polysilicon film 34 is increased. To make it smaller.
상기 폴리실리콘막(34) 제거 단계와 제1 산화막(33) 식각 단계는 폴리실리콘막: 산화막의 식각비를 1:1로하여 연속적으로 실시될 수도 있으며, 상기 모든 식각 공정은 동일 챔버(chamber)에서 진행된다.The removing of the polysilicon layer 34 and the etching of the first oxide layer 33 may be continuously performed by using an etch ratio of polysilicon layer: oxide layer in a ratio of 1: 1, and all the etching processes are performed in the same chamber. Proceeds from.
다음의 표1은 제2 산화막 식각, 폴리실리콘막 식각 및 제1 산화막 식각을 각각 실시할 경우 각 단계에서 산화막과 폴리실리콘막의 상대적인 식각률을 비교하여 나타낸 것이다.Table 1 below shows the relative etch rates of the oxide film and the polysilicon film in each step when the second oxide film etching, the polysilicon film etching, and the first oxide film etching are performed.
다음의 표2는 제2 산화막 식각을 실시하고 폴리실리콘막 및 제1 산화막을 연속적으로 식각할 경우 각 단계에서 산화막과 폴리실리콘막의 상대적인 식각률을 비교하여 나타낸 것이다.Table 2 below shows a comparison of the relative etch rates of the oxide film and the polysilicon film in each step when the second oxide film is etched and the polysilicon film and the first oxide film are continuously etched.
전술한 바와 같이 이루어지는 본 발명은 퓨즈 상의 절연막 사이에 식각정지막을 삽입하여, 식각정지막 상의 절연막 부분은 이후에 퓨즈 상에 잔류하게될 절연막 두께의 편차에 영향을 미치지 않도록 하고, 식각정지막 하부의 절연막을 식각하는 과정만이 절연막 두께의 편차에 영향을 주도록 한다. 즉, 식각정지막을 삽입하여 종래에 한 번에 실시하던 식각 공정을 두 번 이상 실시함으로써 각 식각단계에서 식각대상의 두께를 감소시켜, 절연막의 재증착 정도를 줄이고 식각 불균일에 의해 발생하는 문제를 해결할 수 있어 식각 후 잔류되는 절연막 두께의 편차를 감소시킬 수 있다.According to the present invention made as described above, by inserting an etch stop film between the insulating film on the fuse, so that the portion of the insulating film on the etch stop film does not affect the variation in the thickness of the insulating film to be left on the fuse later, Only the process of etching the insulating film affects the variation of the insulating film thickness. In other words, by inserting the etch stop layer and performing the etching process two or more times in the past, the thickness of the etching target is reduced in each etching step, thereby reducing the degree of redeposition of the insulating film and solving the problem caused by the etching unevenness. This can reduce the variation in the thickness of the insulating film remaining after etching.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 퓨즈 상에 잔류하여 리페어 식각시 식각되는 절연막 두께의 편차를 감소시킴으로써 리페어 수율을 향상시킬 수 있다.According to the present invention as described above, the repair yield can be improved by reducing the variation in the thickness of the insulating layer remaining on the fuse during the etching of the repair.
Claims (11)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024426A KR100303317B1 (en) | 1998-06-26 | 1998-06-26 | Method for forming fuse box of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024426A KR100303317B1 (en) | 1998-06-26 | 1998-06-26 | Method for forming fuse box of semiconductor device |
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| KR20000003231A KR20000003231A (en) | 2000-01-15 |
| KR100303317B1 true KR100303317B1 (en) | 2001-10-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100542943B1 (en) * | 1998-12-30 | 2006-05-09 | 주식회사 하이닉스반도체 | Repair etching method of semiconductor device |
| KR100702314B1 (en) * | 2005-06-27 | 2007-03-30 | 주식회사 하이닉스반도체 | Manufacturing method of fuse box |
| KR100800937B1 (en) * | 2006-09-11 | 2008-02-04 | 동부일렉트로닉스 주식회사 | Method for controlling thickness of fuse oxide layer in a semiconductor devices |
| KR20090070826A (en) | 2007-12-27 | 2009-07-01 | 주식회사 하이닉스반도체 | Semiconductor device with fuse and method for manufacturing the same |
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