KR20010038436A - Method for opening bit line fuse - Google Patents

Abstract

PURPOSE: A method for opening a bit line fuse is provided to leave an insulating layer of a desired thickness on the bit line fuse, by depositing an etch stop layer after an interlayer dielectric of a predetermined thickness is deposited on the bit line fuse, and by etching insulating layers deposited in a subsequent process. CONSTITUTION: A bit line fuse(210b) is formed on a semiconductor substrate. An insulating layer(212) of a predetermined thickness is formed on the bit line fuse. An etch stop layer(222) is deposited on the insulating layer. A multilayered insulating layer is deposited on the etch stop layer. The multilayered insulating layer is etched by a photolithography until the etch stop layer on the bit line fuse is exposed.

Description

How to open a bit line fuse {METHOD FOR OPENING BIT LINE FUSE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a bit line fuse open method.

As semiconductor memory devices become more integrated and higher in capacities, the area of cells and the size of components constituting cells become smaller. Accordingly, process conditions are becoming more stringent to prevent the occurrence of defects. However, even though the process conditions are becoming more stringent as the patterns in the cells become finer, it is difficult to prevent a fail cell. Some defective cells generated in the semiconductor memory chip may make the whole chip unusable. This lowers product yields and raises product prices. Since it is difficult to manufacture chips without completely defective cells, there is a need for a technology capable of coping with defective cells. This technique is called a redundancy technique.

If redundancy technology is used in memory semiconductors, it creates extra cells in addition to the operation cells of the memory chip. That is, redundancy cells are formed around the main cell region. Since all cells are connected by bit line fuses, when a bad cell occurs, the bit line fuses are cut to replace an address with a redundancy cell. In this way, defective chips can be repaired, product yields can be improved, and product costs can be reduced.

In the bit line forming step, a bit line fuse is formed. Therefore, various insulating films are deposited on the bit line fuse by a subsequent process. A laser is used to cut the bit line fuse. If the thickness of the insulating layer on the bit line fuse is too thick, the bit line fuse cannot be cut. In addition, if the thickness of the insulating film on the bit line fuse is too thin, the adjacent bit line fuse may be cut. Therefore, the insulating films thickly deposited on the bit line fuses must be etched so that the thickness of the insulating films on the bit line fuses is a predetermined thickness.

1 is a cross-sectional view illustrating a problem of a conventional bit line fuse open method.

Referring to FIG. 1, a bit line fuse 110 is formed in a first BPSG film (Boron Phosphorus Silicate Glass layer) 112. A second BPSG film 114 is deposited on the first BPSG film 112. A first TEOS layer (Tetra Ethyl Ortho Silicate layer) 116, a Fox layer (flowable oxide layer) 118, a second TEOS layer 120, and a PE-oxidized layer are formed on the second BPSG layer 114. An oxide layer 122 and a silicon nitride film 124 are sequentially deposited. These insulating films are formed by simultaneously depositing a bit line in the cell region and interlayer insulating films deposited after capacitor formation. As such, various types of films are thickly deposited on the bit line fuse 110.

An insulating film thickness suitable for bit line fuse cutting is about 3000 [mu] s. Therefore, the insulating film on the bit line fuse 110 must be etched to a predetermined thickness. If the thickness of the insulating film on the bit line fuse 110 is too thin, the fuse may be cut to an adjacent fuse when the fuse is cut. If the thickness is too thick, the fuse may not be cut. However, since the insulating films on the bit line fuse 110 are many and thick, it is difficult to etch to a desired thickness.

The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a bit line fuse opening method for etching an insulating film on a bit line fuse to a predetermined thickness so as to easily cut a bit line fuse.

1 is a cross-sectional view showing a problem when a conventional bit line fuse is opened;

2A and 2B are cross-sectional views illustrating a film quality deposited on a cell region and a bit line fuse region after capacitor formation according to an embodiment of the present invention; And

3A and 3B are cross-sectional views showing bit line fuse regions in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

210a: bit line 210b: bit line fuse

212: first BPSG film 214: contact plug

216: capacitor lower electrode 218: dielectric film

220: capacitor upper electrode 222: etch stop film

224: second BPSG film 226: first TEOS film

228: Fox 230: the second TEOS film

232: PE-oxide film 234: silicon nitride film

236 photoresist film 238 fuse box

According to the present invention for achieving the above object, the bit line fuse opening method forms a bit line fuse on a semiconductor substrate. An insulating film having a predetermined thickness is deposited on the bit line fuse. An etch stop layer is deposited on the insulating layer. A multilayer insulating film is deposited on the etch stop film. The multilayer insulating layer is etched until the etch stop layer on the bit line fuse is exposed through a photographic process.

In example embodiments, the method may further include removing an etch stop layer after etching the multilayer insulating layer.

In a preferred embodiment, the thickness of the insulating film deposited on the bit line fuses ranges from about 2000 to 3000 microns.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

In the novel bit line fuse open method of the present invention, an interlayer insulating film is deposited on a bit line fuse to a predetermined thickness, and a silicon nitride film is deposited to serve as an etch stop film.

2 and 3 are cross-sectional views sequentially illustrating a bit line fuse opening method according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, a cell region a and a bit line fuse region b are defined on a semiconductor substrate. Bit lines 210a and bit line fuses 210b are formed in the cell area a and the bit line fuse area b, respectively. The bit line 210a and the bit line fuse 210b have a structure in which 1000 ns of polysilicon and 1500 ns of tungsten silicide are stacked. A first BPSG film is deposited on the bit line 210a and the bit line fuse 210b. Next, the contact plug 214, the lower electrode 216 of the capacitor, the dielectric layer 218, and the upper electrode 220 of the capacitor are sequentially formed in the cell region a. The polysilicon for the lower electrode and the upper electrode is also deposited on the bit line fuse region b, but is patterned and removed.

Referring to FIG. 2B, an etch stop layer 222 is deposited on the entire surface of the semiconductor substrate. The etch stop layer 222 is a silicon nitride layer and is formed in a thickness range of 30 to 1000 μm. On the etch stop layer, a second BPSG film (Boron Phosphorus Silicate Glass layer) 224, a first TEOS film (Tetra Ethyl Ortho Silicate layer) 226, a Fox film (flowable oxide layer) 228, and a second TEOS A film 230, a PE-Plasma Enhanced oxide layer 232, and a silicon nitride film 234 are sequentially deposited.

Referring to FIG. 3A, the bit line fuse region b of FIG. 2 is shown. A photoresist film 236 is deposited on the silicon nitride film 234. The photoresist film 236 is patterned through a photolithography process.

Referring to FIG. 3B, the silicon nitride layer 234, the PE-oxide layer 232, and the second TEOS layer 230 are used until the etch stop layer 222 is exposed by using the photoresist pattern 236 as a mask. ), The Fox film 228, the first TEOS film 226, and the second BPSG film 224 are sequentially etched. As a result, the insulating layers on the bit line fuse 210b are etched to leave an insulating layer having a predetermined thickness. The etch stop layer 222 may not be etched according to a process, and subsequent processes may be performed.

According to the present invention, since an etch stop layer is deposited after depositing an interlayer insulating layer having a predetermined thickness on the bit line fuse, an insulating layer having a desired thickness may be left on the bit line fuse by etching subsequently deposited insulating layers.

Claims (3)

Forming a bit line fuse 210b on the semiconductor substrate; Depositing an insulating film 212 having a predetermined thickness on the bit line fuse 210b; Depositing an etch stop film (222) on the insulating film (212); Depositing a multilayer insulating film on the etch stop film (222); And And etching the multilayer insulating film until the etch stop layer (222) on the bit line fuse (210b) is exposed through a photolithography process. The method of claim 1, The etch stop layer 222 is a silicon nitride layer bit line fuse open method. The method of claim 1, And a thickness of the insulating film 212 on the bit line fuse 210b is about 3000 kW.