KR20080000845A - Method for manufacturing of semiconductor device - Google Patents

Abstract

A method of fabricating a semiconductor device is provided to prevent fuse fail by forming an etching stop layer on a dielectric layer formed on an upper portion of a metal fuse. A metal fuse and a first wire are formed on a semiconductor substrate. A first interlayer dielectric, an etching stop layer(135), a second interlayer dielectric(121) and a third interlayer dielectric layer(127) are sequentially formed on the metal fuse and the first metallization, and then are etched to form a contact plug for second wire. A second metallization(143) which is connected to the contact plug is formed on the third interlayer dielectric layer, and then a passivation(145) is formed on the second metallization. A fuse open region(147) for exposing the first interlayer dielectric is formed, and a pad open region(149) for exposing the second metallization is formed.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing a failure caused during laser blowing by making the thickness of the remaining insulating film on the upper part of the fuse uniform during metal fuse manufacturing. to be.

In order to prevent the storage node from falling due to the high integration of semiconductor devices, an insulating film outside the storage node is used as a capacitor in order to prevent the storage node from falling. Currently, the insulating film outside the storage node is removed by a cleaning process. A method of increasing cell capacitance by using both the outside and the inside of a node as a capacitor is used.

In this method, when the plate electrode layer is used as a fuse, all the insulating films under the fuse are also removed in the cleaning process to remove the insulating film outside the storage node, so that the fuse is the same as the step of the bit line. The use of is required. Metal fuses are also required in the triple level metal (TLM) process, which uses a third metal wiring to increase the operation speed, and is considered to be mainstream in the future fuse structure.

However, the metal fuse has a smaller step difference between the fuse part and the pad part than the conventional plate fuse, and thus the thickness of the remaining insulating layer on the upper part of the fuse cannot be easily adjusted after the deposition of the protective film, which causes a margin during laser blowing. This decreases, causing the device to fail.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a metal fuse 31a and a first metal wiring 31b are formed on an upper surface of a semiconductor substrate 11 defined by a fuse region and a pad region and on which a predetermined lower structure is formed.

The lower structure may include a device isolation layer 13, a gate 15, a first interlayer insulating layer 17, a bit line contact plug (not shown), a bit line 19, a second interlayer insulating layer 21, and a storage electrode contact. And a plug (not shown), a storage electrode 23, a plate electrode layer 25, a third interlayer insulating layer 27, and a first metal wiring contact plug 29.

Referring to FIG. 1B, a fourth interlayer insulating film 33, a fifth interlayer insulating film 35, and a sixth interlayer are formed on the metal fuse 31a and the first metal wiring 31b as a metal interlayer insulating layer IMD. The insulating film 37 is formed sequentially.

In this case, the fourth interlayer insulating film 33 is formed of a TEOS film having a thickness of 1000 to 2000 Å, and the fifth interlayer insulating film 35 is formed by performing a curing process after depositing an HSQ film. The sixth interlayer insulating film 37 is formed of a TEOS film.

Referring to FIG. 1C, the sixth interlayer insulating layer 39, the fifth interlayer insulating layer 37, and the fourth interlayer insulating layer 35 are etched by a photolithography process using a second metal wiring contact mask. A hole (not shown) is formed.

Next, a barrier metal (not shown) is deposited along the surfaces of the second metal interconnection contact hole and the sixth interlayer insulating layer 39 and a planarization process is performed so that only the inner surface of the second metal interconnection contact hole is formed on the barrier metal. Let this remain.

In this case, the barrier metal is formed in a stacked structure of a Ti film and a TiN film.

Next, a tungsten (W) film is buried in the second metal wiring contact hole to form a second metal wiring contact plug 39.

Next, a second metal wiring 41 is formed on the sixth interlayer insulating film 39.

In this case, the second metal wiring 41 is formed in a stacked structure of an aluminum (Al) film, a titanium (Ti) film, and a titanium nitride (TiN) film.

Referring to FIG. 1D, a passivation layer 43 is formed on the second metal wire 41.

Referring to FIG. 1E, the passivation layer 43, the sixth interlayer insulating layer 39, and the fifth interlayer insulating layer 37 so that the fourth interlayer insulating layer 35 remains on the metal fuse 31a by a predetermined thickness. And the fourth interlayer insulating layer 35 are etched to form a fuse open region 45, and at the same time, the protective layer 43 is etched until the titanium nitride (TiN) layer of the second metal wiring 41 is removed. The pad open area 47 is formed.

In the above-described method of manufacturing a semiconductor device according to the related art, the thickness of the fourth interlayer insulating layer 35 to be left on the metal fuse 31a cannot be controlled, and is etched unevenly, thereby causing a laser blowing process. There is a problem that the yield (yeild) is reduced due to lack of time margin. In order to solve such a problem, a method of forming the fuse open region 45 and the pad open region 47 by performing two etching processes without forming them simultaneously is used. have.

The present invention was created to solve the above problems, and by forming an etch stop film on the insulating film on the upper portion of the metal fuse, even if the fuse open area and the pad open area are formed at the same time, the thickness of the insulating film remaining on the metal fuse is easily maintained. Its purpose is to provide a method of manufacturing a semiconductor device that can be adjusted.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a metal fuse and a first metal wiring on a semiconductor substrate defined by a fuse region and a pad region and provided with a predetermined lower structure; Sequentially forming a first interlayer insulating film, an etch stop film, a second interlayer insulating film, and a third interlayer insulating film on the metal fuse and the first metal wiring; Etching the third interlayer insulating film, the second interlayer insulating film, the etch stop film, and the first interlayer insulating film to form a contact plug for the second metal wiring; Forming a second metal wire on the third interlayer insulating layer, the second metal wire being connected to the second metal wire contact plug; Forming a protective film on the second metal wire; And forming a fuse open region exposing the first interlayer insulating layer by a photolithography process using a mask defining a fuse open region and a pad open region, and simultaneously forming a pad open region exposing the second metal wiring. It is characterized by.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, a metal fuse 131a and a first metal wiring 131b are formed on a semiconductor substrate 111 defined by a fuse region and a pad region and on which a predetermined lower structure is formed.

The lower structure may include a device isolation layer 113, a gate 115, a first interlayer insulating layer 117, a bit line contact plug (not shown), a bit line 119, a second interlayer insulating layer 121, and a storage electrode contact. It is preferable to include a plug (not shown), a storage electrode 123, a plate electrode layer 125, a third interlayer insulating layer 127, and a first metal wiring contact plug 129.

Referring to FIG. 2B, a fourth interlayer insulating layer 133 as a metal interlayer insulating layer IMD is formed on the metal fuse 131a and the first metal wiring 131b.

In this case, it is preferable that the fourth interlayer insulating film 133 is formed of a TEOS film having a thickness of 1000 to 2000 Å.

Next, an etch stop layer 135 is formed on the fourth interlayer insulating layer 133, and a fifth interlayer insulating layer 137 and a sixth interlayer insulating layer 139 are sequentially formed on the etch stop layer 135. Form.

In this case, the etch stop layer 135 is formed of an amorphous carbon (armophous-Carbon) layer, and then formed to a thickness of 100 ~ 500Å to remain until the aluminum surface of the second metal wiring is exposed during the pad opening process It is preferable.

The fifth interlayer insulating layer 137 may be formed by depositing an HSQ film and then performing a curing process, and reducing the fifth interlayer insulating layer 137 by the thickness of the etch stop layer 135 as compared with the related art.

The sixth interlayer insulating film 139 is preferably formed of a TEOS film.

Referring to FIG. 2C, the sixth interlayer insulating layer 139, the fifth interlayer insulating layer 137, the etch stop layer 135, and the fourth interlayer insulating layer 133 are formed by a photolithography process using a second metal wiring contact mask. Etching to form a second metal wiring contact hole (not shown).

Subsequently, a barrier metal (not shown) is deposited along the surfaces of the second metal wiring contact hole and the sixth interlayer insulating layer 139 and a planarization process is performed so that only the inner surface of the second metal wiring contact hole is formed on the barrier metal. Let this remain.

In this case, the barrier metal is preferably formed in a stacked structure of a Ti film and a TiN film.

Next, a tungsten (W) film is embedded in the second contact hole for metal wiring to form a second contact plug 141 for wiring.

Next, a second metal wiring 143 is formed on the sixth interlayer insulating layer 139.

In this case, the second metal wiring 143 may be formed in a stacked structure of an aluminum (Al) film, a titanium (Ti) film, and a titanium nitride (TiN) film.

Referring to FIG. 2D, a passivation layer 145 is formed on the second metal wire 143.

Referring to FIG. 2E, a photoresist layer (not shown) is formed on the passivation layer 145, and the photoresist layer is exposed and developed with a mask defining a fuse open area and a pad open area to form a photoresist pattern (not shown). .

Subsequently, the protective layer 145, the sixth interlayer insulating layer 143, and the fifth interlayer insulating layer 141 are etched until the etch stop layer 139 is exposed using the photoresist pattern as a mask. ) And at the same time, the passivation layer 145 is etched to form the pad open region 149 until the titanium nitride (TiN) layer of the second metal wiring 143 is removed.

Then, the photoresist pattern is removed. In this case, the amorphous carbon layer 139 for the etch stop layer is also removed, so that an additional removal process is unnecessary, and the etching is performed even if an excessive etching process is performed to remove the titanium nitride (TiN) layer of the second metal wire 143. The fourth interlayer insulating layer 135 may not be lost by the amorphous carbon layer 139 for the stop layer, and thus the fourth interlayer insulating layer 135 may be left on the metal fuse 131a by a predetermined thickness.

As described above, in the method of manufacturing a semiconductor device according to the present invention, an etch stop layer is formed on the insulating film on the upper portion of the metal fuse, so that even when the fuse open region and the pad open region are simultaneously formed, the semiconductor device is not damaged by the insulating film remaining on the metal fuse. Since it can be left as thick as possible, the margin is secured during the laser blowing process, thereby preventing the fuse from failing and improving the yield.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

Forming a metal fuse and a first metal wiring on the semiconductor substrate defined by the fuse region and the pad region and provided with a predetermined lower structure; Sequentially forming a first interlayer insulating film, an etch stop film, a second interlayer insulating film, and a third interlayer insulating film on the metal fuse and the first metal wiring; Etching the third interlayer insulating film, the second interlayer insulating film, the etch stop film and the first interlayer insulating film to form a second metal wiring contact plug; Forming a second metal wiring on the third interlayer insulating layer, the second metal wiring being connected to the second metal wiring contact plug; Forming a protective film on the second metal wiring; And A photolithography process using a mask defining a fuse open area and a pad open area to form a fuse open area that exposes the first interlayer insulating layer and simultaneously form a pad open area that exposes the second metal wiring. Method of manufacturing a semiconductor device comprising a. The method of manufacturing a semiconductor device according to claim 1, wherein the first interlayer insulating film is formed of a TEOS film having a thickness of 1000 to 2000 GPa. The method of claim 1, wherein the etch stop layer is formed of an amorphous carbon (armophous-Carbon) layer. The method of claim 1, wherein the etch stop layer is formed to a thickness of 100 to 500 kV. The method of claim 1, wherein the second interlayer insulating film is formed by depositing an HSQ film and performing a curing process. The method of claim 1, wherein the forming of the second metal wire contact plug is performed. Etching the third interlayer insulating film, the second interlayer insulating film, the etch stop film, and the first interlayer insulating film by a photolithography process using a second metal wiring contact mask to form a second metal wiring contact hole; Depositing a barrier metal along surfaces of the second metal interconnection contact hole and the third interlayer insulating layer and performing a planarization process to leave the barrier metal only on an inner surface of the second metal interconnection contact hole; And Forming a second contact plug for metal wiring by embedding a tungsten (W) film in the second contact hole for metal wiring; Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the forming of the fuse and the pad open area comprises: Forming a photoresist film on the passivation layer; Forming a photoresist pattern by exposing and developing the photoresist with a mask defining the fuse open region and the pad open region; By using the photoresist pattern as a mask, the protective layer, the third interlayer insulating layer, the second interlayer insulating layer and the first interlayer insulating layer are etched to form the fuse open region until the etch stop layer is exposed, and simultaneously the second metal is formed. Etching the passivation layer until the wiring is exposed to form the pad open region; And Removing the photoresist pattern Method of manufacturing a semiconductor device comprising a. The method of claim 7, wherein the etch stop layer is also removed when the photoresist pattern is removed.

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