KR100399062B1 - Fuse structure in semiconductor device and method of fabricating the same - Google Patents
Fuse structure in semiconductor device and method of fabricating the same Download PDFInfo
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- KR100399062B1 KR100399062B1 KR10-2001-0038864A KR20010038864A KR100399062B1 KR 100399062 B1 KR100399062 B1 KR 100399062B1 KR 20010038864 A KR20010038864 A KR 20010038864A KR 100399062 B1 KR100399062 B1 KR 100399062B1
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- polysilicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims abstract description 50
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 238000002844 melting Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 239000002356 single layer Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 21
- 230000008439 repair process Effects 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910003071 TaON Inorganic materials 0.000 description 1
- 239000003518 caustics Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
본 발명은 커패시터 하부전극 형성을 위한 고융점금속 질화막으로 이루어진 하부 퓨즈층과, 커패시터 상부전극 형성을 위한 폴리실리콘으로 이루어진 상부 퓨즈층의 이중 구조로 된 반도체소자의 퓨즈구조에 있어서, 퓨즈 리페어영역에 해당되는 퓨즈 부분이 상기 하부 퓨즈층은 배제하고 폴리실리콘으로 이루어진 상부 퓨즈층의 단일층으로만 구성된 반도체소자의 퓨즈구조를 제공한다. 본 발명에 의하면, 기존의 TiN/폴리실리콘으로 구성된 퓨즈구조에서 발생할 수 있는 신뢰성 저하 문제를 해결하여 신뢰성이 우수한 0.13㎛급 DRAM소자를 제품화할 수 있다.In the fuse structure of a semiconductor device having a double structure of a lower fuse layer made of a high melting point metal nitride film for forming a capacitor lower electrode, and an upper fuse layer made of polysilicon for forming a capacitor upper electrode, A corresponding fuse portion excludes the lower fuse layer and provides a fuse structure of a semiconductor device composed of only a single layer of an upper fuse layer made of polysilicon. According to the present invention, it is possible to commercialize a 0.13㎛ class DRAM device having excellent reliability by solving a problem of deterioration that may occur in a fuse structure composed of conventional TiN / polysilicon.
Description
본 발명은 DRAM소자의 퓨즈구조 및 그 제조방법에 관한 것으로, 특히 고집적 DRAM소자 제조공정중 인라인(In-line) 제조후 전기적 제품검사후에 발견되는 단위셀 불량에 의한 제품의 리페어(repair)시에 사용되는 퓨즈를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse structure of a DRAM device and a method of manufacturing the same. In particular, in the case of repairing a product due to a defective unit cell found after an electrical product inspection after an in-line manufacturing process in a highly integrated DRAM device manufacturing process. A method of forming a fuse to be used.
반도체 메모리소자의 경우, 일부 불량 셀의 발생시 이를 리페어하기 위한 퓨즈를 각 셀마다 예비로 준비하여 리페어를 진행하게 된다.In the case of a semiconductor memory device, when a defective cell occurs, a fuse for repairing the defective cell is prepared in advance for each cell, and the repair is performed.
종래 기술에 의해 형성된 반도체장치의 퓨즈구조를 도1a와 도1b에 평면도와 단면도로 각각 나타내었다.The fuse structure of the semiconductor device formed by the prior art is shown in FIGS. 1A and 1B in plan and cross-sectional views, respectively.
도1a에 나타낸 바와 같이 종래기술에 의한 리페어를 위한 퓨즈패턴(a1)은 그 폭이 1-3㎛이며 간격은 1-5㎛정도이다. 참조부호 a2는 리페어를 위하여 패시베이션층이 제거된 영역을 나타낸다.As shown in Fig. 1A, the fuse pattern a1 for the repair according to the prior art has a width of 1-3 m and an interval of about 1-5 m. Reference numeral a2 denotes a region in which the passivation layer has been removed for repair.
도1b를 참조하면, 참조부호 b3과 b4는 각각 퓨즈를 구성하는 하부전극과 상부전극이다. 일반적으로 하부전극(b3)은 TiN으로 형성하고고, 상부전극(b4)은 폴리실리콘으로 형성한다. b1은 실리콘기판을 포함하는 퓨즈 하부영역이고, b2는 퓨즈와 접촉하고 있는 실리콘산화막이다. 또한, b5는 퓨즈패턴상에 형성된 다층 또는 단층의 절연막이고, b6은 퓨즈영역의 층간절연막을 보호하기 위한 금속 가드링(guard ring)을 나타낸다. 이 가드링은 일반적으로 하부 금속배선층과 상부금속배선층 및 이 두 배선층간의 콘택으로 구성된다.Referring to FIG. 1B, reference numerals b3 and b4 denote lower and upper electrodes constituting a fuse, respectively. In general, the lower electrode b3 is formed of TiN, and the upper electrode b4 is formed of polysilicon. b1 is a fuse lower region including a silicon substrate, and b2 is a silicon oxide film in contact with the fuse. Further, b5 is a multilayer or single layer insulating film formed on the fuse pattern, and b6 represents a metal guard ring for protecting the interlayer insulating film of the fuse region. The guard ring is generally composed of a lower metal wiring layer and an upper metal wiring layer and a contact between the two wiring layers.
b7은 반도체 칩 제조시 금속배선간의 절연을 위한 층간절연막으로 단층 또는 다층으로 구성된다. b8은 칩 제조시 최종 금속배선 및 칩 보호를 위한 패시베이션층이며, b9는 칩 보호를 위한 PIQ층이다. b10은 리페어시 사용하기 위하여 적정량의 산화막이 퓨즈위에 잔류되도록 패턴을 형성한 퓨즈 리페어영역을 나타낸다.b7 is an interlayer insulating film for insulating between metal wirings in the manufacture of semiconductor chips. b8 is a passivation layer for final metallization and chip protection during chip manufacturing, and b9 is a PIQ layer for chip protection. b10 denotes a fuse repair region in which a pattern is formed such that an appropriate amount of oxide film remains on the fuse for use in repair.
도2는 상기 퓨즈의 단면상에서 보이는 전형적인 형태를 나타낸 것으로, c1은 패시베이션층위에 적용된 PIQ물질을 나타내며, c2는 리페어를 위해 노출된 퓨즈영역, c3은 패시베이션층위에 PIQ물질이 없는 영역을 나타낸다. 그리고 c4는 퓨즈로서 사용되는 패턴을 나타낸다.Figure 2 shows a typical shape seen on the cross section of the fuse, c1 represents the PIQ material applied on the passivation layer, c2 represents an exposed fuse area for the repair, c3 represents a region without PIQ material on the passivation layer. And c4 represents a pattern used as a fuse.
상술한 종래의 기술은 소자의 미세화에 따라 고유전율의 커패시터 유전막, TaON, Ta2O5 등을 사용하면서 상부전극과 하부전극을 제한적으로만 적용하게 되며, 또한 이 전극을 퓨즈층으로 적용함에 따라 도3에 나타낸 바와 같이 불량 셀에 의한 리페어 공정을 진행한 뒤 블로우업(blow-up)된 퓨즈 부근의 취약한 영역(A)을 통하여 외부의 습기 및 기타 부식성 물질이 인입되어 점진적으로 퓨즈층 중 하부전극(b3) 영역이 부식되면서 셀영역 또는 그 부근의 트랜지스터가 열화되는 형태의 신뢰성 문제를 야기하게 된다.In the above-described conventional technique, the upper electrode and the lower electrode are limitedly applied using a high dielectric constant capacitor dielectric film, TaON, Ta2O5, etc. as the device becomes smaller, and the electrode is used as a fuse layer in FIG. 3. As shown in the figure, after the repair process by the defective cell, external moisture and other corrosive substances are introduced through the weak area A near the blown-up fuse, thereby gradually lowering the lower electrode b3. Corrosion) causes corrosion problems in the form of deterioration of transistors in or near the cell region.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 반도체 메모리장치에 있어서 커패시터용 전극으로서는 본래의 구성(TiN/폴리실리콘)을 유지하면서 향후 제품 평가 및 전기적 평가후 블로우업하게 될 퓨즈층내의 취약부분에서 신뢰성이 취약한 TiN층을 배제한 안정된 퓨즈구조 및 그 제조방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the semiconductor memory device, while maintaining the original configuration (TiN / polysilicon) as a capacitor electrode, in the weak part of the fuse layer which will blow up after the future product evaluation and electrical evaluation. An object of the present invention is to provide a stable fuse structure and a method of manufacturing the same, excluding a TiN layer having poor reliability.
도1a 및 도1b는 종래기술에 의한 반도체 메모리소자의 퓨즈구조를 나타낸 평면도 및 단면도,1A and 1B are a plan view and a cross-sectional view showing a fuse structure of a semiconductor memory device according to the prior art;
도2는 퓨즈의 단면상에서 보이는 전형적인 형태를 나타낸 도면,2 shows a typical configuration seen in cross section of a fuse;
도3은 종래의 퓨즈구조에 있어서의 퓨즈의 부식 발생경로를 나타낸 도면,3 is a view showing a corrosion occurrence path of a fuse in a conventional fuse structure;
도4는 본 발명에 의한 퓨즈구조를 나타낸 단면도.4 is a cross-sectional view showing a fuse structure according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
a1 : 퓨즈패턴 a2 : 리페어 영역a1: fuse pattern a2: repair area
b1,1 : 퓨즈 하부영역 b2,2 : 산화막b1,1: fuse lower region b2,2: oxide film
b3,3 : 하부 퓨즈층 b4,4 : 상부 퓨즈층b3,3: lower fuse layer b4,4: upper fuse layer
b5,5 : 절연막 b6,6 : 금속 가드링b5,5: insulating film b6,6: metal guard ring
b7,7 : 층간절연막 b8,8 : 패시베이션막b7,7: interlayer insulating film b8,8: passivation film
b9,9 : PIQ층 b10,10 : 퓨즈 리페어영역b9,9: PIQ layer b10,10: fuse repair area
상기 목적을 달성하기 위한 본 발명의 반도체소자의 퓨즈구조는 커패시터 하부전극 형성을 위한 고융점금속 질화막으로 이루어진 하부 퓨즈층과, 커패시터 상부전극 형성을 위한 폴리실리콘으로 이루어진 상부 퓨즈층의 이중 구조로 된 반도체소자의 퓨즈구조에 있어서, 퓨즈 리페어영역에 해당되는 퓨즈 부분이 상기 하부 퓨즈층은 배제하고 폴리실리콘으로 이루어진 상부 퓨즈층의 단일층으로만 구성된 것을 특징으로 한다.The fuse structure of the semiconductor device of the present invention for achieving the above object is a double structure of the lower fuse layer made of a high melting point metal nitride film for forming the capacitor lower electrode, and the upper fuse layer made of polysilicon for forming the capacitor upper electrode In the fuse structure of the semiconductor device, the fuse portion corresponding to the fuse repair region is formed of only a single layer of the upper fuse layer made of polysilicon without the lower fuse layer.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 퓨즈 제조방법은 반도체기판상에 커패시터 하부전극 형성을 위하여 고융점금속 질화막을 증착하는 단계와; 상기 고융점금속 질화막을 사진식각공정을 통해 소정의 커패시터 하부전극패턴과 퓨즈패턴으로 패터닝하되, 퓨즈 리페어영역과 기타 외부 노출이 우려되는 영역상의 상기 고융점금속 질화막은 배제시키면서 패터닝을 행하는 단계; 커패시터 유전체막을 형성하는 단계; 커패시터 상부전극 형성을 위해 폴리실리콘을 증착하는 단계; 및 상기 폴리실리콘층을 사진식각공정을 통해 소정의 커패시터 상부전극패턴과 퓨즈 패턴으로 패터닝하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The fuse manufacturing method of the semiconductor device of the present invention for achieving the above object comprises the steps of depositing a high melting point metal nitride film to form a capacitor lower electrode on the semiconductor substrate; Patterning the high melting point metal nitride layer into a predetermined capacitor lower electrode pattern and a fuse pattern through a photolithography process, and patterning the high melting point metal nitride layer while excluding the high melting point metal nitride layer on a region where the fuse repair region and other external exposures are concerned; Forming a capacitor dielectric film; Depositing polysilicon to form a capacitor upper electrode; And patterning the polysilicon layer into a predetermined capacitor upper electrode pattern and a fuse pattern through a photolithography process.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도4에 본 발명에 의한 반도체 메모리소자의 퓨즈구조를 단면도로 나타내었다.4 is a sectional view showing a fuse structure of the semiconductor memory device according to the present invention.
리페어시 블로우업되는 퓨즈영역에는 통상의 레이저에 의하여 블로우업되는 전도선을 보호하기 위한 산화막이 존재하게 되는데 (통상, 1000-3000Å 두께) 이 부분에 해당하는 퓨즈층이 가장 취약부분이 되게 된다. 따라서 본 발명은 제품 평가 및 전기적 평가후 블로우업하게 될 퓨즈층내의 취약부분을 배제한 퓨즈구조를 제안한다.An oxide film for protecting a conductive line blown up by a conventional laser is present in the fuse area blown up during repair (typically, 1000-3000 mm thick), and the fuse layer corresponding to this part becomes the weakest part. Accordingly, the present invention proposes a fuse structure that excludes a weak part in the fuse layer to be blown up after product evaluation and electrical evaluation.
즉, 도4에 나타낸 바와 같이 반도체 메모리소자의 커패시터 형성을 위한 TiN으로 이루어진 하부전극층(3)과 폴리실리콘으로 이루어진 상부전극층(4)을 이용하여 이중구조를 갖는 퓨즈층을 형성하되, 퓨즈 리페어 영역(10)에 해당되어 블로우업되는 퓨즈층 부분은 커패시터 상부전극층을 형성하는 폴리실리콘(4)으로만 이루어진 단일층으로 구성한다. 상기 폴리실리콘층(4)은 외부 습기나 산화제에 대한 산화특성 및 기타 신뢰성에 문제가 없기 때문에 안정된 퓨즈구조를 확보할 수 있게 된다.That is, as shown in FIG. 4, a fuse layer having a dual structure is formed by using a lower electrode layer 3 made of TiN and an upper electrode layer 4 made of polysilicon for forming a capacitor of a semiconductor memory device. The fuse layer portion blown up corresponding to (10) is composed of a single layer composed of only polysilicon 4 forming a capacitor upper electrode layer. The polysilicon layer 4 has a stable fuse structure because there is no problem in external moisture or oxidation characteristics and other reliability of the oxidizing agent.
상기한 본 발명의 퓨즈구조에 있어서, 퓨즈영역에서의 퓨즈 블로우업을 위하여 오픈되는 영역의 가장자리와 이중구조의 접점까지의 이격거리(도4의 D)는 적어도 3㎛이상이 되도록 하는 것이 바람직하다. 또한, 셀영역 및 기타영역에서 폴리실리콘으로 형성되는 패턴이 최소한 TiN으로 형성된 패턴을 모두 감쌀 수 있도록 적어도 0.1㎛의 오버랩(도4의 L)을 갖도록 하는 것이 바람직하다. 이는 TiN이 외부 산화제 및 습기등에 의해 부식되어 TiNxOy 등으로 열화되면서 발생하는 신뢰성 문제를 최소화하기 위한 것이다. 상기 폴리실리콘과 TiN패턴이 형성되는 최소영역, 상호간의 오버랩 수준 및 금지영역(forbedden gap)은 배선공정 및 신뢰성 수준에 의해 결정한다.In the above-described fuse structure of the present invention, it is preferable that the separation distance (D in FIG. 4) between the edge of the area opened for fuse blow-up in the fuse area and the contact of the double structure is at least 3 μm. . In addition, it is preferable that the pattern formed of polysilicon in the cell region and other regions has an overlap (L in FIG. 4) of at least 0.1 μm so as to cover all of the patterns formed of TiN. This is to minimize the reliability problems caused by TiN deteriorated by TiNxOy due to corrosion by external oxidants and moisture. The minimum area where the polysilicon and the TiN pattern are formed, the overlap level between each other, and the forbidden gap are determined by the wiring process and the reliability level.
상기 이중구조의 퓨즈에 있어서, 하부 전도성 물질로는 상술한 바와 같이 커패시터 하부전극형성용 물질인 TiN이 사용되는바, 그 두께는 100-1000Å이 바람직하며, 상부 전도성 물질인 폴리실리콘은 500-2000Å 두께로 증착하여 형성하는 것이 바람직하다.In the double-structure fuse, as the lower conductive material, TiN, which is a material for forming the lower electrode of the capacitor, is used as described above. The thickness thereof is preferably 100-1000 mW, and the polysilicon is 500-2000 mW. It is preferable to form by depositing in thickness.
상기와 같은 본 발명의 퓨즈구조를 형성하는 공정을 도4를 참조하여 설명하면 다음과 같다.The process of forming the fuse structure of the present invention as described above with reference to Figure 4 as follows.
통상적인 DRAM 제조공정을 통해 커패시터 하부구조를 반도체기판상에 형성한 후, 커패시터 하부전극 형성을 위하여 예컨대 TiN(3)을 기판상에 증착하고 이를 사진식각공정을 통해 소정의 커패시터 하부전극패턴(도시하지 않음)과 퓨즈패턴으로 패터닝한다. 이때, 퓨즈 리페어영역(10)과 기타 외부 노출이 염려되는 영역의 TiN층은 배제시키면서 패터닝을 행한다.After the capacitor substructure is formed on the semiconductor substrate through a conventional DRAM manufacturing process, for example, TiN (3) is deposited on the substrate to form a capacitor lower electrode, and a predetermined capacitor lower electrode pattern is formed through a photolithography process. And the fuse pattern). At this time, patterning is performed while removing the TiN layer in the fuse repair region 10 and other regions where external exposure is concerned.
이어서 커패시터 유전체막(도시하지 않음)을 형성한 후, 커패시터 상부전극 형성을 위해 폴리실리콘(4)을 증착하고 사진식각공정을 통해 소정의 커패시터 상부전극패턴(도시하지 않음)과 퓨즈 패턴(4)으로 패터닝한다.Subsequently, after forming a capacitor dielectric film (not shown), a polysilicon 4 is deposited to form a capacitor upper electrode, and a predetermined capacitor upper electrode pattern (not shown) and fuse pattern 4 are formed through a photolithography process. Pattern with.
상기 퓨즈패턴은 통상의 공정으로 리페어가 가능하도록 형성한다.The fuse pattern is formed to be repairable in a conventional process.
이후, 절연막 형성공정 및 평탄화공정을 진행하여 이후에 형성될 금속배선과의 절연을 확보하며, 이어서 금속공정 및 기타 후속 공정을 진행하여 반도체 메모리장치를 제조한다.Thereafter, an insulating film forming process and a planarization process are performed to ensure insulation from metal wirings to be formed later, and then a metal process and other subsequent processes are performed to manufacture a semiconductor memory device.
도4에 있어서, 참조부호1은 실리콘기판을 포함하는 퓨즈 하부영역을 나타내며, 2는 퓨즈와 접촉하고 있는 실리콘 산화막, 5는 퓨즈 상부에 형성된 절연막, 6은 퓨즈영역의 층간절연막을 보호하기 위한 금속 가드링을 나타낸다. 또한 7은 금속배선간의 절연을 위한 층간절연막, 8은 최종 금속배선 및 칩을 보호하기 위한 패시베이션층, 9는 칩 보호를 위한 PIQ층을 각각 나타낸다.In Fig. 4, reference numeral 1 denotes a lower fuse area including a silicon substrate, 2 is a silicon oxide film in contact with the fuse, 5 is an insulating film formed on the top of the fuse, and 6 is a metal for protecting the interlayer insulating film of the fuse area. Indicates a guard ring. In addition, 7 is an interlayer insulating film for insulating between metal wiring, 8 is a passivation layer for protecting the final metal wiring and the chip, and 9 is a PIQ layer for chip protection.
본 발명은 DRAM소자 뿐만 아니라 셀 어레이를 적용하여 제조되는 메모리 소자의 불량 셀을 리페어하는 퓨즈는 사용하는 모든 반도체소자에 적용할 수 있다. 또한, TiN 뿐만 아니라 고융점금속 질화막(refractory metal nitride)으로 퓨즈 하부구조를 형성하는 경우에도 본 발명을 적용할 수 있다.According to the present invention, a fuse for repairing a defective cell of a memory device manufactured by applying a cell array as well as a DRAM device may be applied to all semiconductor devices used. In addition, the present invention can be applied to a case in which a fuse substructure is formed of not only TiN but also a refractory metal nitride.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 의하면, 기존의 TiN/폴리실리콘으로 구성된 퓨즈구조에서 발생할 수 있는 신뢰성 저하 문제를 해결하여 신뢰성이 우수한 0.13㎛급 DRAM소자를 제품화할 수 있다.According to the present invention, it is possible to commercialize a 0.13㎛ class DRAM device having excellent reliability by solving a problem of deterioration that may occur in a fuse structure composed of conventional TiN / polysilicon.
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| KR100889336B1 (en) | 2002-12-30 | 2009-03-18 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
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| KR100548998B1 (en) * | 2003-09-25 | 2006-02-02 | 삼성전자주식회사 | Semiconductor device having a capacitor and a fuse at the same level and a method of fabricating the same |
| KR100843206B1 (en) * | 2006-10-18 | 2008-07-02 | 삼성전자주식회사 | Semiconductor device able to prevent bridge between fuse pattern and guard ring |
| KR101631452B1 (en) | 2010-06-03 | 2016-06-17 | 삼성전자 주식회사 | Fuse structure, e-fuse comprising the fuse structure and semiconductor device comprising the e-fuse |
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