KR100929289B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, in the case of a semiconductor device using a fuse as a metal layer in order to prevent the fuse oxidized due to the oxidation of the anti-reflection film exposed to the air during the packaging process, the diffuse reflection before the fuse open process The anti-reflective film is not exposed to air by etching the protection film and the fuse to a predetermined depth to prevent oxidation of the fuse, thereby improving repair efficiency and yield.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1A to 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a fuse as a metal layer.

As the integration of semiconductor devices proceeds, the size of the device becomes smaller and the area of the capacitor is also smaller. Here, the capacitor has a structure in which a dielectric film is interposed between the storage electrode and the plate electrode. The capacitance of the capacitor having this structure is proportional to the dielectric constant of the electrode surface and the dielectric film and inversely proportional to the spacing between the electrodes, that is, the thickness of the dielectric film.

Therefore, recent technical developments for increasing capacitance have been inclined to increase electrode surface area or to apply high dielectric constant dielectric films such as tantalum oxynitride (TaON) or tantalum oxide (Ta2O5).

Here, as a method for increasing the electrode surface area, a method of forming the storage electrode into a three-dimensional structure having a cylinder or a pin structure is typical. In addition, a method of forming hemispherical silicon grain (HemiSpherical Silicon Grain) on the surface of the electrode and a method of increasing the height of the capacitor are widely used.

In particular, the method of increasing the height of the capacitor is relatively easy to compensate for the reduced capacitance by increasing the height of the capacitor according to the narrowed capacitor area and is widely applied.

However, when the height of the capacitor is increased, there is a problem in that the fuse is not cut well during the repair process when the gate, bit line, or plate layer of the lower layer is used as the fuse layer. To solve this problem, a metal layer is used as a fuse layer.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a cell region and a fuse region are defined, a first metal wiring 35a and a fuse 35b are formed on a semiconductor substrate 11 having a predetermined substructure, and the first metal wiring is formed. An diffuse reflection prevention film 37 is formed over the 35a and the fuse 35b.

In this case, the lower structure may include a device isolation layer 13, a gate 15, a first interlayer insulating layer 17, a bit line contact plug 19, a bit line 21, a second interlayer insulating layer 23, and a third interlayer. An insulating film 25, a capacitor 27, a plate 29, a third interlayer insulating film 31, and a first contact plug 33 for metal wiring are included.

The anti-reflective film 37 is formed in a stacked structure of a titanium (Ti) film and a titanium nitride film (TiN).

Next, a fourth interlayer insulating film 39 is formed to cover the first metal wiring 35a and the fuse 35b, and the second metal wiring contact is formed by an etching process using a second metal wiring contact mask (not shown). A hole (not shown) is formed.

Then, a conductive material is embedded in the second metal wiring contact hole to form a second contact plug 41 for wiring.

Next, a second metal wiring 43 is formed on the contact plug 41 for the second metal wiring, and a protective film 45 is formed to cover the second metal wiring 43.

Next, a photoresist pattern (not shown) defining a fuse open region is formed on the passivation layer 45, and the passivation layer 45, the second antireflection layer 37 are exposed using the photoresist pattern as a mask. The four interlayer insulating layer 39 is etched to form a fuse open region 47.

Referring to FIG. 1B, a repair process is performed to replace a defective cell, thereby cutting the corresponding fuse 35b with a laser.

However, during the repair process, a portion (A) of the anti-reflective film 37 is exposed to air, and thereafter, an oxidation reaction occurs in a package process, thereby causing a fuse error.

In order to solve this problem, a method of leaving the fourth interlayer insulating film 39 on the fuse 35b with a predetermined thickness is used.

2A through 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art, in which the same reference numerals are used for the same components shown in FIGS. 1A through 2B.

Referring to FIG. 2A, a cell region and a fuse region are defined, a first metal wiring 35a and a fuse 35b are formed on a semiconductor substrate 11 having a predetermined substructure, and the first metal wiring is formed. An diffuse reflection prevention film 37 is formed over the 35a and the fuse 35b.

In this case, the lower structure may include a device isolation layer 13, a gate 15, a first interlayer insulating layer 17, a bit line contact plug 19, a bit line 21, a second interlayer insulating layer 23, and a third interlayer. An insulating film 25, a capacitor 27, a plate 29, a third interlayer insulating film 31, and a first contact plug 33 for metal wiring are included.

The anti-reflective film 37 is formed in a stacked structure of a titanium (Ti) film and a titanium nitride film (TiN).

Next, a fourth interlayer insulating film 39 is formed to cover the first metal wiring 35a and the fuse 35b, and the second metal wiring contact is formed by an etching process using a second metal wiring contact mask (not shown). A hole (not shown) is formed.

Then, a conductive material is embedded in the second metal wiring contact hole to form a second contact plug 41 for wiring.

Next, a second metal wiring 43 is formed on the contact plug 41 for the second metal wiring, and a protective film 45 is formed to cover the second metal wiring 43.

Next, a photoresist pattern (not shown) defining a fuse open region is formed on the passivation layer 45, and the passivation layer 45, the second antireflection layer 37 are exposed using the photoresist pattern as a mask. The four interlayer insulating layer 39 is etched to form a fuse open region 47.

Referring to FIG. 2B, the fuse 35b is cut by a laser by performing a repair process to replace a defective cell.

As described above, even when the fourth interlayer insulating layer 39 having a predetermined thickness is left on the diffuse reflection prevention layer 37 during the fuse open process, a part B of the diffuse reflection prevention layer 37 is exposed.

In the above-described method of manufacturing a semiconductor device according to the related art, during the repair process, the anti-reflective coating film 37 is exposed to air and then an oxidation reaction occurs in a packaging process. cause an error. In order to solve this problem, an insulating film may be formed in the fuse region after the repair process is performed, but this method increases the process step and has difficulty in the process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing an antireflection film and a phenomenon in which a fuse is oxidized during a packaging process when a fuse is used as a metal layer. .

A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of sequentially forming a fuse and the anti-reflection film on the semiconductor substrate of the fuse region; Forming a trench by etching the anti-reflective film and a portion of the fuse by a photolithography process using an exposure mask defining a region in which the fuse is open in a predetermined width; Forming an interlayer insulating film including a second contact plug for metal wiring on the entire surface; Forming a second metal wiring on the interlayer insulating film, and forming a protective film covering the second metal wiring; And forming a fuse open region by etching a portion of the passivation layer and the interlayer insulating layer by a photolithography process using an exposure mask defining a fuse open region.

In addition, the method of manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a first metal wiring conductive film and an antireflection film on a semiconductor substrate in a fuse region; Forming a trench by etching a part of the anti-reflective film and the conductive film for the first metal wiring by a photolithography process using an exposure mask defining an area in which the fuse is open in a predetermined width; Patterning the diffuse reflection prevention film and the first conductive film for metal wiring to form a diffuse reflection prevention film pattern and a fuse; Forming an interlayer insulating film including a second contact plug for metal wiring on the entire surface; Forming a second metal wiring on the interlayer insulating film, and forming a protective film covering the second metal wiring; And forming a fuse open region by etching a portion of the passivation layer and the interlayer insulating layer by a photolithography process using an exposure mask defining a fuse open region.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 3A, a cell region and a fuse region are defined and a first anti-reflective layer 135 and a diffuse reflection prevention layer 137 are formed on a semiconductor substrate 111 having a predetermined lower structure.

The lower structure may include a device isolation layer 113, a gate 115, a first interlayer insulating layer 117, a bit line contact plug 119, a bit line 121, a second interlayer insulating layer 123, and a third interlayer. An insulating film 125, a capacitor 127, a plate 129, a third interlayer insulating film 131, and a first contact plug 133 for metal wiring are included.

In this case, the anti-reflection film 137 is formed of a laminated structure of a titanium (Ti) film and a titanium nitride (TiN) film, the titanium (Ti) film is formed to a thickness of 100 ~ 500Å, the titanium nitride (TiN) film is 100Å It is preferable to form in thickness of -1000 kPa.

Referring to FIG. 3B, the first metal wiring conductive layer 135 and the diffuse reflection prevention layer 137 are patterned to form a first metal interconnect 135a, a fuse 135b, and an antireflection coating pattern 137a.

Referring to FIG. 3C, the diffuse reflection prevention film pattern 137a and the fuse 135b may be etched by a photolithography process using an exposure mask (not shown) that defines a region wider than the fuse open region by the trench 139. To form.

Referring to FIG. 3D, a fourth interlayer insulating layer 141 is formed over the entire surface, and a second metal wiring contact hole (not shown) is formed by a photolithography process using a second metal wiring contact mask (not shown). .

Next, a conductive material is filled in the second metal wiring contact hole to form a second metal wiring contact plug 143.

Next, a second metal wiring 145 is formed on the contact plug 143 for the second metal wiring, and a protective film 147 is formed to cover the second metal wiring 145.

Subsequently, a portion of the passivation layer 147 and the fourth interlayer insulating layer 141 is etched by a photolithography process using an exposure mask (not shown) that defines a fuse open region on the passivation layer 147. And form 149.

In this case, the fuse open region 149 may be formed to have an interval between 1 and 100 nm with an outer side of the trench 139.

Referring to FIG. 3E, a repair process for replacing defective cells is performed to cut the fuse 135b with a laser.

Accordingly, since the diffuse reflection prevention film pattern 137a and the fuse 135b of the fuse region are partially removed during the trench 139 formation process, the diffuse reflection prevention film pattern 137a during the process of forming the fuse open region 149. ) And the fuse 135b are not exposed to air.

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 4A, a cell region and a fuse region are defined, and a first anti-reflective layer 235 and a diffuse reflection prevention layer 237 are formed on a semiconductor substrate 211 having a predetermined lower structure.

The lower structure may include a device isolation layer 213, a gate 215, a first interlayer insulating layer 217, a bit line contact plug 219, a bit line 221, a second interlayer insulating layer 223, and a third interlayer. An insulating film 225, a capacitor 227, a plate 229, a third interlayer insulating film 231, and a first contact plug 233 for metal wiring are included.

In this case, the anti-reflection film 237 is formed of a laminated structure of a titanium (Ti) film and a titanium nitride (TiN) film, the titanium (Ti) film is formed to a thickness of 100 ~ 500Å, the titanium nitride (TiN) film is 100Å It is preferable to form in thickness of -1000 kPa.

Referring to FIG. 4B, the diffuse reflection prevention layer 237 and the first metal wiring conductive layer 235 of the fuse region may be formed by a photolithography process using an exposure mask (not shown) that defines a region wider than the fuse open region. Etch to form the trench 239.

Referring to FIG. 4C, the first metal wiring conductive film 235 and the anti-reflective coating 237 are patterned to form a first metal wiring 235a, a fuse 235b, and an anti-reflective coating pattern 237a.

Referring to FIG. 4D, a fourth interlayer insulating film 241 is formed over the entire surface, and a second metal wiring contact hole (not shown) is formed by a photolithography process using a second metal wiring contact mask (not shown). .

Next, a conductive material is embedded in the second metal wiring contact hole to form a second metal wiring contact plug 243.

Next, a second metal wiring 245 is formed on the second contact plug 243 for the second metal wiring, and a protective film 247 is formed to cover the second metal wiring 245.

Next, a portion of the passivation layer 247 and the fourth interlayer insulating layer 241 is etched by a photolithography process using an exposure mask (not shown) that defines a fuse open region on the passivation layer 247. (249) is formed.

In this case, the fuse open area 249 may be formed to have an interval between 1 and 100 nm with an outer side of the trench 239.

Referring to FIG. 4E, a repair process for replacing a defective cell is performed to cut the fuse 135b with a laser.

As described above, in the method of manufacturing a semiconductor device according to the present invention, when the fuse is used as a metal layer, the antireflection film and the fuse are oxidized in a package process performed after the antireflection film and the fuse are etched to a predetermined depth before the fuse opening process. It can be prevented to provide an effect to improve the repair efficiency and yield (yield).

In addition, the present invention does not need to perform a process for preventing oxidation of the fuse after the repair process, thereby providing an effect of reducing the production cost.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

Sequentially forming a fuse and an anti-reflection film on the semiconductor substrate in the fuse region; Forming a trench by etching the diffuse reflection prevention layer and the fuse by a photolithography process using an exposure mask defining an enlarged area than the fuse open area; Forming an interlayer insulating film including a second contact plug for metal wiring on the entire surface; Forming a second metal interconnection on the interlayer insulating layer and forming a passivation layer covering the second metal interconnection; And Forming a fuse open region by etching the passivation layer and the interlayer insulating layer by a photolithography process using an exposure mask defining a fuse open region. Method of manufacturing a semiconductor device comprising a. The method of manufacturing a semiconductor device according to claim 1, wherein the anti-reflection film is formed in a laminated structure of a titanium (Ti) film and a titanium nitride (TiN) film. The method of claim 2, wherein the titanium (Ti) film is formed to a thickness of 100 kPa to 500 kPa, and the titanium nitride (TiN) film is formed to have a thickness of 100 kPa to 1000 kPa. The method of claim 1, wherein the enlarged region extends from 1 nm to 100 nm from both sides of the fuse open region. Sequentially forming a first conductive film for metal wiring and an antireflection film on the semiconductor substrate in the fuse region; Forming a trench by etching the diffuse reflection prevention layer and the first metal wiring conductive layer by a photolithography process using an exposure mask defining an enlarged area than the fuse open area; Patterning the anti-reflection film and the conductive film for the first metal wiring to form an anti-reflection film pattern and a fuse; Forming an interlayer insulating film including a second contact plug for metal wiring on the entire surface; Forming a second metal interconnection on the interlayer insulating layer and forming a passivation layer covering the second metal interconnection; And Forming a fuse open region by etching the passivation layer and the interlayer insulating layer by a photolithography process using an exposure mask defining a fuse open region. Method of manufacturing a semiconductor device comprising a. The method of manufacturing a semiconductor device according to claim 5, wherein the diffuse reflection prevention film is formed in a laminated structure of a titanium (Ti) film and a titanium nitride (TiN) film. The method of claim 6, wherein the titanium (Ti) film is formed to a thickness of 100 kPa to 500 kPa, and the titanium nitride (TiN) film is formed to a thickness of 100 kPa to 1000 kPa. The method of claim 5, wherein the enlarged region extends from 1 nm to 100 nm from both sides of the fuse open region.

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