KR20070105827A - Method for manufacturing semiconductor device having repair fuse - Google Patents

Abstract

A method for manufacturing a semiconductor device having a repair fuse is provided to shorten a process time and to reduce a manufacturing cost by performing a photo-masking process only once. A repair fuse is formed on a substrate(31). An interlayer dielectric(32) is formed on an entire structure including the repair fuse. A metal line for a pad is formed on the interlayer dielectric. The metal line has a stacked structure of a first metal layer and a second metal layer. A protective layer is formed on the entire structure including the metal line. A mask pattern(40) for a pad open part(41) and a fuse open part(42) is formed. The protective layer and the interlayer dielectric are etched on the second metal layer. The polymer is removed. The second metal layer is etched.

Description

Method for manufacturing a semiconductor device having a repair fuse {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING REPAIR FUSE}

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device having a repair fuse according to the prior art;

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a repair fuse according to a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 substrate 32 first interlayer insulating film

33: first metal wiring 34: second interlayer insulating film

35: Via contact 36: Al

37 TiN 38 oxide film for protective film

39 nitride film for protective film 40 mask pattern (photoresist pattern)

41: pad open part 42: fuse open part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device having a repair fuse.

In the case of a semiconductor device failure, a fuse is used to repair the defective part. The fuse is not formed by an additional process, but a bit line, a word line, or a capacitor is used. It is formed using a conductive layer forming a plate line. Typically, a repair open part having a thin insulating film is formed on the repair fuse.

The semiconductor device also has a pad opening for subsequent wire bonding.

In manufacturing the semiconductor device, the repair open part and the pad open part may be formed together in one mask and etching process or may be formed in separate mask and etching processes, respectively.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device having a repair fuse according to the related art, and show that the repair open part and the pad open part are formed by separate mask and etching processes, respectively.

As shown in FIG. 1A, a first interlayer insulating film 12 is formed on a substrate 11 on which a predetermined structure for implementing a semiconductor device such as a DRAM is formed. The first metal wiring 13a is formed on the first interlayer insulating film 12. The first metal wire 13 is formed of a metal layer such as aluminum (Al). On the other hand, the metal layer used as the first metal wiring 13a is also patterned in the fuse area of the substrate to be formed as a repair fuse 13b.

Next, a second interlayer insulating film 14 is formed on the entire surface including the first metal wiring 13a, and a via contact 15 penetrating a predetermined region of the second interlayer insulating film 14 is formed. Then, a second metal wiring 100 is formed on the second interlayer insulating film 14 to be connected to the via contact 15. In this case, the second metal wiring 100 has a structure in which Al (16) and TiN (17) are stacked. Subsequently, an oxide film 18 and a nitride film 19 are laminated as a passivation layer on the entire structure including the second metal wiring 100.

Next, the fuse open part 20 is formed by a fuse mask and an etching process. At this time, the nitride film 19, the oxide film 18, and the second interlayer insulating film 14 are sequentially etched, and the second interlayer insulating film 14 is a target that leaves a thin thickness (for example, 300 to 500 nm) on the repair fuse 13b. Etching proceeds.

As shown in FIG. 1B, the pad opening portion 21 is formed by a pad mask and an etching process. At this time, the nitride film 19, the oxide film 18, and the TiN 17 are sequentially etched to expose the Al 16.

As described above, in the prior art, as the device is highly integrated, a wiring metal on the plate line is used as a fuse. The fuse open part and the pad open part are formed by separate mask and etching processes, respectively. As such, when the wiring metal layer is used as a fuse, the pad opening part and the fuse opening part have to be formed by a separate mask and etching process, because the lack of an etching target may cause the pad opening part to fail. Because.

Specifically, when a lower lower conductive layer (eg, a bit line conductive layer, a capacitor conductive electrode layer, etc.) under the first metal wiring layer is used as a fuse, the etching thickness of the insulating layer for the fuse opening may be increased. thick. Therefore, since the etching target is sufficient to open the TiN of the pad opening part sufficiently, only one mask can be used. However, when the metal layer for the first metal wiring is used as a fuse, the etching thickness of the insulating layer for the fuse open part is relatively small, and thus the pad open part may fail due to insufficient etching target of TiN. Thus, a conventional mask process is performed.

However, when using two masks as described above, since two photolithography processes have to be performed, the process is complicated, manufacturing costs are increased, and production speed is also reduced.

Such a problem may occur when the pad opening portion is formed in a state where the etching thickness of the insulating layer for the fuse opening portion is relatively thin, even when the first metal wiring metal layer is not used as the fuse.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and even if the etching thickness of the insulating layer for the fuse open portion is small, a semiconductor device fabrication capable of forming the fuse open portion and the pad open portion using a single mask. The purpose is to provide a method.

The semiconductor device manufacturing method of the present invention for achieving the above object,

Forming a repair fuse on the substrate; Forming an interlayer insulating film on the entire structure including the repair fuse; Forming a pad metal wiring on the interlayer insulating film, wherein the metal wiring has a structure in which a first metal layer and a second metal layer are stacked; Forming a protective film on the entire structure including the metal wires; Forming a mask pattern for the pad open portion and the fuse open portion; Etching the passivation layer and the interlayer insulating layer by a process in which a polymer is formed on the second metal layer while the interlayer insulating layer having a predetermined thickness is left on the repair fuse; Removing the polymer; And etching the second metal layer.

Preferably, the mask pattern is a photoresist pattern, and the method may further include stripping and cleaning the photoresist pattern after the etching of the second metal layer. Alternatively, the photoresist pattern may be removed together in the polymer removing step.

Preferably, the interlayer insulating film is an oxide, and the protective film may be a laminate of an oxide and a nitride. In this case, the treatment of etching the protective film and the interlayer insulating film may use a mixed gas of CF ₄ , CHF ₃ , and Ar, and induces the formation of a polymer by reducing the CF ₄ / CHF ₃ ratio to 4 in the mixed gas. can do. In addition, the process of etching the protective film and the interlayer insulating film may use a gas having a high carbon / fluorine ratio (High Carbon / Fluorine Ratio).

Preferably, the second metal layer may be TiN, and the etching thereof may be such that there is no loss of the interlayer insulating film by using a gas containing Cl ₂ . For example, the gas containing Cl ₂ may be Cl ₂ / BCl ₃ or Cl ₂ / Ar mixed gas.

Preferably, the metal wiring is an upper metal wiring, and the repair fuse may be patterned with a metal layer for lower metal wiring.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

(First embodiment)

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, a first interlayer insulating film 32 is formed on a substrate 31 on which a predetermined structure for implementing a semiconductor device such as a DRAM is formed. The first metal wiring 33a is formed on the first interlayer insulating film 32 in the pad region. The first metal wiring 33a is formed of a metal layer such as aluminum (Al), for example. On the other hand, the metal layer used as the first metal wiring 33a is also patterned in the fuse area of the substrate to be formed as a repair fuse 33b.

Next, a second interlayer insulating film 34 is formed on the entire structure including the first metal wiring 33a and the repair fuse 33b, and the via contact penetrating the predetermined region of the second interlayer insulating film 34. 35). An oxide may be used for the second interlayer insulating film 34. Then, a second metal wiring 200 is formed on the second interlayer insulating film 34 so as to be connected to the via contact 35. Here, the second metal wire 200 may have a structure in which Al 36 and TiN 37 are stacked. Subsequently, the oxide film 38 and the nitride film 39 are laminated as a passivation layer on the entire structure including the second metal wiring 200. In addition to the laminated structure of the oxide film / nitride film, the protective film may be a single layer or a multilayer structure of oxide and nitride.

Subsequently, a mask pattern 40 for forming a pad open portion and a fuse open portion is formed on the nitride film 39. The mask pattern 40 may be a photoresist pattern or a sacrificial hard mask pattern, but the photoresist pattern will be described as an example in this embodiment.

As shown in FIG. 2B, the protective layers 39 and 38 and the second interlayer insulating layer 34 are etched using the mask pattern 40 as an etch barrier to form the fuse open part 42 and the pad open part 41. . At this time, the second interlayer insulating film 34 having a predetermined thickness is left on the repair fuse 33b, and etching is performed by a process in which the polymer P is formed on the TiN 37.

Salpimyeon the etching process, specifically, the etching gas may be a mixed gas of CF _4, CHF _3, and Ar. At this time, CF ₄ except Ar in the mixed gas The ratio of and CHF ₃ is smaller than 4, that is, CF ₄ / CHF ₃ <4. This is to prevent a rapid increase in the etching rate of the second interlayer insulating layer 34 by generating a relatively large amount of polymer during the repair etching.

In addition, a gas having a high carbon / flourine ratio may be used instead of the mixed gas of CF ₄ , CHF ₃ , and Ar to induce polymer (P) generation.

Then, as shown in FIG. 2C, the remaining polymer P is removed using O ₂ gas. Then, the TiN 37 is etched by the target on which the Al 36 is exposed. Here, Al 36 exposed to the pad opening 41 is a portion where wires are to be bonded in a package process. The etching of TiN 37 may use a gas containing Cl ₂ , for example, plasma etching of Cl ₂ / BCl ₃ or Cl ₂ / Ar mixed gas. There is almost no loss of the second interlayer insulating film 34 which is an oxide during plasma etching of the gas containing Cl ₂ .

Subsequently, as illustrated in FIG. 2D, the pad open part 41 and the fuse are opened by removing the photoresist pattern by an O ₂ plasma strip process and performing wet cleaning to remove process residues. The formation of the part 42 is completed.

Although not shown in the drawings, a nitride spacer may be formed on side surfaces of the pad opening 41 and the fuse opening 42 to further passivate the spacer. This is to prevent the intake of moisture or impurities to the side wall as much as possible.

Subsequently, the chip protection fix film PIX is formed, and the fix film is densified through a thermal process. Fix film is a film containing carbon (carbon), and serves to protect the chip from X-rays and the like that can be introduced into the external environment.

Meanwhile, in the embodiment of the present invention, after performing the process up to FIG. 2D, the photoresist pattern may be removed together when the polymer P is removed. That is, even if there is no photoresist pattern 40 which is a mask pattern 40 when etching the subsequent TiN 37, the protective films 39 and 38 made of oxide and nitride and the second interlayer insulating film during plasma etching including Cl ₂ are included. This is because there is almost no loss of 34.

In addition, in the present embodiment, the repair fuse 33b is formed as the metal layer for the lower metal wiring in the multi-layer metallization (MLM) structure, but the repair fuse may be used as another conductive layer in addition to the lower metal wiring. For example, in the case of DRAM devices, a conductive layer for bit lines, a conductive layer for electrodes of a capacitor, and the like can be used.

As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, even if there is no margin of the etch target, since the fuse open portion and the pad open portion can be formed through one photo masking operation, the process time can be shortened, thereby reducing the cost.

Claims (15)

Forming a repair fuse on the substrate; Forming an interlayer insulating film on the entire structure including the repair fuse; Forming a pad metal wiring on the interlayer insulating film, wherein the metal wiring has a structure in which a first metal layer and a second metal layer are stacked; Forming a protective film on the entire structure including the metal wires; Forming a mask pattern for the pad open portion and the fuse open portion; Etching the passivation layer and the interlayer insulating layer by a process in which a polymer is formed on the second metal layer while the interlayer insulating layer having a predetermined thickness is left on the repair fuse; Removing the polymer; And Etching the second metal layer Semiconductor device manufacturing method comprising a. The method of claim 1, And the mask pattern is a photoresist pattern. The method of claim 2, And after the etching of the second metal layer, stripping and cleaning the photoresist pattern. The method of claim 2, And removing the photoresist pattern in the polymer removing step. The method according to any one of claims 1 to 4, The interlayer insulating film is an oxide, the protective film is a semiconductor device manufacturing method of the oxide and nitride are laminated. The method of claim 5, The process of etching the protective film and the interlayer insulating film, A method for manufacturing a semiconductor device using a mixed gas of CF ₄ , CHF ₃ , and Ar. The method of claim 6, The method of manufacturing a semiconductor device for reducing the CF ₄ / CHF ₃ ratio to less than 4. The method of claim 5, The process of etching the protective film and the interlayer insulating film, A method of manufacturing a semiconductor device using a gas having a high carbon / fluorine ratio (High Carbon / Fluorine Ratio). The method of claim 8, The gas having a high carbon / florin ratio is C ₄ F ₈ or C ₄ F _{6 A} method of manufacturing a semiconductor device. The method according to any one of claims 1 to 4, And the second metal layer is TiN. The method of claim 10, Etching the second metal layer. Method of manufacturing a semiconductor device using a gas containing Cl ₂ . The method of claim 11, The gas containing Cl ₂ , A method of manufacturing a semiconductor device which is Cl ₂ / BCl ₃ or Cl ₂ / Ar mixed gas. The method of claim 3, Removing the polymer, A semiconductor device manufacturing method performed by plasma etching of a gas containing O ₂ . The method according to any one of claims 1 to 4, The first metal layer is Al semiconductor device manufacturing method. The method according to any one of claims 1 to 4, Wherein the metal wiring is an upper metal wiring, and the repair fuse is patterned with a metal layer for lower metal wiring.

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