JP3506369B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a fuse portion used for a redundancy repair circuit or a function adjusting circuit of a large capacity memory, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been advanced in microfabrication technology, and dynamic random access memory (DR
The memory capacity of a semiconductor integrated circuit represented by AM), static random access memory (SRAM), etc. has been developed to G-bit class. In addition, in order to achieve high integration, a multi-layer wiring technique has been used for wiring connecting circuit elements. As the storage capacity of semiconductor integrated circuits is increasing due to the progress of microfabrication technology, even fine dust in the manufacturing process may cause defective bits that cause deterioration of the device function or malfunction. However, as it is, the semiconductor integrated circuit becomes defective as a whole, and a decrease in manufacturing yield is becoming a problem. One of the solutions to this is a redundancy repair technology. This is because spare memory bits are manufactured in excess of the memory capacity of the product in advance at the same time as the chip manufacturing process, and even if a defective memory bit occurs due to a defect in part of the chip, it is switched to the spare memory bit. This is a technology for relieving defective bits in which all memory capacity of a product is changed to non-defective bits. One of the methods for switching between the defective memory bit and the spare memory bit is a redundant relief technique by laser processing.
This is a technique for irradiating a laser beam to blow or cut a fuse portion of a redundant relief switching circuit on a chip to realize the switching.

Conventionally, one of fuse materials to be laser processed is polysilicon or silicide of the same material as a gate electrode of a MOS transistor or a bit signal line, and polycide in which these layers are laminated and multilayered because of ease of manufacturing process. Mainly used fuse material.

The fuse portion used in the conventional redundancy repair switching circuit will be described below. FIG. 22 is a cross-sectional view of main parts of a conventional semiconductor integrated circuit device. In FIG. 22, 1 is a semiconductor substrate, 2 is an interlayer insulating film, 3 is a fuse part made of, for example, a polycide layer, 4 is an inorganic insulating protective film, 5 is an organic insulating protective film, 6 is an opening, and 7 is a pad electrode. . The pad electrode 7 is an electrode for connecting with a package assembly lead, and the organic insulating protective film 5 and the inorganic insulating protective film 4 above the pad electrode 7 are removed and opened by a usual etching method. At the same time, the organic insulating protective film 5 and the inorganic insulating protective film 4 above the fuse portion 3 are removed by selective etching to form the opening 6 so that the fuse portion 3 can be easily cut by laser light irradiation. The interlayer insulating film 8 above 3 is also thinned.

[0005]

However, semiconductor integrated circuits have become multi-layered wiring in response to high integration and miniaturization. Therefore, the conventional configuration has new technical problems. In other words, because multi-layer wiring is used,
Many wiring layers are provided above the fuse portion made of a polycide layer or the like, and as a result, the thickness of the interlayer insulating film above the fuse portion is increased. Therefore, when forming an opening of the interlayer insulating film for making electrical contact between the multilayer wiring layers above the fuse, a step of simultaneously removing the opening of the interlayer insulating film above the fuse portion is also applied as a result. It has been devised such as adopting the process of thinning the interlayer insulating film on the fuse. If this is not done, the protective film and interlayer insulating film above the fuse part will become thick, and the fuse material gasified by laser irradiation when the fuse part is blown breaks the protective film and insulating film above the chip part This is because a large explosive force was needed to scatter outside. In other words, it is necessary to increase the irradiation energy of the laser to the fuse portion to blow and gasify the fuse portion in a shorter time and increase the instantaneous explosion pressure at that time.

However, the pressure is exerted simultaneously on the direction of the semiconductor substrate below the blow fuse portion and the direction of the periphery of the blow fuse portion at the time of explosion. At the same time, excessive thermal energy for cutting the fuse portion causes excessive heating of the semiconductor substrate portion below the fuse portion. Therefore, excessive laser energy irradiation causes damage such as cracking or fusing to the semiconductor substrate portion below the fuse portion. Even if this damage is small with respect to the initial variation in the electrical characteristics of the semiconductor integrated circuit, it may affect the reliability thereof. Also, if a large explosion occurs simultaneously in the semiconductor substrate, the adjacent fuses that do not need to be blown may also be blown by the explosion, causing the desired redundant relief circuit operation to become impossible and the memory bit relief to be performed. This made it impossible to reduce the production yield.

Therefore, as a countermeasure against this problem, the insulating film and the interlayer film above the fuse portion are removed by selective etching and the remaining film is thinned. In recent years, some multilayer wirings for highly integrating semiconductor integrated circuits have more than three layers, and the thickness of the interlayer insulating film above the fuse portion is also increasing. Therefore, the thickness of the interlayer insulating film to be removed by etching is increased from about 1 μm to several μm or more, and a long etching removal time is required. This causes a decrease in the throughput of the etching apparatus, which is a technical problem that the manufacturing time is long. In addition, it is difficult to keep the in-plane variation and fluctuation of the etching rate small during etching removal for a wafer with a diameter of 8 inches or more. There is also a technical problem that it is difficult to uniformly control in-plane.

An object of the present invention is to provide a semiconductor integrated circuit device having a multi-layered wiring corresponding to the miniaturization and high integration, which can prevent a decrease in reliability and a decrease in manufacturing yield due to cutting of a fuse part. And a method for manufacturing the same.

Still another object of the present invention is to provide a semiconductor integrated circuit device and a method of manufacturing the same which can shorten the manufacturing time by shortening the formation time of the opening above the fuse portion.

[0010]

According to another aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: an uppermost wiring layer formed on an interlayer insulating film formed on a semiconductor substrate; and an uppermost wiring layer and an interlayer. an inorganic insulating protective film formed on the insulating film, a semiconductor integrated circuit device having a formed on the inorganic insulating protective film organic insulating protective film, the wiring of the uppermost layer which is formed on the interlayer insulating film a fuse unit comprising a layer, the upper portion of the fuse unit
And the opening of the organic insulating protective film provided on the
The wiring layer in the gap portion is characterized by having at least a metal layer for main conduction .

According to the structure of the first aspect, the fuse portion is formed by the uppermost wiring layer formed on the interlayer insulating film, and the opening portion is provided in the organic insulating protective film as the opening portion above the fuse portion. Therefore, it is not necessary to etch the interlayer insulating film to form the opening in the upper portion of the fuse portion as in the conventional case, and the time for forming the opening can be shortened and the overall manufacturing time can be shortened. . In addition, since only the inorganic insulating protective film is formed on the fuse part, the fuse part can be easily cut without increasing the irradiation energy of the laser beam, and the fuse part can be cut reliably. It does not cause deterioration of the productivity and the manufacturing yield. Further, since the fuse part is covered with the inorganic insulating protective film, the moisture resistance can be improved.

A semiconductor integrated circuit device according to claim 2 is
The semiconductor integrated circuit device according to claim 1, wherein interlayer insulation is provided.
External extraction consisting of the uppermost wiring layer formed on the film
And electrodes, are <br/> and a opening of the opening and an organic insulating protective film of an inorganic insulating protective film provided on the upper portion of the external lead electrodes. Thus, the opening above the fuse portion can be formed at the same time as the opening above the organic insulating protective film above the external extraction electrode, and no particular time is required to form the opening above the fuse portion.

A semiconductor integrated circuit device according to a third aspect is
The semiconductor integrated circuit device according to claim 1,
The upper portion of the fuse portion of the inorganic insulating protective film exposed at the opening of the organic insulating protective film is etched to be thinned. This makes it easier to cut the fuse portion by irradiating the laser beam.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, which includes a step of forming a fuse portion including an uppermost wiring layer on an interlayer insulating film formed on a semiconductor substrate.
A step of forming an inorganic insulating protective film on the uppermost wiring layer and the interlayer insulating film, a step of forming an organic insulating protective film on the entire surface after forming the inorganic insulating protective film, and an organic insulating protective film on the fuse part. And a step of forming an opening of
The wiring layer of at least has a metal layer for main conduction .

According to the manufacturing method of the fourth aspect, the fuse portion is formed by the uppermost wiring layer formed on the interlayer insulating film, and the opening portion is formed in the organic insulating protective film as the opening portion above the fuse portion. Since it is sufficient to form the opening, it is not necessary to etch the interlayer insulating film to form the opening in the upper portion of the fuse portion as in the related art, and it is possible to shorten the formation time of the opening and shorten the entire manufacturing time. it can. In addition, since only the inorganic insulating protective film is formed on the fuse portion, the fuse portion can be easily cut without increasing the laser irradiation energy excessively, and the fuse portion is cut to improve reliability. It does not cause a decrease in manufacturing yield. Further, since the fuse part is covered with the inorganic insulating protective film, the moisture resistance can be improved.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, which includes a step of forming a fuse portion and an external lead electrode made of an uppermost wiring layer on an interlayer insulating film formed on a semiconductor substrate. A step of forming an inorganic insulating protective film on the upper wiring layer and the interlayer insulating film, a step of selectively etching the inorganic insulating protective film to form an opening above the external extraction electrode, and an opening of the inorganic insulating protective film. After forming the portion, a step of forming an organic insulating protective film on the entire surface, and a step of forming an opening of the organic insulating protective film on the upper portion of the fuse portion and the upper portion of the external extraction electrode, the wiring layer of the fuse portion, Less
Both have a main conductive metal layer .

According to the manufacturing method of the fifth aspect, in addition to the function and effect of the manufacturing method of the fourth aspect, since the external extraction electrode is also formed by the uppermost wiring layer, the organic insulating protective film above the fuse portion is formed. The opening can be formed at the same time as the opening of the organic insulating protective film above the external extraction electrode, and there is no particular time required to form the opening of the organic insulating protective film above the fuse portion.

A method of manufacturing a semiconductor integrated circuit device according to a sixth aspect is the method of manufacturing a semiconductor integrated circuit device according to the fourth or fifth aspect, wherein after forming the opening of the organic insulating protective film,
The method is characterized by including a step of thinning the inorganic insulating protective film in the portion exposed in the opening by etching. As a result, the inorganic insulating protective film on the fuse portion is thinned, and the fuse portion can be more easily cut by laser light irradiation.

According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit device, which comprises a step of forming a fuse portion and an external lead electrode made of an uppermost wiring layer on an interlayer insulating film formed on a semiconductor substrate. A step of forming an inorganic insulating protective film on the upper wiring layer and the interlayer insulating film, and a step of forming a first photoresist on the entire surface after forming the inorganic insulating protective film,
Forming an opening in the first photoresist on top of at least the fuse portion, a step of thinning by etching the inorganic insulating protective film in a portion exposed to the opening of the first photoresist, an inorganic insulating protective A step of removing the first photoresist after thinning the film, a step of forming a second photoresist on the entire surface after removing the first photoresist, and a second photoresist on the external extraction electrode. And a step of forming an opening of the inorganic insulating protective film above the external extraction electrode by etching away the portion of the inorganic insulating protective film exposed in the opening of the second photoresist. , The opening of the inorganic insulating protective film
A step of removing the second photoresist after the formation,
After removing the photoresist, the step of forming an organic insulating protective film on the entire surface and the step of forming an opening of the organic insulating protective film on the fuse portion and the external extraction electrode are included.

According to the manufacturing method of the seventh aspect, the fuse portion is formed by the uppermost wiring layer formed on the interlayer insulating film, and the opening portion is formed in the organic insulating protective film as the opening portion above the fuse portion. Since it is sufficient to form the opening, it is not necessary to etch the interlayer insulating film to form the opening in the upper portion of the fuse portion as in the related art, and it is possible to shorten the formation time of the opening and shorten the entire manufacturing time. it can. Further, the opening of the organic insulating protective film above the fuse portion can be formed at the same time as the opening of the organic insulating protective film above the external extraction electrode, so that the opening of the organic insulating protective film above the fuse portion can be formed. No time is required. In addition, since only a thin inorganic insulating protective film is formed on the fuse part, the fuse part can be easily cut without increasing the laser irradiation energy. It does not cause deterioration of the productivity and the manufacturing yield. Further, since the fuse part is covered with the inorganic insulating protective film, the moisture resistance can be improved.

A semiconductor integrated circuit device according to an eighth aspect of the present invention is a semiconductor integrated circuit device having a multi-layered wiring structure including one wiring layer forming a fuse portion, wherein an insulating film above the fuse portion is thinned. The one wiring layer forming the fuse part is formed on the interlayer insulating film and has a lower barrier metal layer, and the fuse part is a part of the one wiring layer where the barrier metal layer is removed or thinned. It is characterized in that it is configured with.

A semiconductor integrated circuit device according to a ninth aspect is the semiconductor integrated circuit device according to the eighth aspect, wherein one wiring layer forming the fuse portion is embedded in a groove formed on the surface of the interlayer insulating film. It is characterized by

According to the eighth and ninth aspects of the present invention, the fuse portion is formed by removing or thinning the barrier metal layer below the wiring layer, and the fuse portion does not have a high melting point barrier metal layer. Alternatively, since the fuse portion is thinned, the fuse portion can be easily and surely cut without increasing the laser irradiation energy, and the fuse portion does not cause a decrease in reliability and a reduction in manufacturing yield.

According to a tenth aspect of the semiconductor integrated circuit device,
The semiconductor integrated circuit device according to claim 8 or 9,
One wiring layer forming the fuse portion is the uppermost wiring layer, and the thinned insulating film above the fuse portion is an inorganic insulating protective film. As a result, the fuse portion is covered with the inorganic insulating protective film, so that the moisture resistance can be improved.

A method of manufacturing a semiconductor integrated circuit device according to claim 11 has a multilayer wiring structure including one wiring layer forming a fuse portion, and a semiconductor integrated circuit in which an insulating film above the fuse portion is thinned. A method of manufacturing a device, comprising: a step of forming a barrier metal layer on an interlayer insulating film formed on a semiconductor substrate; a step of applying a photoresist on the barrier metal layer; A step of forming an opening in the resist, a step of removing or thinning the barrier metal layer exposed in the opening of the photoresist by etching, and a barrier metal
After removing or thinning the layer, the step of removing the photoresist, the step of forming the main conductive metal layer after removing the photoresist, and by etching the main conductive metal layer and the barrier metal layer into a desired shape Forming a fuse part including a metal layer for main conduction and forming one wiring layer including a metal layer for main conduction and a barrier metal layer.

According to the manufacturing method of the eleventh aspect, the fuse portion is formed by removing or thinning the barrier metal layer under the wiring layer, and the fuse portion does not have or has a high melting point barrier metal layer. Therefore, the cutting of the fuse portion can be easily and surely performed without increasing the laser irradiation energy, and the cutting of the fuse portion does not lower the reliability or the manufacturing yield.

A method for manufacturing a semiconductor integrated circuit device according to a twelfth aspect of the present invention is a semiconductor integrated circuit having a multilayer wiring structure including one wiring layer forming a fuse portion, wherein an insulating film above the fuse portion is thinned. A method of manufacturing a device, wherein a groove is formed in an interlayer insulating film formed on a semiconductor substrate, a step of forming a barrier metal layer on the inner surface of the groove, and a step of applying a photoresist on the barrier metal layer, A step of forming a photoresist opening at least in a region corresponding to the fuse portion, a step of removing or thinning the barrier metal layer exposed in the photoresist opening by etching, and a step of removing or thinning the barrier metal layer. After removing the photoresist, the step of removing the photoresist, and after removing the photoresist,
A step of forming a fuse part including the main conductive metal layer by embedding the main conductive metal layer in the groove and forming one wiring layer including the main conductive metal layer and the barrier metal layer. To do.

According to the manufacturing method of the twelfth aspect, as in the eleventh aspect, the fuse portion is formed by removing or thinning the barrier metal layer under the wiring layer.
The same effect as 1 can be obtained.

A method of manufacturing a semiconductor integrated circuit device according to a thirteenth aspect is the method of manufacturing a semiconductor integrated circuit device according to the eleventh or twelfth aspect, wherein one wiring layer forming the fuse portion is an uppermost wiring layer. Further, the thinned insulating film on the fuse portion is an inorganic insulating protective film. As a result, the fuse portion is covered with the inorganic insulating protective film, so that the moisture resistance can be improved.

A semiconductor integrated circuit device according to claim 14 is
The semiconductor integrated circuit device according to any one of claims 1, 2, 3, 8, 9 and 10 is characterized in that at least two electrically fused fuse portions are blown by laser irradiation. This makes it possible to more reliably electrically cut the fuse portion.

A semiconductor integrated circuit device according to claim 15 is
The semiconductor integrated circuit device according to claim 14 is characterized in that a plurality of fuse portions are provided, and portions of the plurality of fuse portions that are blown by laser irradiation are arranged on a straight line. As a result, the fuse portion can be electrically disconnected at a high speed by laser irradiation, and throughput can be improved and productivity can be improved.

A semiconductor integrated circuit device according to claim 16 is
16. The semiconductor integrated circuit device according to claim 1, 2, 3, 10, 14 or 15, wherein at least one end of the fuse portion formed of the uppermost wiring layer is connected to the lower wiring layer via a contact hole. However, a guard band made of a conductive layer is provided so as to surround the fuse portion and the contact hole. In this way, by reconnecting the fuse wiring inside the guard band to the wiring layer in the lower layer through the contact hole, moisture and ionic components from the cut portion of the fuse portion can pass through the fuse wiring remaining after cutting. The permeation path is extended, and since the entire circumference of the contact hole is surrounded by a guard band, it is possible to prevent moisture and ionic components from permeating inside the card band, and outside the guard band (semiconductor element part). Water and ionic components do not come into, contributing to the improvement of reliability.

A semiconductor integrated circuit device according to claim 17 is
The semiconductor integrated circuit device according to any one of claims 1, 2, 3, 10, 14, 15 or 16 is characterized in that a wiring width of a portion of the fuse portion to be cut by laser is 1.0 µm or less. As a result, the fuse portion can be easily and reliably laser-cut.

A semiconductor integrated circuit according to claim 18 is the semiconductor integrated circuit device according to claim 1, 2, 3, 10, 14, 15, 16 or 17, wherein the wiring layer of the fuse portion is a metal layer for main conduction. The barrier metal layer formed below the barrier metal layer has a thickness of 150 nm or less at least under the laser cutting portion of the fuse portion. As a result, when the fuse portion is laser-cut, it can be surely cut without leaving the barrier metal layer below the fuse portion.

According to a nineteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device according to the fourth, fifth, sixth, seventh, eleventh, twelfth or one aspect.
3. The method for manufacturing a semiconductor integrated circuit device according to 3, further comprising the step of irradiating the fuse portion with laser light from a YLF crystal having a wavelength of 1047 nm to 1053 nm and a pulse width of 2 to 10 ns. Characterize. By using such a laser beam, damage to the base of the fuse portion can be suppressed and the fuse portion can be cut.

A method for manufacturing a semiconductor integrated circuit device according to a twentieth aspect of the present invention is the method of producing a semiconductor integrated circuit device according to any one of the fourth to fifth aspects.
3. The method for manufacturing a semiconductor integrated circuit device according to 3, wherein the wiring layer of the fuse portion is composed of a main conductive metal layer and a barrier metal layer formed thereunder, and a laser light source having at least two wavelength components is used. It is characterized by having a step of cutting the fuse portion. With this, when the fuse portion is cut, it is possible to selectively irradiate the wavelength components corresponding to the cutting of the main conductive metal layer and the barrier metal layer, and it is possible to increase the laser energy margin and improve the processing yield. it can.

The method of manufacturing a semiconductor integrated circuit device according to claim 21 is the method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein the laser light source has a wavelength component around 1340 nm and a wavelength component around 1050 nm. It is characterized by As a result, when the main conductive metal layer is formed of a metal mainly containing aluminum and the barrier metal layer is formed of titanium nitride, titanium, or the like, the main conductive metal layer is
The barrier metal layer is irradiated with laser light having a wavelength of around 340 nm.
By irradiating with a laser beam having a wavelength of about 050 nm, a large laser energy margin can be secured and the processing yield can be increased.

A method for evaluating a semiconductor integrated circuit device according to a twenty-second aspect is the method of preparing a plurality of samples each having a fuse group in which two or more different fuse parts are connected in parallel on a semiconductor substrate, and a fuse for each sample. The first measurement step to measure the resistance value at both ends of the group, the step of irradiating each sample with laser light to cut all the fuse parts, and the resistance value at each end of the fuse group after laser irradiation for each sample A second measuring step for calculating the fuse cutting yield from the results of the first and second measuring steps for each sample, and a semiconductor integrated circuit based on the relationship between the fuse cutting yield calculated for each sample and the number of fuse parts And a step of estimating a cutting yield in the number of actually used fuse parts of the device. In this way, it is possible to accurately estimate the cutting yield in the number of actually used fuse parts of the semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 23 is the semiconductor integrated circuit device according to claim 1, 2, 3, 10, 14, 15, 16.
Alternatively, in the semiconductor integrated circuit device described in the paragraph 17, the wiring layer of the fuse portion is composed of a main conductive metal layer and a barrier metal layer formed below the main conductive metal layer. Claim 24
The semiconductor integrated circuit device according to claim 1 is a semiconductor integrated circuit device.
In the semiconductor integrated circuit device described in 0, 14, 15, 17, and 23, at least one end of the fuse portion formed of the uppermost wiring layer is connected to the lower wiring layer through a contact hole. And The semiconductor integrated circuit device according to claim 25, wherein the uppermost wiring layer formed on the interlayer insulating film formed on the semiconductor substrate and the inorganic insulating film formed on the uppermost wiring layer and the interlayer insulating film. A protective film,
A semiconductor integrated circuit device having an organic insulating protective film formed on an inorganic insulating protective film, comprising a fuse portion formed of an uppermost wiring layer formed on an interlayer insulating film, and provided on the fuse portion. And the wiring layer of the fuse portion is at least a metal layer for main conduction.
And the inorganic insulating protective film exposed in the opening of the organic insulating protective film is etched to be thinned.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[ First Embodiment ] FIG. 1 is a partial cross-sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, 11 is a semiconductor substrate and 12 is an interlayer insulating film. , 13 are fuse parts, 1
4 is an inorganic insulating protective film, 15 is an organic insulating protective film, 16 and 1
Reference numeral 9 is an opening of the organic insulating protective film 15, 17 is a pad electrode which is an external extraction electrode, and 18 is an opening of the inorganic insulating protective film 14.

In the semiconductor integrated circuit device of the present embodiment, the fuse portion 13 and the pad electrode 17 are formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the upper portion of the fuse portion 13 is formed with the organic material. An opening 16 of the insulating protection film 15 is provided, and an upper portion of the pad electrode 17 is opened by an opening 18 of the inorganic insulation protection film 14 and an opening 19 of the organic insulation protection film 15. Furthermore, in order to thin the inorganic insulating protective film 14 on the fuse portion 13, the opening 1 of the organic insulating protective film 1 is formed.
The inorganic insulating protective film 14 exposed at 6 and 19 is etched and thinned. Further, the opening 19 of the organic insulating protective film 15 provided on the pad electrode 17 is formed in a wider area than the opening 18 of the inorganic insulating protective film 14, and is formed in the pad electrode 17 and a region in the vicinity thereof. There is.

In the present embodiment, the pad electrode 17 which is an external extraction electrode is reduced to the package assembly limit, a large number of pad electrodes 17 are mounted at a high density, and the opening 19 is formed in order to suppress the chip size. Has been shown to be wider than the opening 18, but the present invention is not limited to this, and the case where the opening 19 and the opening 18 have the same width or the opening 19 has the same width.
Needless to say, it may be narrower than the opening 18. Although the case where the inorganic insulating protective film 14 is thinned is shown, the present invention is not limited to this, and when the inorganic insulating protective film 14 is thin from the beginning when the fuse is blown, it is not necessary to intentionally thin the film. Not to mention the matter.

Further, in this embodiment, one opening 1
Although the case where two fuse parts 13 are formed under 6 has been illustrated, the present invention is not limited to this, and one fuse part 13 may be provided under one opening 16, or 3 It goes without saying that there may be more than one book.

FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 3 is a process flow chart showing the same manufacturing method. This will be described below with reference to FIGS. 2 and 3.

The elements formed on the semiconductor substrate 11 are wired in multiple wiring layers (not shown). The fuse portion 13 and the pad electrode 17 are formed on the uppermost metal wiring layer on the interlayer insulating film 12 of the multi-layer wiring, and the plasma silicon nitride film [plasma CVD (Chemical Vapor Deposition) is formed thereon.
An inorganic insulating protective film 14 such as a silicon nitride film formed by the above method is formed to a thickness of about 1 μm (FIG. 2A, step S of FIG. 3).
11, S12).

After that, a photoresist (not shown) is applied, an opening is formed in the resist on the pad electrode 17, and the pad electrode 1 is formed by a normal dry etching process.
The inorganic insulating protective film 14 above 7 is removed by selective etching to form an opening 18. After that, the photoresist (not shown) is removed (FIG. 2B, steps S13 to S16 in FIG. 3).

Next, a photosensitive organic insulating protective film 15 is formed on the entire surface.
Is applied to a thickness of about 10 μm and patterned in a lithographic process to form an opening 16 on the fuse portion 13 and an opening 19 on the pad electrode 17 (FIGS. 2 (c) and 3).
Steps S17 and S18). Normally, an organic insulating protective film 1
5 uses a photosensitive polyimide film or the like, but is not limited thereto, and the case of a thickness of about 10 μm has been described, but it goes without saying that the invention is not limited to this.

Thereafter, if necessary, the inorganic insulating protective film 14 exposed in the openings 16 and 19 is etched so that the film thickness of the inorganic insulating protective film 14 on the fuse portion 13 is 0.1 to 0.1. The thickness is reduced to 0.8 μm (configuration of FIG. 1, step S19 of FIG. 3). The etching amount is not limited to this, and the thinner the thickness of the inorganic insulating protective film 14 on the fuse portion 13, the more likely the fuse can be reliably cut. However, if the thickness of the inorganic insulating protective film 14 is thin, the inorganic insulating protective film 14 is easily affected by the filler of the resin sealing at the time of package assembly performed later, and the film thickness of the inorganic insulating protective film 14 is large from the viewpoint of moisture resistance performance. Better When the space between the adjacent fuse portions 13 is wide, the inorganic insulating protective film 14 does not have to be thinned by etching. This is because, when the fuse portion 13 is cut by laser light irradiation to be performed later, the thicker the film thickness of the inorganic insulating protective film 14 on the fuse portion 13, the larger the cut opening diameter, and the narrower the distance between the fuse portions 13. This is because the adjacent fuse portions 13 are affected in some cases, but the adjacent fuse portions 13 are not affected when the distance between the fuse portions 13 is wide.

As described above, according to the present embodiment, the fuse portion 13 is formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the opening portion 16 above the fuse portion 13 is formed.
Since the opening may be formed in the organic insulating protective film 15 as described above, it is not necessary to etch the interlayer insulating film 2 in order to form the opening 6 above the fuse portion 3 as in the conventional case shown in FIG. It is possible to shorten the formation time of the opening 16 above the fuse portion 13 and shorten the entire manufacturing time. Further, the opening 16 above the fuse portion 13 can be formed at the same time as the opening 19 above the pad electrode 17, and no particular time is required to form the opening 16 above the fuse portion 13. Further, since only the inorganic insulating protective film 14 is formed on the fuse portion 13, the fuse portion 13 can be easily cut without increasing the laser irradiation energy. It is possible to achieve high reliability and high productivity without lowering the productivity and the manufacturing yield. In addition, the fuse unit 1
Since 3 is covered with the inorganic insulating protective film 14, the moisture resistance can be improved.

Further, after the step of FIG. 2C, the inorganic insulating protective film 14 is etched to be thinned to have the structure of FIG. 1, so that the fuse portion 13 can be more easily cut by laser light irradiation.

In this embodiment, the interlayer insulating film 12 is also used.
Since the fuse portion 13 is formed by the uppermost wiring layer above, conventionally, in a wafer having a diameter of 8 inches or more, the remaining amount of the interlayer insulating film on the upper portion of the fuse portion can be accurately made uniform within the wafer surface. The problem of being difficult to control does not occur.

Furthermore, in the present embodiment, the thickness of the inorganic insulating protective film 14 on the fuse portion 13 can be uniformly controlled within the wafer surface in a wafer having a diameter of 8 inches or more. In the case of the configuration of FIG. 2C, uniformity can be secured within the wafer surface within about ± 10% (within about ± 0.1 μm) of the formed film thickness (about 1 μm) of the inorganic insulating protective film 14. In the case of the structure of FIG. 1 in which the inorganic insulating protective film 14 is thinned to about 0.1 to 0.8 μm, the etching amount for thinning corresponds to about 0.9 to 0.2 μm. Can be controlled to within about ± 10% (within about ± 0.09 to 0.02 μm) of the etching variation, and the square sum of the variation of the formed film thickness (about ± 10%) and the etching variation (about ± 10%) can be controlled. It is possible to control the uniformity within the wafer surface within about ± 0.15 μm of the square root.

In the above embodiment, the case where the inorganic insulating protective film 14 is formed to a thickness of about 1 μm has been described. However, if the interlayer insulating film 12 has a good flatness, no problem occurs in the moisture resistance and characteristics of the product. In some cases, the inorganic insulating protective film 14 is about 1
It goes without saying that the thickness may be thinner than μm. Also,
In forming a multi-layered wiring, a wiring method (damascene: damascene:
In the case of Damascene), the uppermost wiring is relatively flat and has good coverage. Even if the inorganic insulating protective film 14 is made thinner than 1 μm, the uppermost wiring is relatively flat and the inorganic insulating protective film 14 is thin.
Needless to say, there is no need to further reduce the thickness of the inorganic insulating protective film 14 by etching, since the coverage of the product is improved and the moisture resistance and characteristics of the product may not be a problem.

On the contrary, when the interlayer insulating film 12 has poor flatness or when the moisture resistance performance deteriorates in the reliability test of the product, the inorganic insulating protective film 14 is set to about 1 μm or more and divided into one or more times. To form. Needless to say, the inorganic insulating protective film 14 may be composed of a combination of a single layer and a plurality of layers of a silicon nitride film or a silicon oxide film.

Although the thickness of the inorganic insulating protective film 14 above the fuse portion 13 is reduced to about 0.1 to 0.8 μm, the thickness is not limited to this. For example, fuse part 1
It goes without saying that the inorganic insulating protective film 14 on 3 may not be left (the film thickness is 0), and even if the inorganic insulating protective film 14 does not remain, there may be no problem in the moisture resistance and characteristics of the product. .

However, when the inorganic insulating protective film 14 does not exist on the fuse portion 13 at all, the moisture-resistant protective film disappears, so that the reliability generally tends to deteriorate. Further, when a large etching amount is set for the purpose of completely removing the inorganic insulating protective film 14 on the fuse portion 13, the upper portion of the fuse portion 13 is simultaneously etched in parallel, so that the film thickness of the fuse portion 13 is reduced. It becomes thinner and deviates from the designed value, which in turn increases the resistance, leading to disconnection. If the inorganic insulating protective film 14 does not exist on the fuse portion 13, the cutting of the fuse portion 13 by the laser becomes unstable. This is because the wiring layer constituting the fuse portion 13 is usually connected to the wiring layer in the lower layer through a contact hole, a thin barrier metal layer having a high melting point is formed on the wall surface of the contact hole, and an aluminum metal layer is formed thereon. Further, since the main conductive metal layer made of aluminum-copper alloy or the like is formed, a thin barrier metal layer having a high melting point is laid under the fuse portion 13, and the fuse portion 13 is cut at the time of laser heating cutting. The main component of the aluminum and the aluminum-copper-based main conductive metal layer is heated in advance, and immediately after laser irradiation fusing and gasifying and scattering, but the barrier metal layer with a high melting point is below. This is because the barrier metal layer may be left uncut, resulting in partial disconnection of the barrier metal layer, resulting in defective fuse cutting. When the inorganic insulating protective film 14 remains on the upper and side portions of the fuse portion 13 even for a little, the thin barrier metal layer laid on the lower portion of the fuse portion 13 also receives heat conduction from the heated aluminum until it is melted. It becomes possible to earn time. As a result, when the fuse portion 13 is melted and gasified to break the inorganic insulating protective film and the fuse portion 13 is scattered, the barrier metal layer is also scattered at the same time, so that the fuse can be cut reliably.

When the fuse portion 13 is composed of the uppermost wiring layer, after the inorganic insulating protective film 14 is formed, the corner portion of the fuse portion 13 is rounded in a semicircle so as to cover the fuse portion 13 and is made of inorganic insulating material. It is covered with the protective film 14. When the inorganic insulating protective film 14 is thinned by dry etching, the thickness of the inorganic insulating protective film 14 remaining on the side wall of the fuse portion 13 is smaller than the thickness of the inorganic insulating protective film 14 remaining on the upper portion of the fuse portion 13. Also becomes thicker (refer to the inorganic insulating protective film 39 in FIG. 19), the time from the laser irradiation for cutting the fuse to the scattering can be made sufficient, and the inorganic insulating on the upper part of the fuse portion 13 which is easy to scatter upward Protective film 1
It can be thinned to a film thickness of 4. On the other hand, when the inorganic insulating protective film is thinly formed on the fuse portion 13, the thickness of the inorganic insulating protective film on the upper and side portions of the fuse portion 13 can be made substantially the same. Possible, but
In this case, the cutting probability was high, but it was not stable enough. This is because, since the film thickness of the side portion is small, the fuse scattering starts early, so that the heating and melting of the barrier metal layer becomes insufficient and a part of the barrier metal layer may remain.

[ Second Embodiment ] FIG. 4 is a partial cross-sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention. In FIG. 4, 11 is a semiconductor substrate and 12 is an interlayer insulating film. , 13 are fuse parts, 1
4 is an inorganic insulating protective film, 15 is an organic insulating protective film, 16 and 1
Reference numeral 9 is an opening of the organic insulating protective film 15, 17 is a pad electrode which is an external lead electrode, 18 is an opening of the inorganic insulating protective film 14, and 20 is an inorganic insulating protective film on the fuse portion 13.

In the semiconductor integrated circuit device of the present embodiment, the fuse portion 13 and the pad electrode 17 are formed by the uppermost wiring layer formed on the interlayer insulating film 12, and the upper portion of the fuse portion 13 is formed with an organic material. An opening 16 of the insulating protection film 15 is provided, and an upper portion of the pad electrode 17 is opened by an opening 18 of the inorganic insulation protection film 14 and an opening 19 of the organic insulation protection film 15. Further, in order to reduce the thickness of the inorganic insulating protective film 20 on the fuse portion 13, the opening 1 of the organic insulating protective film 1 is formed.
The inorganic insulating protective film 14 exposed at 6 is thinned by etching. Further, the opening 19 of the organic insulating protective film 15 provided on the pad electrode 17 is formed in a wider area than the opening 18 of the inorganic insulating protective film 14, and is formed in the pad electrode 17 and a region in the vicinity thereof. There is.

In the present embodiment, the pad electrode 17 which is an external extraction electrode is reduced to the package assembly limit, a large number of pad electrodes 17 are mounted at high density, and the opening 19 is formed in order to suppress the chip size. Has been shown to be wider than the opening 18, but the present invention is not limited to this, and the case where the opening 19 and the opening 18 have the same width or the opening 19 has the same width.
Needless to say, it may be narrower than the opening 18. Then, the inorganic insulating protective film 14 is thinned,
The case of using the inorganic insulating protective film 20 on the fuse portion 13 is shown, but the invention is not limited to this, and the pad electrode 1
It goes without saying that the inorganic insulating protective film 14 in the opening 19 may also be thinned in order to facilitate the formation of the opening 18 in 7.

Further, in this embodiment, one opening 1
Although the case where two fuse parts 13 are formed under 6 has been illustrated, the present invention is not limited to this, and one fuse part 13 may be provided under one opening 16, or 3 It goes without saying that there may be more than one book.

FIGS. 5 and 6 are process sectional views showing a method of manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 7 is a process flow chart showing the same manufacturing method. This will be described below with reference to FIGS.

The elements formed on the semiconductor substrate 11 are wired by multilayer wiring layers (not shown). The fuse portion 13 and the pad electrode 17 are formed on the uppermost metal wiring layer on the interlayer insulating film 12 of the multi-layer wiring, and the plasma silicon nitride film [plasma CVD (Chemical Vapor Deposition) is formed thereon.
An inorganic insulating protective film 14 such as a silicon nitride film formed by the above method is formed to a thickness of about 1 μm (FIG. 5A, step S of FIG. 7).
21, S22).

After that, a photoresist 21 is applied to form an opening A in the resist on the fuse portion 13 (FIG. 5B, steps S23 and S24 in FIG. 7). Then, the fuse portion 1 is subjected to a normal dry etching process.
The inorganic insulating protective film 14 in the opening A above 3 is thinned. The inorganic insulating protective film 14 below the opening A is thinned until the inorganic insulating protective film 20 above the fuse portion 13 has a film thickness of about 0.1 to 0.8 μm. After that, the photoresist 21 is removed (FIG. 5C, steps S25 and S26 in FIG. 7).

Next, a photoresist 22 is applied to form an opening B in the resist on the pad electrode 17 (FIG. 6 (a), steps S27 and S28 in FIG. 7). Then, the inorganic insulating protective film 14 in the opening B above the pad electrode 17 is removed by selective etching by a normal dry etching process to form an opening 18. At this time, the inorganic insulating protective film 20 on the upper portion of the fuse portion 13 which has already been thinned is not removed by etching. After that, the photoresist 22 is removed (FIG. 6B, step S2 in FIG. 7).
9, S30).

Next, a photosensitive organic insulating protective film 15 is formed on the entire surface.
Is applied to a thickness of about 10 μm and patterned in a lithographic process to form an opening 16 on the fuse portion 13 and an opening 19 on the pad electrode 17 (steps S31 and S32 in FIGS. 4 and 7). ). Normally, a photosensitive polyimide film or the like is used as the organic insulating protective film 15, but the present invention is not limited to this, and the case of a thickness of about 10 μm has been described, but it goes without saying that the present invention is not limited to this.

After that, as a result of measuring the film thickness of the inorganic insulating protective film 20 on the fuse portion 13 with an ordinary measuring device, if necessary, the inorganic insulating protective film exposed in the openings 16 and 19 is exposed. 20 and 23 may be etched to adjust the film thickness of the inorganic insulating protective film 20 above the fuse portion 13. Needless to say, it is not necessary to intentionally perform etching unless it is necessary to adjust the film thickness of the inorganic insulating protective film 20.

As described above, according to this embodiment, the organic insulating protective film 15 is patterned and the openings 16 and 19 are formed.
After forming the hole, the opening 1
The thickness of the inorganic insulating protective film 23 of No. 9 is the same as the thickness of the inorganic insulating protective film 14 under the organic insulating protective film 15, and the opening 1
The inorganic insulating protective film 23 of No. 9 is the inorganic insulating protective film on the periphery of the pad electrode 17 and on the internal wiring and the wiring (not shown) up to the pad electrode 17 and does not reduce the film thickness. To work for you. In addition, the interlayer insulating film 1
The fuse portion 13 is formed by the uppermost wiring layer formed on
Since the opening may be formed in the organic insulating protective film 15 as the opening 16 above the fuse portion 13, the opening 6 above the fuse portion 3 is formed as in the conventional example shown in FIG. 22, for example. Therefore, it is not necessary to etch the interlayer insulating film 2, and the formation time of the opening 16 above the fuse portion 13 can be shortened and the entire manufacturing time can be shortened.

Further, in the step of FIG. 5C (step S25 of FIG. 7), the etching time for adjusting the film thickness of the inorganic insulating protective film 20 on the fuse portion 13 is determined by the opening area ratio of the pad electrode 17. It is possible to set independently without depending on. Further, the metal (aluminum or the like) of the pad electrode 17 is not exposed to the etching gas, the film thickness of the pad electrode 17 itself is not reduced, and the metal-based deposit (adhesion) is not generated during etching. Therefore, stable etching for adjusting the film thickness is possible.

Further, since the thickness of the inorganic insulating protective film 20 is adjusted and etched first, the organic insulating protective film 15 to be performed later is formed.
(Normally used photosensitive polyimide) is patterned in a lithographic process and heat-cured to form the openings 16 and 19, but a thin organic insulating protective film (polyimide film) may remain although it is very slight. However, it does not affect the thickness of the inorganic insulating protective film 20. As a result, since the thin inorganic insulating protective film 20 is formed on the fuse portion 13, the fuse portion 13 can be easily cut without increasing the laser irradiation energy. High reliability and high productivity can be realized without lowering reliability and manufacturing yield by cutting the fuse portion 13. Further, since the fuse portion 13 is covered with the inorganic insulating protective film 20, the moisture resistance can be improved.

In this embodiment, the interlayer insulating film 12 is also used.
Since the fuse portion 13 is formed by the uppermost wiring layer above, conventionally, in a wafer having a diameter of 8 inches or more, the remaining amount of the interlayer insulating film on the upper portion of the fuse portion can be accurately made uniform within the wafer surface. The problem of being difficult to control does not occur.

Further, in the present embodiment, the thickness of the inorganic insulating protective film 20 on the fuse portion 13 can be uniformly controlled within the wafer surface in the wafer having a large diameter of 8 inches or more. In the case of the configuration shown in FIG. 4, within ± 10% of the formed film thickness (about 1 μm) of the inorganic insulating protective film 14 (within about ± 0.1 μm)
Uniformity can be secured within the wafer surface. Further, the etching amount for thinning the inorganic insulating protective film 20 on the fuse portion 13 to about 0.1 to 0.8 μm is about 0.9 to.
Corresponding to 0.2 μm, within about ± 10% (about ± 0.09 ~
It is possible to control the etching variation within 0.02 μm), and it is about ± 0.15 μ of the square root of the sum of squares of the formed film thickness variation (about ± 10%) and the etching variation (about ± 10%).
It is possible to control the in-plane uniformity of the wafer within m.

In the above embodiment, the case where the inorganic insulating protective film 14 is formed to have a thickness of about 1 μm has been described. However, if the interlayer insulating film 12 has a good flatness, the moisture resistance and characteristics of the product will not be a problem. In some cases, the inorganic insulating protective film 14 is about 1
It goes without saying that the thickness may be thinner than μm. Also,
In forming a multi-layered wiring, a wiring method (damascene: damascene:
In the case of Damascene), the uppermost wiring is relatively flat and has good coverage. Even if the inorganic insulating protective film 14 is made thinner than 1 μm, the uppermost wiring is relatively flat and the inorganic insulating protective film 14 is thin.
Needless to say, there is no need to further reduce the thickness of the inorganic insulating protective film 14 by etching, since the coverage of the product is improved and the moisture resistance and characteristics of the product may not be a problem.

On the contrary, when the flatness of the interlayer insulating film 12 is bad or when the moisture resistance performance is bad in the reliability test of the product, the inorganic insulating protective film 14 is set to about 1 μm or more and divided into one or more times. To form. Needless to say, the inorganic insulating protective film 14 may be composed of a combination of a single layer and a plurality of layers of a silicon nitride film or a silicon oxide film.
Further, the thickness of the inorganic insulating protective film 20 on the fuse portion 13 is reduced to about 0.1 to 0.8 μm, but the invention is not limited to this. For example, in some cases, the inorganic insulating protective film 20 on the fuse portion 13 may not be left (film thickness 0), and even if the inorganic insulating protective film 20 does not remain, there may be no problem in moisture resistance and characteristics of the product. Needless to say.

[ Third Embodiment ] FIG. 8A is a plan view showing an arrangement of main parts of a semiconductor integrated circuit device according to a third embodiment of the present invention.
(b) and (c) are x ₁ −x ₁ ′ and x ₂ −x of FIG. 8 (a), respectively.
It is sectional drawing in ₂ '. In addition, FIG. 9 shows y− in FIG.
It is sectional drawing in y '. In FIGS. 8 and 9, 12
Is an interlayer insulating film formed on a semiconductor substrate (not shown),
Reference numeral 13 is a fuse portion, 13A is a main conductive metal layer forming the fuse portion 13, 13a is an antireflection layer, 13b is a barrier metal layer, 14 is an inorganic insulating protective film, 15 is an organic insulating protective film, and 16 is an organic insulating protective film. An opening portion 20 of the film 15 is an inorganic insulating protective film on the fuse portion 13.

The semiconductor integrated circuit device of the present embodiment exemplifies the case where the fuse portion 13 and the pad electrode (not shown) are formed by the uppermost wiring layer formed on the interlayer insulating film 12. There is. After forming a via hole (not shown) in the interlayer insulating film 12, a barrier metal layer 13b is formed to improve the adhesion with the lower wiring and prevent the penetration of the plug electrode metal or the like. As the barrier metal layer 13b, a single-layer film or a double-layer metal film of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) is formed with a film thickness of about 100 nm. . After forming the barrier metal layer 13b, a plug electrode (not shown) of a metal such as tungsten is formed in the via hole, and the barrier metal layer 13b in the region of the opening C (see FIG. 11A) of FIG. 8A is formed. Are removed by selective etching. The fuse portion 13 is formed on the uppermost wiring layer as the uppermost wiring layer. The main conductive metal layer 13A of the fuse portion 13 is mainly made of aluminum metal and an aluminum-copper alloy, and an upper portion thereof is often used as a stepper for the purpose of microfabrication in order to facilitate microfabrication in a lithography process. As an antireflection layer 13a for preventing reflection of light during exposure of a potassium fluoride (KrF: 248 nm) laser or an i-line (365 nm) which is an exposure light source, a titanium nitride (TiN) film or the like which is often often used is used. It is formed with a film thickness of about 10 to 50 nm.

As shown in FIG. 8B, the barrier metal layer 13b is provided below the fuse portion 13 and the antireflection layer 1 is provided above the fuse portion 13.
3a is formed, but before forming the main conductive metal layer 13A, the barrier metal layer 1 in the region of the opening C in FIG. 8A is previously formed.
3b is selectively etched, and as shown in FIG. 8C, the barrier metal layer 13b is not formed under the fuse portion 13. The fuse cutability is improved even when the barrier metal layer 13b is thinned in the region of the opening C, but the fuse cutability is further improved by removing the fuse by etching.

An opening 16 of the organic insulating protective film 15 is provided above the fuse portion 13, and an opening (not shown) of the inorganic insulating protective film 14 and the organic insulating protective film are provided above the pad electrode (not shown). It is opened by 15 openings (not shown). Furthermore, the inorganic insulating protective film 20 on the fuse portion 13
When the fuse is reliably cut by thinning, the inorganic insulating protective film 14 exposed in the opening 16 of the organic insulating protective film is thinned by selectively etching as necessary.

As shown in FIG. 9, a laser beam (hν) pulse is focused and applied to a portion without the barrier metal layer 13b to heat and explode the fuse portion 13 to melt it. At this time, the antireflection layer 13a is also fused. In addition, the inorganic insulating protective film 2
In the case of 0, the fuse portion 13 is also opened at the same time when the explosion is scattered. Since the high melting point barrier metal layer 13b is not provided, the fuse is cut more reliably. Further, the opening (not shown) of the organic insulating protective film 15 provided on the pad electrode (not shown) is formed in a wider area than the opening (not shown) of the inorganic insulating protective film 14. , A pad electrode (not shown) and a region in the vicinity thereof. The pad electrode and its vicinity can be configured in the same manner as in the case of FIGS.

Although the case where the fuse portion 13 is formed of the uppermost wiring layer is shown as an example, the present invention is not limited to this, and one or two wiring layers below the uppermost wiring layer may be used. It goes without saying that it is good. This is because when the barrier metal layer 13b is present under the fuse portion 13, when the uppermost wiring layer is used for the fuse portion 13,
Since the interlayer insulating film layer is flatter when the wiring layer which is one or two layers below the uppermost layer is used for the fuse portion 13,
This is because the remaining probability of the barrier metal layer at the time of cutting the fuse increases and the probability of defective cutting increases, but since the barrier metal layer 13b does not exist in the present embodiment, the cutting can be performed more reliably.

In the present embodiment, the case where the two fuse portions 13 are formed under the one opening 16 has been described as an example, but the present invention is not limited to this and one opening 16 is provided.
It goes without saying that there may be one fuse portion 13 or three or more fuse portions 13 underneath.

10 to 12 are process sectional views showing a method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention, and FIG. 13 is a process flow chart showing the same manufacturing method. This will be described below with reference to FIGS.

In FIG. 10A, the elements formed on the semiconductor substrate 11 are wired by the multilayer wiring layers (25 etc.) formed on the interlayer insulating film 24 and the plug metal (not shown). A groove for wiring is formed on the surface of the interlayer insulating film 24, the wiring layer 25 buried in the groove is formed, and then the next interlayer insulating film 26 is formed on the entire surface (step S4 in FIG. 13).
1). Although the case where the wiring layer 25 is embedded in the groove is illustrated here, the present invention is not limited to this, and the wiring layer 25 is formed on the surface of the flattened interlayer insulating film 24, and then the following is formed on the entire surface. It goes without saying that the interlayer insulating film 26 may be formed and the surface thereof may be planarized.

Next, a via hole 27 for contact is used.
Is formed on the interlayer insulating film 26 on the wiring layer 25 to be connected (FIG. 10B, step S42 in FIG. 13). next,
A barrier metal layer 28 for improving the adhesiveness with the lower wiring layer 25 and preventing the penetration of the plug electrode metal or the like is formed on the entire surface of the semiconductor substrate by a CVD method or the like which is a usual method. As the barrier metal layer 28, a single-layer film or a multi-layer metal layer of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) is formed with a thickness of about 100 nm. Next, a plug electrode 29 of a metal such as tungsten is formed in the via hole 27 by a normal selective growth method (FIG. 10 (c), steps S43 and S4 in FIG. 13).
4).

Next, a photoresist 30 is applied on the entire surface and an opening C is formed in the resist corresponding to the fuse portion by ordinary mask exposure and development. After that, the barrier metal layer 28 in the opening C of the photoresist 30 and the metal layer of the plug electrode 29 which may remain in a small amount are removed by selective etching (FIG. 11A, step S45 to FIG. 13). S47). Even if the thickness of the barrier metal layer 28 is reduced, the cuttability of the fuse is improved, but the cuttability of the fuse is further improved by removing it by etching.

Next, as shown in FIG. 11B, the photoresist 30 is removed (step S48 in FIG. 13), and then, here, the uppermost main conductive metal layer 13A is formed.
After forming the antireflection layer 13a thereon, the fuse portion 13 is formed at the same time as the pad electrode (not shown) which is the external lead electrode by the usual lithography / etching method (step S49 in FIG. 13). At this time, the barrier metal layer 28 also includes the antireflection layer 13a and the main conductive metal layer 13
Etched into the same shape as A to form the barrier metal layer 13b. The main conductive metal layer 13A of the fuse portion 13 is mainly made of aluminum metal and aluminum-copper alloy,
On top of that, potassium fluoride (KrF: 248n), which is an exposure light source often used in a stepper for the purpose of microfabrication in order to facilitate microfabrication in the lithography process, is formed.
m) A commonly used titanium nitride (TiN) film or the like having a film thickness of about 10 to 50 nm is formed as an antireflection layer 13a for preventing reflection of light at the time of exposure such as laser or i-line (365 nm). Form.

Next, a plasma silicon nitride film (P-SiN) is formed to a film thickness of about 1 μm as the inorganic insulating protective film 14 (step S50 in FIG. 13). The inorganic insulating protective film 14 is not limited to the plasma silicon nitride film, but a commonly used silicon oxide film (SiO 2
Needless to say, it may be a single-layer film of _two films), a silicon oxynitride film (SiON film), a plasma silicon nitride film, or a multi-layer film combining them.

Next, a photoresist (not shown) is applied on the inorganic insulating protective film 14, the photoresist above the fuse portion 13 is opened, and the inorganic insulating protective film 20 in the opening A corresponding to the opening is usually formed. By etching about 0.1
The thickness is reduced to about 0.8 μm (FIG. 11 (c)). By thinning the inorganic insulating protective film 20, the fuse portion 13 can be stably and reliably blown and cut with a smaller laser energy than when the inorganic insulating protective film 20 has a large thickness.
Damage to the interlayer insulating film 26 and the like below the fuse portion 13 can be reduced. However, the fuse part 1
If the inorganic insulating protective film does not exist at all on the upper part of 3, the moisture-resistant protective film disappears, and the reliability tends to deteriorate.

After that, after opening (not shown) the inorganic insulating protective film 14 on the pad electrode (not shown) which is an external extraction electrode, a photosensitive polyimide film is applied / baked as the organic insulating protective film 15 to form an organic insulating protective film 15. The film is formed with a film thickness of 10 μm. An opening 16 on the fuse portion 13 and an opening (not shown) on a pad electrode (not shown) which is an external extraction electrode are formed by an exposure and development process and cured in a heat curing furnace (FIG. 12).

The adjustment of the film thickness of the inorganic insulating protective film 20 above the fuse portion 13 is not limited to the previous etching step, but after the organic insulating protective film 15 is opened and cured, it is further etched. Needless to say, the film thickness may be adjusted.

Further, in the present embodiment, the fuse portion 13
As an example of the case where is formed in the uppermost wiring layer,
In this case, as the steps after the formation of the inorganic insulating protective film 14, the steps described in the first embodiment and the second embodiment can be applied.

In the above, the case where the fuse portion 13 is formed of the uppermost wiring layer is illustrated, but when the fuse portion 13 is formed by using the wiring layer which is one layer below the uppermost layer, FIG. After the antireflection layer 13a, the fuse portion 13 and the barrier metal layer 13b are formed in a desired shape in the step of (1), an interlayer insulating film is formed, and then a wiring layer (uppermost layer) is formed. The inorganic insulating protective film 14 is formed. In this case, the inorganic insulating protective film 1 on the fuse portion 13 is selectively etched.
4 is completely removed and the interlayer insulating film is subsequently etched to reduce the thickness of the interlayer insulating film on the fuse portion 13 to 0.1 to 0.8.
Thin to μm. In this case, the configuration of the upper portion of the fuse portion 13 is similar to that in the case of FIG. The same applies to the case where the fuse portion 13 is formed by using the wiring layer which is two layers below the uppermost layer. In these cases, the etching time is longer than in the case of forming the uppermost wiring layer, and the variation in the film thickness of the interlayer insulating film on the fuse portion 13 after etching becomes large.

[ Fourth Embodiment ] FIGS. 14 and 15 are process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
FIG. 15B is a main part sectional view of the semiconductor integrated circuit device according to the present embodiment. In FIG. 15B, 11 is a semiconductor substrate, 24 and 41 are interlayer insulating films, and 13 is a main conductive metal layer. Fuse portion made of 13A, 14 an inorganic insulating protective film, 15 an organic insulating protective film, 16 an organic insulating protective film 15
, 20 is an inorganic insulating protective film on the fuse portion 13,
Reference numeral 40 is a barrier metal layer, 42 is a via hole, and 43 is a wiring groove.

In the semiconductor integrated circuit device of this embodiment, as shown in FIG. 15B, the fuse portion 13 and the pad electrode (see the figure) are formed by the uppermost wiring layer formed in the groove 43 of the interlayer insulating film 41. (Not shown) is shown as an example.
Forming a via hole 42 and a groove 43 in the interlayer insulating film 41,
A so-called dual damascene wiring structure is adopted. A barrier metal layer 40 is formed to improve the adhesiveness to the lower wiring and prevent punch-through. As the barrier metal layer 40, titanium nitride (TiN) or titanium (Ti)
In addition, a single-layer film and a multi-layer metal layer of a dense metal film such as tungsten nitride (WN) are formed with a film thickness of about 100 nm. After forming the barrier metal layer 40, the barrier metal under the fuse portion 13 is removed by selective etching, and then copper or the like is formed in the via hole 42 and the groove 43 by a commonly used method such as plating. Main conductive metal layer 13A
In addition, the inorganic insulating protective film 14 and the organic insulating protective film 15 are formed on the interlayer insulating film 41, and in the upper portion of the fuse portion 13, the inorganic insulating protective film 20 has a thinned area in the opening A. An opening 16 is formed in the organic insulating protective film 15.

The present embodiment is different from the third embodiment in that the wiring layer forming the fuse portion 13 has the above-mentioned dual damascene wiring structure and there is no antireflection layer on the main conductive metal layer 13A. The point is, as in the third embodiment,
Since the high melting point barrier metal layer 40 is not provided under the fuse portion 13, the fuse is more reliably cut. Although the case of the wiring fuse made of copper is illustrated, the present invention is not limited to this, and a buried wiring made of aluminum or another metal may be used. Needless to say, the fuse portion 13 is not limited to the uppermost wiring layer.

FIG. 16 is a process flow chart showing the manufacturing method in the present embodiment. Hereinafter, a method of manufacturing a main part will be described with reference to FIGS.

In FIG. 14A, the elements formed on the semiconductor substrate 11 are wired by the multilayer wiring layers (25 etc.) formed on the interlayer insulating film 24 and the plug metal (not shown). A groove for wiring is formed on the surface of the interlayer insulating film 24, the wiring layer 25 buried in the groove is formed, and then the next interlayer insulating film 41 is formed on the entire surface (step S6 in FIG. 16).
1).

Next, a via hole 42 is formed in the interlayer insulating film 41.
And a barrier metal layer 4 for forming a wiring groove 43 and improving adhesion to a lower wiring and preventing punch-through on the inner surface thereof.
0 (FIG. 14 (b), step S62 of FIG. 16,
S63). Here, as the barrier metal layer 40, a single-layer film or a multi-layer metal layer of a dense metal film such as titanium nitride (TiN), titanium (Ti), and tungsten nitride (WN) is formed with a thickness of about 100 nm. To do.

Next, a photoresist 30 is applied on the entire surface, and an opening C is formed in the resist in the area corresponding to the fuse portion by ordinary mask exposure and development. Then, the barrier metal layer 40 in the opening C of the photoresist 30 is removed by selective etching (FIG. 14 (c), steps S64 to S66 in FIG. 16). Here, even if the film thickness of the barrier metal layer 40 is reduced by etching, it does not matter since the cuttability of the fuse is improved, but it is removed as much as possible.

Next, after removing the photoresist 30,
The metal layer 13A for main conduction such as copper is formed in the via hole 42 and the groove 43 by a commonly used method such as plating.
At this time, the main conductive metal layer 13A is buried in the via hole 42 and the groove 43, and then planarized by using at least one of a chemical mechanical polishing technique and an etch back technique. As a result, the fuse portion 13 and the pad electrode (not shown) are formed. An inorganic insulating protective film 14 such as a plasma silicon nitride film is formed thereon (FIG. 1).
5 (a), steps S67 to S69 in FIG. 16).

After that, as in the third embodiment, the inorganic insulating protective film 20 on the fuse portion 13 is etched by about 0.1 to 0.8 μm in the area of the opening A by etching.
Then, the organic insulating protective film 15 made of polyimide or the like is formed, and the opening 16 of the organic insulating protective film 15 is formed on the fuse portion 13. The openings of the inorganic insulating protective film 20 and the organic insulating protective film 15 above the pad electrode (not shown) can be formed in the same manner as in the third embodiment.

In the third embodiment, the via hole 27 is used.
A plug electrode 29 made of a metal such as tungsten is formed on the step S44, and the main conductive metal layer 1 for the fuse is formed thereon.
3A is formed (step S49), the fourth
In the embodiment, the main conductive metal layer 13A for the fuse is used.
Are formed in both the via hole 42 and the groove 43 (step S68).

[ Fifth Embodiment ] The fifth embodiment can be applied to the above-described first to fourth embodiments, and only the main part thereof will be described here. 17 (a) and 17 (b) are plan views showing the arrangement of the main parts of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. In FIGS. 17 (a) and 17 (b), 100
Reference numerals 106 to 106 denote fuse wirings in which one electrically continuous fuse portion is formed, and D and E are thinned regions of the inorganic insulating protective film and openings of the organic insulating protective film. _{L 0, L 1, L '} 1, L 3, L' 3, L '' 3, L 5, L '5, L 6, L' 6, L '' 6 is a laser irradiation portion.

In FIG. 17 (a), conventionally, the fuse material of the fuse wiring 100 is melted and cut only by the laser irradiation portion L ₀ , and the fuse wiring 100 is electrically cut between both ends 0 and 0 '. . On the other hand, in the present embodiment, the fuse wiring 101 is electrically cut between the two ends 1 and 1'of the fuse wiring 101 at the two laser irradiation portions L ₁ and L ′ ₁ . In addition, the fuse wiring 103 is connected to the laser irradiation part.
L _3, L both ends 3 of the _'3, L''fuse wiring 103 at three locations ₃
It is an electrical cut between 3 and 3 '. The fuse wirings 102 and 104 are shown in a non-cut state.

As in this embodiment, by cutting one electrically continuous fuse portion at a plurality of points, the cutting resistance value at one location becomes serial, so that the cutting resistance value of the fuse can be increased. It is possible. Further, even if the disconnection is defective at one location, it is possible to disconnect at the other fuse disconnection portion, so that the disconnection can be ensured. That is, the cutting resistance value is a multiple of the cutting position, and the cutting accuracy (probability) is the product of the cutting probabilities at one position.

Further, with the structure shown in FIG. 17B, the fuse can be cut at high speed. In FIG. 17B, the two fuse wires 105 and 106 are
The laser irradiation parts L ₅ , L ′ ₅ and L ₆ , L ′ ₆ , L ″ ₆ are used to connect the electrical end portions 5 and 5 ′ of the fuse wiring 105 and the electrical end portions of the fuse wiring 106. 6 and 6'are cut off in circuit operation.

That is, two fuse wires 105 and 106 having fuse portions that can be cut at a plurality of locations are provided in one opening E, and their laser irradiation portions L ₅ , L' ₅ , L ₆ ,
All of L' ₆ and L'' ₆ are arranged on the line I-I'.
By arranging in this way, the laser feed of the laser processing equipment is usually realized by moving the wafer, but it is possible to irradiate the laser on a straight line, and the semiconductor substrate can be moved at high speed while moving without stopping. Can be cut. As a result, throughput can be improved, productivity can be improved, and TAT can be shortened.

In the above embodiment, the number of cut points in each of the fuse wirings 102 to 106 is two or three, but the number is not limited to this and may be plural. In addition, in FIG. 17 (b), one opening E
Although the case where the two fuse wirings 105 and 106 are provided is shown in the above, it goes without saying that the number may be three or more. However, although the cutting accuracy increases as the number of cutting points increases, the occupied area increases and the number of chips taken decreases due to the increase in area. That is, there is a trade-off relationship between the cutting accuracy and the number of chips taken, and the cutting point is determined by the relationship between the two.

Further, when the above-mentioned structure is applied to the third and fourth embodiments, the barrier metal layer is removed so that the barrier metal layer does not exist at least under the planned cutting portion (laser irradiation portion).

It is needless to say that even when the structure of this embodiment is applied to the conventional structure as shown in FIG. 22, the unique effect described in this embodiment can be obtained. Nor.

[ Sixth Embodiment ] This sixth embodiment is applied to the above-described first to fifth embodiments (however, the fuse portion is formed of the uppermost wiring layer). This is possible, and only the main part will be described here. FIG. 18 is a main part plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention. In FIG. 18, 31 is a fuse part, 32, 33,
34 is a metal wiring layer, 35 is a guard band, F is a thinned region of the inorganic insulating protective film, G is an opening of the organic insulating protective film, C
H1 to CH3 are contact hole portions between wiring layers.

In FIG. 18, the fuse portion 31 is formed of the uppermost wiring layer, and is electrically connected to the wiring layer 32 one layer below the uppermost layer by the plug metal in the contact hole portion CH1. The other of the fuse portions 31 is electrically connected to the wiring layer 34, which is one layer below the uppermost layer, via the plug metal in the contact hole CH2, and then the wiring layer 33.
To the contact hole CH3 via the plug metal. The wiring layer 33 may be the uppermost wiring, or may be a wiring layer lower than the uppermost layer by two or more layers. In addition, FIG.
In addition to the above configuration, both ends of the fuse part 31 may be changed to an electrical wiring layer using a single contact hole like the wiring layer 32, or contact holes may be used more than once like the wiring layer 33. Needless to say, the electric wiring layer may be changed. The size relationship between the thinned region F of the inorganic insulating protective film and the opening G of the organic insulating protective film is not particularly limited.

The guard band 35 is formed of a conductive layer. As the conductive layer, a wiring layer from the uppermost layer to the lowermost layer, a contact plug metal layer between wirings, a substrate portion and the like are used. The wiring layers and the like forming the guard band 35 are electrically connected to each other. Also, the guard band 35
Surrounds the contact holes CH1 to CH3 as shown in FIG. However, the wiring layers 32 and 33 for electrically extracting the fuse portion 31 are separated by a predetermined distance so as not to be electrically connected to the guard band 35. Therefore, if the portion of the guard band 35 that intersects with the lead-out wiring layers 32 and 33 is the same wiring layer as those, a portion that is not partially connected can be a very small portion.

According to the present embodiment, the guard band 35
Fuse wiring inside contact holes CH1 to CH
By reconnecting at 3, the path through which moisture and ionic components permeate from the cut portion (not shown) of the fuse portion 31 via the fuse wiring remaining after the cutting is extended, and the contact hole CH1 Since the plug metal embedded in to CH3 is a metal such as tungsten that does not corrode easily, the corrosion reaction can also be prevented by the plug metal part in the contact holes CH1 to CH3. Further, since the entire periphery of the contact holes CH1 to CH3 is surrounded by the guard band 35, it is possible to prevent moisture and ionic components from permeating inside the card band 35, and to the outside (semiconductor element portion) of the guard band 35. No water or ionic components come in,
It is possible to improve reliability. If the potential of the guard band 35 is also connected to the semiconductor substrate and is in the well,
The potential can be determined freely. That is, it goes without saying that positive, negative, and zero potentials can be set freely. In addition, although the case of the single guard band 35 is illustrated, the area increases, but by using the double or more guard band 35,
Positive and negative voltages may be applied and zero potential may be set to serve as traps for negative ions, positive ions, and water.

In the present embodiment, the fuse portion 31
Although both ends of the wiring are connected to the lower wiring layer by the contact holes CH1 to CH3 having the plug metal portion, only one end of the wiring of the fuse portion 31 is connected to the lower wiring layer by the contact hole. If you do this,
It is possible to prevent the corrosion reaction and the permeation of water and ionic components at one of the ends.

Further, even if the contact holes CH1 and CH2 at the end of the wiring of the fuse part 31 are not filled with the plug metal as in the fourth embodiment (see FIG. 15B), the contact holes are made of the plug metal. Although the effect of preventing corrosion cannot be obtained, the effect of providing the guard band 35 can be obtained.

Next, in the configurations of the first and second embodiments (see FIGS. 1 and 4), the fuse portion 13 is formed of at least the main conductive metal layer and the barrier metal layer formed thereunder. In such a case, preferable dimensions of each part will be described with reference to FIGS. 19 and 20.

FIG. 19 is a main sectional view for illustrating the dimensions of each part of the semiconductor integrated circuit device according to the embodiment of the present invention. In FIG. 19, 12 is an interlayer insulating film, 36 is a fuse portion, 37 is a barrier metal layer, 38 is an antireflection layer,
Reference numeral 39 is an inorganic insulating protective film. FIG. 20 is a diagram showing the relationship between the size of each part and the ease of cutting the fuse part by laser irradiation.

In FIG. 19, a fuse portion 36 formed of the uppermost wiring layer is formed on the interlayer insulating film 12, an inorganic insulating protective film 39 such as a plasma silicon nitride film is formed to a thickness of about 1 μm, and then a region including the fuse portion 36 is formed. The inorganic insulating protective film 39 is thinned by ordinary dry etching using the resist for opening the as a mask. Film thickness t _p1 of the upper portion of the inorganic insulating protective film 39 of the fuse unit 36, and the thickness of the sidewall of the inorganic insulating protective film 39 of the fuse portion 36 and t _p2, represented by relational expression t _p1 <t _p2.

This is because the normal dry etching of the inorganic insulating protective film 39 is anisotropic etching, and the horizontal etching speed is slower than the vertical etching speed. Is. This is the same as the principle of the method of forming the sidewall spacer of the gate electrode portion of the transistor of the LDD (Lightly Doped Drain) structure. On the other hand, since the wet etching is isotropic etching, the film thickness t _p2 of the inorganic insulating protective film 39 on the side wall of the fuse portion 36 is also substantially equal to the film thickness t _p1 of the inorganic insulating protective film 39 above the fuse portion. .

The easiness of cutting the fuse portion 36 Y (au) is t
It is desirable that _p1 is thin, and if evaluated under other conditions as shown in FIG. Further, the upper width W _FT and the lower width W _FB (≧ W _FT ) of the fuse portion 36
Is larger than about 1.0 μm, it becomes difficult to easily cut the fuse portion 36 (see FIG. 20 (b)). Further, when the film thickness t _F3 of the barrier metal layer 37 exceeds about 150 nm, the barrier metal or the like remains and the fuse cutability deteriorates (FIG. 20 (c)).
reference).

That is, the ease of cutting Y of the fuse portion 36 depends on the fact that the barrier metal layer 37 can be scattered, depending on the fact that the fuse is sealed with the inorganic insulating protective film 39 so that the explosion does not proceed until it is heated to a sufficiently high temperature by laser light. It depends. However, if the film thickness t _p1 of the inorganic insulating protective film 39 is too thick, the energy for exploding the fuse portion is also damaged in the direction of the interlayer insulating film 12 to cause cracks, so that no damage occurs. The upper limit of energy (about 800 nm) can be set (Fig. 20 (a)). The lower limit value is a set value including etching variations so that there is no fluctuation in the film thickness of the fuse portion 36 itself due to over-etching of the fuse portion 36.

[0123] the width W _FB of the fuse unit 36, since the possibility of the barrier metal layer 37 remains during large enough fuse cutting is high, as narrow well, for example, the thickness of the main conductive metal layer 36A made of an aluminum layer t _F2 Is about 500 nm, the upper limit of the width of the fuse portion 36 is about 1.0 μm, and the lower limit is the fine processing limit. This is because the barrier metal layer 13 below the fuse portion 13 in the third and fourth embodiments.
The same applies to the case where the thin films b and 40 (see FIG. 12, FIG. 15B, etc.) are not completely removed.

The film thickness t _F3 of the barrier metal layer 37 is preferably thin, but the lower limit value is determined by the barrier property at the contact portion and cannot be 0 nm at the contact portion. Therefore, the film thickness t _F3 of the barrier metal layer 37 is about 50 to 150 n.
m is desirable. However, it goes without saying that the barrier property is not limited to this.

There is also a case where a silicon dioxide film or the like (not shown) is thinly formed and patterned on the fuse portion 36 for fine processing of the fuse portion 36 and used as an etching mask for the fuse wiring layer. However, in this case, it can be considered that the film thickness of the silicon dioxide film or the like is added as the film thickness of the inorganic insulating protective film 39 on the fuse portion 36.

Further, the film thickness t _F1 of the antireflection layer 38 is a film thickness at which the effect of preventing the reflection of light with respect to the exposure light source can be obtained.
With a film thickness of 0 nm, there is no difference in cutting characteristics.

Further, as the laser used for cutting the fuse portion in the semiconductor integrated circuit device of the above embodiment,
For example YLF (yttrium-lithium-fluoride)
It is preferable that the laser light from the crystal is an infrared ray having a wavelength of 1047 to 1053 nm and a short pulse having a pulse width of about 2 to 10 nsec. In addition, YAG (yttrium-
Aluminum-Garnet) Short crystal wavelength 1064 nm
There are some infrared rays having a pulse width of about 40 nsec, but a pulse width shorter than 10 nsec tends to be advantageous for cutting the fuse portion of the metal wiring. This is because if the pulse width is too long, the base of the fuse portion is easily damaged.

In addition, as shown in FIG.
Is composed of, for example, an antireflection layer 38, a main conductive metal layer 36A, and a barrier metal layer 37, the main conductive metal layer 36A is made of an aluminum-based metal, and the antireflection layer 38 and the barrier metal layer 37 are titanium nitride films or When the fuse portion 36 is cut by using a titanium film or the like, the cutting yield can be increased by cutting the fuse portion 36 using a laser light source having two or more wavelength components. In this example, there are two types of so-called SDWL (Simultaneous dual wavelength) with which the oscillation wavelength of the laser light is 1340 nm and 1050 nm.
The processing yield can be increased by using a laser processing device using lasers).

This is 1340 nm for cutting the main conductive metal layer 36A composed of a metal mainly containing aluminum.
When the laser light having the wavelength is used, the heat absorption is high and it is possible to secure a large energy margin with respect to the silicon of the underlying semiconductor substrate. In addition, the antireflection layer 38 and the barrier metal layer 37 formed of a titanium nitride film or a titanium film are
It can be heat cut with infrared rays of 050 nm. That is, it is possible to perform laser processing on a multilayer film having different absorption characteristics. Since the laser energy margin can be increased, it is possible to further improve the processing yield by using this device for cutting the fuse.

Next, a method for evaluating the semiconductor integrated circuit device according to the embodiment of the present invention will be described. Here, a method for evaluating the above-described fuse easiness of cutting Y (see FIG. 20) will be described. 21 (a) and 21 (b) are a conceptual diagram and a characteristic diagram for explaining this evaluation method.

As shown in FIG. 21A, n, m, and h fuse parts 51 (n, m) formed on the semiconductor substrate are formed.
m and h are different numbers of 2 or more each) A sample having a fuse group connected in parallel is prepared. The fuse part 51 of these samples is a fuse part having the same structure as the semiconductor integrated circuit device to be evaluated, and the fuse parts 51 of each sample are connected by the wiring layer 52 forming the fuse part 51. Next, between the terminals (a-b,
The resistance value (a-d, a-c, b-d, etc.) is measured as an initial characteristic. Next, laser irradiation is performed on each sample in order to cut all the fuse parts, and thereafter, the resistance value between the terminals of the fuse group (between ab, ad, ac, bd, etc.) is measured again. It is measured as a characteristic after cutting. The easiness of cutting (cutting yield) Y is calculated from the results of the initial characteristics and the characteristics after cutting for each sample and plotted (FIG. 21 (b)). In FIG. 21B, the number of cuts is plotted on the horizontal axis (log scale), and the easiness of cutting (cutting yield) Y is plotted on the vertical axis (linear scale).

As the initial characteristics and the characteristics after cutting, resistance values between ab, ad, ac, bd, etc. were measured, but these are examples, and Conductivity confirmation of the other terminals b, c, d viewed from a is measured by the initial characteristic, and after cutting, the resistance value between a and b and between a and d and b-
Confirm the disconnection by the resistance value between c and ac to confirm the conductivity of the electrode.
And between b and d are required.

The method of calculating the easiness of cutting (cutting yield) Y from the results of the initial characteristics (characteristics before cutting) and the characteristics after cutting is, specifically, the resistance value before cutting and the resistance value after cutting. And determine that the resistance value before and after cutting has a change of a certain value or more, or that the resistance value after cutting is more than a certain resistance value. The easiness of cutting (cutting yield) Y is calculated by dividing the completed number by the total number of cutting processes. That is, the easiness of cutting (cutting yield) Y means the ratio of successful cutting.

In each sample, most of the fuse parts can be blown, so it is impossible to calculate the blow probability of each fuse. However, as shown in FIG. 21B, the number of parallel fuses is n, The m and h easiness of cutting Y lie on a straight line, and it becomes possible to accurately estimate and evaluate the easiness of cutting Y in the number applied (actually used) to an actual semiconductor integrated circuit device.

Here, three samples were used as the samples in the case where the number of parallel connections of the fuse portion was n, m, and h, but it is possible to use two or more samples. The larger the number of samples, the higher the accuracy of estimating the easiness of cutting Y in the number of actually used fuses.

Incidentally, conventionally, the resistance values at both ends of each fuse portion were measured after cutting, but the number of electrodes that can be arranged on the wafer was limited. Also, in order to measure on a wafer, the conductivity between the probe and the electrode must be reliable, and even if the probe deviates from the electrode, the resistance value increases, and even if it is not cut, it is mistakenly cut. There was a possibility to judge. Then, it was impossible to evaluate the cutting yield when the number of cuts in the cutting yield near 100% was increased.

[0137]

As described above, according to the present invention, the uppermost wiring layer is formed on the interlayer insulating film, and the inorganic insulating protective film and the organic insulating protective film are formed on the uppermost wiring layer. Since the fuse portion is formed by the layer and the opening portion may be provided in the organic insulating protective film as the opening portion above the fuse portion, the interlayer insulating film is formed to form the opening portion above the fuse portion as in the conventional case. Since it is not necessary to perform etching, it is possible to shorten the formation time of the opening and reduce the entire manufacturing time. Further, since only the inorganic insulating protective film is formed on the fuse portion, the fuse portion can be easily cut without increasing the irradiation energy of the laser beam, and the fuse portion can be cut to improve reliability. High reliability and high productivity can be realized without lowering the manufacturing yield and the manufacturing yield. Further, since the fuse part is covered with the inorganic insulating protective film, the moisture resistance can be improved.

Further, according to the present invention, the wiring layer forming the fuse portion is formed of the wiring layer having the barrier metal layer as the lower layer, and the fuse portion is constituted by the portion of the wiring layer where the barrier metal layer is removed or thinned. By doing so, it is possible to easily and surely cut the fuse portion, and it is possible to realize high reliability and high productivity without lowering reliability and manufacturing yield due to the cutting of the fuse portion. Also in this case, the moisture resistance can be improved by forming the fuse portion with the uppermost wiring layer and covering the fuse portion with the inorganic insulating protective film.

Further, by electrically cutting two or more locations in one electrically continuous fuse section by laser irradiation, the fuse section can be electrically cut more reliably. Further, by arranging the portions of the plurality of fuse portions that are blown by the laser irradiation on a straight line, the fuse portions can be electrically cut by the laser irradiation at a high speed, and the throughput and the productivity can be improved.

Further, by providing the guard band so as to surround the fuse portion and the contact hole to which the fuse portion is connected, it is possible to prevent the penetration of moisture and ionic components from the cut portion of the fuse portion inside the card band. You can
Water and ionic components do not come to the outside of the guard band (semiconductor element part), which contributes to improvement in reliability.

Further, the relationship between the fuse cutting yield and the number of fuse parts is obtained by using the sample, and the cutting yield in the number of actually used fuse parts of the semiconductor integrated circuit device can be accurately estimated from this relationship.

[Brief description of drawings]

FIG. 1 is a main part cross-sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the invention.

FIG. 3 is a flowchart showing a method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 4 is a main part cross-sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 6 is a process sectional view showing a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 8 is a plan view and a cross-sectional view of a main portion of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 9 is a partial partial cross-sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 10 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 11 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 12 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 13 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 14 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit device in the fourth embodiment of the present invention.

FIG. 15 is a process sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

FIG. 16 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 17 is a plan view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 18 is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 19 is a cross-sectional view for explaining preferable dimensions of each part of the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 20 is a diagram showing the relationship between the dimensions of each part of the semiconductor integrated circuit device and the ease of cutting the fuse part in the embodiment of the present invention.

FIG. 21 is a diagram for explaining a method for evaluating a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 22 is a partial cross-sectional view of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

11 Semiconductor substrate 12 Interlayer insulation film 13 Fuse part 14 Inorganic insulating protective film 15 Organic insulating protective film 16 openings 17 Pad electrode 18 openings 19 opening 20 Inorganic insulation protective film on fuse part

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/8222 H01L 27/04 G06F 17/50 H01L 21/3205

Claims (25)

(57) [Claims] 1. An uppermost wiring layer formed on an interlayer insulating film formed on a semiconductor substrate, an inorganic insulating protective film formed on the uppermost wiring layer and the interlayer insulating film,
A semiconductor integrated circuit device having an organic insulating protective film formed on the inorganic insulating protective film, comprising: a fuse part formed of the uppermost wiring layer formed on the interlayer insulating film; And an opening of the organic insulating protective film provided on the upper part of the semiconductor integrated circuit device, wherein the wiring layer of the fuse part has at least a metal layer for main conduction. 2. An external lead electrode formed of an uppermost wiring layer formed on an interlayer insulating film, an opening of an inorganic insulating protective film and an opening of an organic insulating protective film provided on the external lead electrode. The semiconductor integrated circuit device according to claim 1, further comprising: 3. The semiconductor integrated circuit device according to claim 1, wherein the upper portion of the fuse portion of the inorganic insulating protective film exposed in the opening of the organic insulating protective film is etched to be thinned. 4. A step of forming a fuse portion composed of an uppermost wiring layer on an interlayer insulating film formed on a semiconductor substrate, and an inorganic insulating protective film on the uppermost wiring layer and the interlayer insulating film. A step of forming an inorganic insulating protective film, a step of forming an organic insulating protective film over the entire surface, and a step of forming an opening of the organic insulating protective film above the fuse portion, The method of manufacturing a semiconductor integrated circuit device, wherein the wiring layer of the fuse portion has at least a metal layer for main conduction. 5. A step of forming a fuse portion composed of an uppermost wiring layer and an external extraction electrode on an interlayer insulating film formed on a semiconductor substrate, and forming a fuse portion and an external lead electrode on the uppermost wiring layer and the interlayer insulating film. A step of forming an inorganic insulating protective film, a step of selectively etching the inorganic insulating protective film to form an opening in the upper portion of the external extraction electrode, and after forming the opening of the inorganic insulating protective film, over the entire surface A step of forming an organic insulating protective film; and a step of forming an opening of the organic insulating protective film above the fuse portion and above the external extraction electrode, wherein the wiring layer of the fuse portion is at least the main conductive layer. A method of manufacturing a semiconductor integrated circuit device, comprising a metal layer for use in a semiconductor device. 6. The method according to claim 4, further comprising the step of forming an opening of the organic insulating protective film and then etching the portion of the inorganic insulating protective film exposed in the opening to reduce the thickness. Manufacturing method of semiconductor integrated circuit device. 7. A step of forming a fuse portion composed of an uppermost wiring layer and an external lead electrode on an interlayer insulating film formed on a semiconductor substrate, and forming a fuse portion and an external lead electrode on the uppermost wiring layer and the interlayer insulating film. Forming an inorganic insulating protective film, forming a first photoresist on the entire surface after forming the inorganic insulating protective film, and forming an opening of the first photoresist at least above the fuse portion And a step of thinning the portion of the inorganic insulating protective film exposed in the opening of the first photoresist by etching, and after thinning the inorganic insulating protective film, the first photoresist is removed. A step of removing, a step of forming a second photoresist over the entire surface after removing the first photoresist, and an opening of the second photoresist above the external extraction electrode. And a step of forming an opening of the inorganic insulating protective film on the external extraction electrode by etching away the inorganic insulating protective film in a portion exposed in the opening of the second photoresist, Removing the second photoresist after forming the opening of the inorganic insulating protective film; forming an organic insulating protective film over the entire surface after removing the second photoresist; And a step of forming an opening of the organic insulating protective film on the external extraction electrode, the method of manufacturing a semiconductor integrated circuit device. 8. A semiconductor integrated circuit device having a multilayer wiring structure including one wiring layer forming a fuse part, wherein an insulating film above the fuse part is thinned, wherein the fuse part is formed. One wiring layer is formed on the interlayer insulating film and is composed of a wiring layer having a barrier metal layer as a lower layer,
A semiconductor integrated circuit device, wherein the fuse portion is formed by a portion of the one wiring layer where the barrier metal layer is removed or thinned. 9. The semiconductor integrated circuit device according to claim 8, wherein the one wiring layer forming the fuse portion is embedded in a groove formed on the surface of the interlayer insulating film. 10. The one wiring layer forming the fuse portion is an uppermost wiring layer, and the thinned insulating film above the fuse portion is an inorganic insulating protective film. 8. The semiconductor integrated circuit device according to 8 or 9. 11. A method of manufacturing a semiconductor integrated circuit device having a multilayer wiring structure including one wiring layer forming a fuse portion, wherein an insulating film above the fuse portion is thinned, the method comprising: A step of forming a barrier metal layer on the interlayer insulating film formed in step 5, a step of applying a photoresist on the barrier metal layer, and a step of forming an opening of the photoresist in a region corresponding to at least a fuse part. A step of removing or thinning the portion of the barrier metal layer exposed in the opening of the photoresist by etching, a step of removing or thinning the barrier metal layer, and then removing the photoresist, After removing the photoresist, forming a metal layer for main conduction, and etching the metal layer for main conduction and the barrier metal layer into a desired shape. A step of forming the fuse part including the main conductive metal layer and forming the one wiring layer including the main conductive metal layer and the barrier metal layer. Production method. 12. A method of manufacturing a semiconductor integrated circuit device having a multilayer wiring structure including one wiring layer forming a fuse portion, wherein an insulating film on the upper portion of the fuse portion is thinned, the method comprising: Forming a groove on the interlayer insulating film formed on the barrier metal layer, forming a barrier metal layer on the inner surface of the groove, applying a photoresist on the barrier metal layer, and forming the groove on the photoresist layer at least in a region corresponding to the fuse portion. A step of forming an opening of the photoresist, a step of removing or thinning the portion of the barrier metal layer exposed in the opening of the photoresist by etching, and a step of removing or thinning the barrier metal layer, A step of removing a photoresist; and, after removing the photoresist, embedding a metal layer for main conduction in the groove to thereby include the metal layer for main conduction. And a wiring layer formed of the main conductive metal layer and the barrier metal layer. 13. The one wiring layer forming the fuse portion is an uppermost wiring layer, and the thinned insulating film above the fuse portion is an inorganic insulating protective film. 13. The method for manufacturing a semiconductor integrated circuit device according to 11 or 12. 14. The semiconductor integrated circuit device according to claim 1, wherein two or more fuse portions electrically connected to each other are blown by laser irradiation. 15. The semiconductor integrated circuit device according to claim 14, wherein a plurality of fuse portions are provided, and portions of the plurality of fuse portions that are blown by laser irradiation are arranged on a straight line. 16. A fuse portion formed of the uppermost wiring layer is connected to at least one end portion of the fuse portion to a lower wiring layer through a contact hole, and a conductive layer is formed so as to surround the fuse portion and the contact hole. A guard band consisting of:
Alternatively, the semiconductor integrated circuit device according to item 15. 17. A semiconductor integrated circuit device according to claim 1, wherein the wiring width of the laser cutting portion of the fuse portion is 1.0 μm or less. 18. The wiring layer of the fuse part comprises a main conductive metal layer and a barrier metal layer formed thereunder, and the film thickness of the barrier metal layer at least below the laser cutting part of the fuse part is 150 nm. The semiconductor integrated circuit device according to claim 1, 2, 3, 10, 14, 15, 16 or 17, wherein: 19. The wavelength ranges from 1047 nm to 1053 nm.
5. The method according to claim 4, further comprising the step of cutting the fuse part by irradiating the fuse part with laser light from a YLF crystal having a pulse width of 2 to 10 ns.
15. A method for manufacturing a semiconductor integrated circuit device according to 5, 6, 7, 11, 12 or 13. 20. A step of cutting the fuse part by using a laser light source having a wavelength component of at least 2 or more, wherein a wiring layer of the fuse part is composed of a main conductive metal layer and a barrier metal layer formed thereunder. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 4, 5, 6, 7, 11, 12, or 13. 21. The method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein the laser light source has a wavelength component around 1340 nm and a wavelength component around 1050 nm. 22. A step of preparing a plurality of samples having a fuse group in which two or more different numbers of fuse parts are connected in parallel on a semiconductor substrate, and a first step of measuring resistance values at both ends of the fuse group for each sample. For each sample, a measurement step, a step of irradiating each sample with laser light to cut all the fuse parts, a second measurement step for measuring the resistance value of both ends of the fuse group after the laser irradiation for each sample, and each sample In the step of calculating the fuse cutting yield from the results of the first and second measurement steps, and the relationship between the fuse cutting yield calculated for each sample and the number of fuse sections, the number of fuse sections actually used in the semiconductor integrated circuit device A method of evaluating a semiconductor integrated circuit device, the method comprising: estimating a cutting yield. 23. The wiring layer of the fuse portion is composed of a main conductive metal layer and a barrier metal layer formed below the main conductive metal layer.
Or the semiconductor integrated circuit device according to item 17. 24. The at least one end of the fuse portion formed of the uppermost wiring layer is connected to the lower wiring layer via a contact hole.
2. A semiconductor integrated circuit device according to 2, 3, 10, 14, 15, 17, 23. 25. An uppermost wiring layer formed on an interlayer insulating film formed on a semiconductor substrate, an inorganic insulating protective film formed on the uppermost wiring layer and the interlayer insulating film, A semiconductor integrated circuit device having an organic insulating protective film formed on the inorganic insulating protective film, comprising: a fuse part formed of the uppermost wiring layer formed on the interlayer insulating film; And an opening of the organic insulating protective film provided on the upper part of the wiring layer, and the wiring layer of the fuse portion is at least a metal layer for main conduction.
The semiconductor integrated circuit device according to claim 1, wherein the inorganic insulating protective film exposed in the opening of the organic insulating protective film is etched to be thinned.