KR20070002738A - Method for manufacturing a semiconductor apparatus - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to compensate a fuse pattern for an electrical opening state and to restrain the generation of electrical failure in the device by connecting electrically the fuse pattern with a bit line through a contact plug. A plurality of conductive layers are formed on a substrate(110). A first interlayer dielectric(116) with first contact plugs(118) for contacting the conductive layers is formed on the resultant structure. A fuse pattern(120) for being connected with the first contact plug is formed on the first interlayer dielectric. A window layer(122) with a second contact plug(124) for being connected with the fuse pattern is formed on the resultant structure. A metal line(126) is formed on the window layer to contact the second contact plug. A passivation layer(136) for covering the metal line is formed thereon. A fuse box for exposing partially the fuse pattern is formed on the resultant structure by etching selectively the passivation layer and the window layer.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING A SEMICONDUCTOR APPARATUS}

1 is a plan view illustrating a semiconductor device using a metal wiring connected to an upper electrode of a capacitor as a fuse pattern.

2 and 3 are process cross-sectional views taken along the line II ′ shown in FIG. 1.

Figure 4 is a SEM (Scanning Electron Microscope) photograph showing the problem of cracks (see 'C' region) generation according to the prior art.

5 to 7 are process cross-sectional views illustrating a manufacturing process of a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

110: semiconductor substrate

112, 116, 128, 134: interlayer insulating film

114: bit line

118, 124, 130: contact plug

120: fuse pattern

122: window curtain

126, 132: metal wiring

136: passivation film

138: PIQ layer

FB: Fuse Box

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a fuse pattern of a semiconductor device that is cut by irradiation of a laser beam when a defective cell is repaired.

In general, fabrication of a semiconductor device is a FABrication (FAB) process of forming cells having integrated circuits by repeatedly forming circuit patterns set on a silicon substrate. A packaging process includes packaging the substrate on which the cells are formed, in a chip unit. In addition, an electrical die sorting (hereinafter referred to as EDS) is performed between the fabrication process and the packaging process to detect the defective cells by inspecting the electrical characteristics of the cells formed on the substrate.

The EDS process is a process of determining whether the cells formed on the substrate have an electrically good state or a bad state. The EDS process eliminates defective cells before performing the packaging process, thereby reducing the effort and cost of the packaging process. Then, the cells having a bad state are found early and reproduced through the repair. Therefore, the EDS process examines cells to select defective cells, generates a pre-laser test to generate the data, a repair process to repair the repairable cells based on the data, and the repaired cell. They consist of a post-laser test that retests them. In the EDS process, a repair process is a process of cutting a wire connected to a defective cell by irradiating a laser beam and replacing the redundancy cell embedded in the chip. Here, the wiring cut by the irradiation of the laser beam is called a fuse pattern, and the cut sheet is called a fuse box. As a result, as the laser is irradiated through the fuse box, the lower fuse pattern is cut off. A plurality of insulating films, that is, window films, are formed on the fuse pattern to protect the fuse pattern and define the fuse area.

Known techniques for fuse patterns are disclosed in US Pat. No. 6,100,117 issued to Hal et al. And US Pat. No. 6,180,503 issued to Tzeng et al.

According to the disclosed patents, a bit line of a semiconductor device is used as a fuse pattern. That is, when the bit line is formed, the extended bit line may be used as the fuse pattern by extending the bit line to the fuse region where the fuse pattern is to be formed.

However, when the bit line is used as a fuse pattern, it is not easy to open the fuse region in which the fuse pattern is formed. This is because an insulating film, a metal wiring, and the like having a multilayer structure are formed on the bit line. That is, the depth for opening the fuse area is deep. And, since the time required for etching for opening the fuse region is extended, productivity is reduced. This is because the thickness of the window film on the fuse pattern cannot be properly adjusted when opening the fuse area.

Accordingly, recently, there has been a trend to use a metal wiring for connecting the upper electrode or the contact of the capacitor formed on the bit line instead of the bit line as a fuse pattern.

2 and 3 are process cross-sectional views illustrating a semiconductor device manufacturing process using a metal wiring connecting the upper electrode of a capacitor as a fuse pattern according to the related art. 2 and 3 illustrate a cut along the line II ′ of FIG. 1. Referring to FIG. 1, the fuse pattern 14 is a guard ring layer for preventing moisture from penetrating into an area outside the fuse box. You can see that it is surrounded by (GL: Guardring Layer).

First, as shown in FIG. 2, a first interlayer dielectric (ILD) 12 is deposited on the substrate 10 where the word line and bit line forming processes are completed according to a conventional DRAM manufacturing process.

Subsequently, after forming the lower electrode (not shown) and the dielectric film (not shown) of the capacitor, polysilicon is deposited to form the upper electrode. Then, the pattern is patterned into a predetermined upper electrode pattern (not shown) and the fuse pattern 14 through a photolithography process.

Subsequently, a window film 16 is formed on the entire structure including the fuse pattern 14 via the contact plug 18 electrically connected to the fuse pattern 14. In this case, the window layer 16 may be formed of a single layer or a stack of an oxide-based material.

Subsequently, a metal material is deposited on the window layer 16 including the contact plug 18, and then patterned to form the metal wiring 20. Thereafter, a second interlayer insulating film 22 is formed on the metal wiring 20 so as to cover the metal wiring 20 through the contact plug 24 electrically connected to the metal wiring 20. In this case, the second interlayer insulating layer 22 may be formed of a single layer or a stack of an oxide-based material like the window layer 16.

Subsequently, the final metal wiring 26 connected to the contact plug 24 is patterned on the second interlayer insulating layer 22 including the contact plug 24.

Subsequently, as shown in FIG. 3, after the deposition of the third interlayer insulating film 28 covering the metal wiring 26, the passivation for protecting the final metal wiring 26 on the third interlayer insulating film 28 is performed. A nitride film is deposited as the pasivation film 30. Thereafter, a polyisode droinorazinindione (PIQ) layer 32 is formed on the nitride film to protect the chip.

Subsequently, the fuse box FB which sequentially opens the fuse pattern 14 by etching the PIQ layer 32, the passivation film 30, the third and second interlayer insulating films, and the window films 28, 22, and 16 sequentially. Form.

However, according to the related art, a crack (see 'C' region) occurs in a corner area of the bottom of the fuse box FB during a molding operation to be performed subsequently. Detailed description thereof will be made with reference to FIG. 4.

Referring to (a) of FIG. 4, a problem occurs in that a guard region in which a guard ring layer is formed is damaged by an external force during a milling process during molding. Able to know. In addition, referring to FIG. 4B, it can be seen that cracks (see 'C' region) are also generated in a part of the fuse pattern 14 due to such guard damage (see 'D' region).

As such, as a crack occurs in the fuse pattern 14, electrical failure of the semiconductor device increases.

Accordingly, the present invention has been made to solve the above problems of the prior art, to provide a semiconductor device manufacturing method that can suppress the increase in electrical failure of the semiconductor device due to cracks when forming the fuse pattern of the semiconductor device. The purpose is.

According to an aspect of the present invention, there is provided a substrate including a plurality of conductive layers, and a plurality of first layers connected to the conductive layer on an entire structure including the plurality of conductive layers. Forming a first interlayer insulating film through a contact plug, forming a fuse pattern connected to the first contact plug on the first interlayer insulating film, and forming a first fuse layer connected to the fuse pattern on the fuse pattern; Forming a window film via a second contact plug; forming a metal wiring connected to the second contact plug on the window film; depositing a passivation film to cover the metal wiring; and forming a passivation film. And forming a fuse box to expose a portion of the fuse pattern by etching the window layer. The.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

5 to 7 are process cross-sectional views illustrating a semiconductor device manufacturing process in accordance with a preferred embodiment of the present invention. For convenience of description, the cell region in which the cell is to be formed is not illustrated, but only the peri region in which a driving circuit and a fuse pattern are formed, which are formed of a plurality of transistors for driving the cell, are shown.

First, as shown in FIG. 5, an interlayer insulating film 112 (hereinafter, referred to as a first interlayer insulating film) is deposited on the substrate 110 on which an isolation process and a word line forming process are completed. .

Subsequently, a conductive layer is deposited on the first interlayer insulating layer 112, and then patterned to form a bit line 114. Then, an interlayer insulating film (hereinafter referred to as a second interlayer insulating film) 116 is deposited to cover the bit line 114. In this case, the second interlayer dielectric layer (IMD: 116) is formed of an oxide-based material. For example, HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate Glass) film, FSG (FSG) film It is formed from a single layer film made of any one of a fluorinated Silicate glass (CDO) film, a carbon doped oxide (CDO) film, and an organosilicate glass (OSG) film, or they are formed as a laminated film in which at least two or more layers are laminated.

Subsequently, a photolithography process is performed to form a plurality of contact holes (not shown) exposing a part of the bit line 114 in the second interlayer insulating layer 116, and then a plug material such as polysilicon to fill the contact holes. Deposit.

Subsequently, an etch-back or chemical mechanical polishing (CMP) process is performed to form a contact plug 118 (hereinafter referred to as a first contact plug) that is only embedded in the contact hole.

Subsequently, a fuse pattern 120 is formed on the second interlayer insulating layer 116 including the first contact plug 118 to be connected to the first contact plug 118. At this time, the fuse pattern 120 is patterned together in the patterning process for forming the upper electrode of the capacitor in the cell region not shown.

Subsequently, the window film 122 is deposited on the fuse pattern 120 to protect the fuse pattern 120. In this case, the window film 122 is formed of an oxide-based material like the first and second interlayer insulating films 112 and 116.

Subsequently, a plurality of contact holes (not shown) are formed in the window film 122 by performing a photolithography process, and then a plug material such as polysilicon is deposited to fill the contact holes.

Subsequently, an etch back or CMP process is performed to form a contact plug 124 (hereinafter referred to as a second contact plug) that is only embedded in the contact hole.

Subsequently, the metal wiring 126 (hereinafter referred to as a first metal wiring) is patterned by depositing a metal material on the window film 122 including the second contact plug 124 and then performing a photolithography process.

Next, as shown in FIG. 6, a third interlayer insulating film (IMD) 128 is deposited on the window film 122 to cover the first metal wiring 126. In this case, the third interlayer insulating film 128 is formed of a single layer or a stack of the same oxide film-based material as the second interlayer insulating film 116.

Subsequently, a plurality of contact holes (not shown) are formed in the third interlayer insulating layer 128 by performing a photolithography process, and then a plug material such as polysilicon is deposited to fill the contact holes.

Subsequently, an etch back or CMP process is performed to form a contact plug 130 (hereinafter, referred to as a third contact plug) that is only embedded in the contact hole.

Subsequently, the metal wiring 132 (hereinafter referred to as a second metal wiring) is patterned by depositing a metal material on the third interlayer insulating layer 128 including the third contact plug 130 and then performing a photolithography process. .

Subsequently, as illustrated in FIG. 7, a fourth interlayer dielectric layer ILD 134 is deposited on the third interlayer dielectric layer 128 to cover the second metal interconnection 132 with the same material. Then, the passivation film 136 of the nitride film series is deposited to protect the second metal wiring 132 and the chip, which are the final metal wiring.

Next, a PIQ layer 138 is deposited on the passivation film 136 to protect the chip.

Next, a photolithography process is performed to etch the PIQ layer 138, the passivation film 136, the fourth interlayer insulating film 134, the third interlayer insulating film 128, and the window film 122. As a result, a fuse box FB exposing a part of the fuse pattern 120 is formed.

Subsequently, when the molding operation is performed, cracks (see 'C' region) are generated in the corner region of the bottom of the fuse box FB. However, according to a preferred embodiment of the present invention, even if such a crack (see 'C' region) occurs, the electrical failure of the semiconductor device does not occur. This is because the fuse pattern 120 is electrically connected to the bit line 114 and the first contact plug 118 so that the fuse pattern 120 is damaged and electrically opened by a crack (see 'C' region). Because you can compensate for that.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the fuse pattern is formed to be electrically connected to the bit line through the contact plug when the fuse pattern is formed in the semiconductor device, thereby compensating that the fuse pattern is damaged and opened due to crack generation. can do. Therefore, the electrical failure of the semiconductor device can be suppressed to increase the package yield.

Claims (6)

Providing a substrate having a plurality of conductive layers formed thereon; Forming a first interlayer insulating film on the entire structure including the plurality of conductive layers via a plurality of first contact plugs connected to the conductive layer; Forming a fuse pattern connected to the first contact plug on the first interlayer insulating layer; Forming a window layer on the fuse pattern, the window layer having a second contact plug connected to the fuse pattern; Forming a metal wire connected to the second contact plug on the window layer; Depositing a passivation film to cover the metal wiring; And Etching the passivation layer and the window layer to form a fuse box exposing a portion of the fuse pattern; Semiconductor device manufacturing method comprising a. The method of claim 1, And the conductive layer is formed at the same time during the bit line forming process. The method of claim 1, The fuse pattern is formed at the same time during the upper electrode forming process of the capacitor. The method according to any one of claims 1 to 3, And said passivation film is formed of a nitride film. The method of claim 4, wherein And depositing a PIQ layer on the passivation film after depositing the passivation film. The method of any one of claims 1 to 3, wherein the forming of the metal wiring, Forming a first metal wire connected to the second contact plug on the window layer; Forming a second interlayer insulating film through a third contact plug connected to the first metal wiring; And Forming a second metal wire connected to the third contact plug on the second interlayer insulating layer; Semiconductor device manufacturing method comprising a.

Images