KR20030048870A - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR20030048870A KR20030048870A KR1020010078915A KR20010078915A KR20030048870A KR 20030048870 A KR20030048870 A KR 20030048870A KR 1020010078915 A KR1020010078915 A KR 1020010078915A KR 20010078915 A KR20010078915 A KR 20010078915A KR 20030048870 A KR20030048870 A KR 20030048870A
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- Prior art keywords
- fuse
- layer
- protective
- film
- pad
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- 239000004065 semiconductor Substances 0.000 title abstract description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 62
- 229920001721 polyimide Polymers 0.000 claims abstract description 39
- 239000004642 Polyimide Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract 3
- 230000001681 protective effect Effects 0.000 claims description 42
- 230000004888 barrier function Effects 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000000926 separation method Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000010030 laminating Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 장치 제조 방법에 관한 것으로, 보다 상세하게는 반도체 장치 제조 공정의 마무리 공정에 해당하는 퓨즈, 패드, 보호막 공정을 간소화할 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for simplifying a fuse, pad, and protective film process corresponding to a finishing step of a semiconductor device manufacturing process.
반도체 장치 제조에 있어서, 완성된 반도체 장치 불량시 간단한 수선을 통해 여분으로 형성한 가외 회로 부분을 사용할 수 있도록 혹은 직류 전압 조정을 위해 퓨즈 사용이 일반화되고 있다. 기존의 메모리 제품이나 논리 회로 제품에서는 최상부 배선층의 베리어 메탈을 퓨즈로 사용하거나, 비트라인을 퓨즈로 사용하는 경우가 많다.BACKGROUND OF THE INVENTION In the manufacture of semiconductor devices, the use of fuses for the use of extra-circuit portions formed by simple repairs in the event of a defective semiconductor device or for adjusting the DC voltage has become common. In conventional memory or logic circuit products, the barrier metal of the uppermost wiring layer is often used as a fuse, or the bit line is used as a fuse.
그러나, 소자 고집적화에 따라 디자인 룰이 엄격해지고 장치 구조가 복잡해질수록 비트라인 이후에 적층되는 배선층 수가 늘어난다. 따라서, 비트라인을 퓨즈로 사용하는 제품에서는 퓨즈 형성을 위해 비트라인층까지 장치의 많은 상부층들을 식각 제거해야 하므로 퓨즈 형성의 어려움이 증가한다.However, as device integration increases, the stricter the design rule and the more complicated the device structure, the more wiring layers to be stacked after the bit line. Therefore, in the case of using a bit line as a fuse, the difficulty of fuse formation is increased because many upper layers of the device must be etched out to the bit line layer to form a fuse.
이하 도1 내지 도5는 종래 최상 배선층의 하부 베리어 메탈층을 퓨즈로 사용하는 공정 각 단계를 나타내는 공정 단면도들이다.1 to 5 are cross-sectional views illustrating each step of a process of using a lower barrier metal layer of a conventional uppermost wiring layer as a fuse.
도1을 참조하면, 기판(10)에 층간 절연막(20)이 적층된 상태에서 최상 배선층이 형성된다. 최상 배선층은 하부 베리어막(30)으로 티타늄/티타늄 질화막이 수백 옹스트롬 적층된 뒤, 알미늄층(40) 수천 옹스트롬, 상부 베리어막(50)으로 티타늄 질화막이 수백 옹스트롬 적층되어 형성될 수 있다. 최상 배선층을 패터닝하여 퓨즈 영역과 패드 영역에 최상 배선 패턴을 형성한다. 최상 배선 패턴 위로 실리콘 산화막(60)과 제1 보호막(65)으로서 실리콘 질화막이 콘포말하게 형성된다.Referring to FIG. 1, an uppermost wiring layer is formed in a state in which an interlayer insulating film 20 is stacked on a substrate 10. The uppermost wiring layer may be formed by stacking several hundred angstroms of titanium / titanium nitride film into the lower barrier film 30, and then stacking several hundred angstroms of the aluminum layer 40 and several hundred angstroms of titanium nitride into the upper barrier film 50. The uppermost wiring layer is patterned to form the uppermost wiring pattern in the fuse region and the pad region. A silicon nitride film is conformally formed as the silicon oxide film 60 and the first passivation film 65 over the uppermost wiring pattern.
도1 및 도2를 참조하면, 노광 공정을 통해 패드 영역을 포토레지스트(미도시)로 덮은 상태에서 퓨즈 영역에 대한 전면 이방성 식각을 통해 배선 패턴 측벽에 실리콘 산화막과 제1 보호막으로 이루어진 스페이서(66,61)를 형성한다. 과식각을 통해 층간 절연막(20)이 일부 두께 제거될 수 있다. 이때 퓨즈 영역의 배선 패턴 위쪽의 상부 베리어막(50)은 제거된다. 이어서, 포토레지스트를 제거하고 알미늄층(40)에 대한 식각을 통해 하부 베리어막(30)으로 이루어진 퓨즈만 남도록 한다.1 and 2, a spacer 66 including a silicon oxide film and a first passivation layer on a sidewall of a wiring pattern through full anisotropic etching of a fuse region in a state in which a pad region is covered with a photoresist (not shown) through an exposure process. , 61). The thickness of the interlayer insulating layer 20 may be removed through overetching. At this time, the upper barrier film 50 above the wiring pattern of the fuse region is removed. Subsequently, the photoresist is removed and only the fuse made of the lower barrier layer 30 is left by etching the aluminum layer 40.
도3 및 도4를 참조하면, 기판 전면에 제2 보호막(70)으로서 실리콘 질화막을 콘포말하게 적층한다. 이어서, 패드 영역을 드러내는 포토레지스트 패턴(미도시)을형성하고 제1,2 보호막(79,65)과 실리콘 산화막(60)에 대한 식각을 실시하여 최상 배선 패턴으로 이루어진 패드를 드러낸다. 이때 배선 패턴의 상부 베리어막(50)은 제거될 수 있다. 이어서, 포토레지스트 패턴을 제거한다.3 and 4, a silicon nitride film is conformally laminated as the second protective film 70 on the entire substrate. Subsequently, a photoresist pattern (not shown) exposing the pad region is formed, and the first and second passivation layers 79 and 65 and the silicon oxide layer 60 are etched to expose the pads having the best wiring patterns. In this case, the upper barrier layer 50 of the wiring pattern may be removed. Next, the photoresist pattern is removed.
도5를 참조하면, 기판 전면에 보호용 폴리이미드(polyimide)막을 적층하고, 패터닝 과정을 통해 퓨즈 및 패드를 드러내는 폴리이미드 패턴(91)을 형성한다. 이때, 통상적으로 폴리이미드는 비감광성이므로 폴리이미드 패턴(91) 형성을 위해서는 노광 및 식각 공정이 더 필요하다.Referring to FIG. 5, a protective polyimide film is stacked on the entire surface of a substrate, and a polyimide pattern 91 exposing a fuse and a pad is formed through a patterning process. At this time, since the polyimide is generally non-photosensitive, an exposure and etching process is further required to form the polyimide pattern 91.
이상과 같이 최상 배선층의 하부 베리어 메탈층을 퓨즈로 사용할 경우, 퓨즈와 패드 형성을 위해 별도의 노광 공정이 필요하다. 그리고, 패드 위로 형성되는 폴리이미드 보호막(passivation layer)에서 패드 및 퓨즈를 드러내기 위해 노광 및 식각이 계속되면, 공정의 복잡화는 가중되게 된다. 더욱이, 퓨즈 및 패드와 관련한 구조상의 문제점으로 패키지 공정에서 크랙을 유발할 위험이 높다.As described above, when the lower barrier metal layer of the uppermost wiring layer is used as a fuse, a separate exposure process is required to form the fuse and the pad. And, if exposure and etching continue to reveal the pads and fuses in a polyimide passivation layer formed over the pads, the complexity of the process is increased. Moreover, structural problems associated with fuses and pads present a high risk of causing cracks in the packaging process.
본 발명은 상술한 종래 반도체 장치 형성 공정의 문제점을 완화시키기 위한 것으로, 반도체 장치의 퓨즈 형성, 패드 형성 및 보호막 형성을 연관시켜 공정을 단순화할 수 있는 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention aims to alleviate the above problems of the conventional semiconductor device forming process, and an object thereof is to provide a method that can simplify the process by incorporating fuse formation, pad formation, and protective film formation of a semiconductor device.
본 발명은 또한, 퓨즈 형성 및 운용의 신뢰성을 높일 수 있는 반도체 장치 제조 방법을 제공하는 것을 목적으로 한다.Another object of the present invention is to provide a method for manufacturing a semiconductor device which can improve the reliability of fuse formation and operation.
도1 내지 도5는 종래 최상 배선층의 하부 베리어 메탈층을 퓨즈로 사용하는 공정 각 단계를 나타내는 공정 단면도들이다.1 to 5 are process cross-sectional views illustrating respective steps of a process of using a lower barrier metal layer of a conventional uppermost wiring layer as a fuse.
도6 내지 도7은 본 발명에 따라 퓨즈, 패드 및 보호용 폴리이미드막 패턴을 형성하는 방법의 일 실시예를 나타내는 공정 단면도들이다.6 to 7 are process cross-sectional views illustrating one embodiment of a method of forming a fuse, pad, and protective polyimide film pattern according to the present invention.
상기 목적을 달성하기 위한 본 발명의 반도체 장치 제조 방법은, 기판에 차상 배선층을 적층, 패터닝하여 차상 배선과 퓨즈를 형성하는 단계, 층간 절연막을 형성하는 단계, 최상 배선층을 적층 패터닝하여 최상 배선 및 패드를 형성하는 단계, 보호막 및 감광성의 보호용 폴리이미드막을 형성하는 단계, 마스크 노광 및 현상을 통해 퓨즈 영역 및 패드 영역에서 보호용 폴리이미드막을 제거하여 보호용 폴리이미드 패턴을 형성하는 단계, 보호용 폴리이미드 패턴을 이용하여 보호막을 식각함으로써 패드를 드러내는 단계를 구비하여 이루어진다.The semiconductor device manufacturing method of the present invention for achieving the above object, laminating and patterning the on-board wiring layer on the substrate to form the on-vehicle wiring and fuse, forming an interlayer insulating film, by laminating and patterning the uppermost wiring layer, the best wiring and pad Forming a protective film, forming a protective film and a photosensitive protective polyimide film, removing a protective polyimide film in a fuse region and a pad region through mask exposure and development, and forming a protective polyimide pattern, using a protective polyimide pattern To expose the pad by etching the protective film.
본 발명에서 차상 배선층 및 최상 배선층은 배선 금속층 상하에 베리어 메탈층을 구비하여 이루어질 수 있다. 또한, 보호막은 통상 산화막과 질화막을 적층하여 이중막으로 형성한다.In the present invention, the on-vehicle wiring layer and the uppermost wiring layer may be provided with a barrier metal layer above and below the wiring metal layer. In addition, the protective film is usually formed by laminating an oxide film and a nitride film.
보호용 폴리이미드 패턴을 식각 마스크로 사용하여 보호막을 식각할 때, 패드는 외부 단자와의 접속을 위해 드러나야 하지만, 퓨즈 위로는 보호막을 이루는 실리콘 산화막 일부 두께, 가령, 2000 옹스트롬 정도가 잔류하는 것이 퓨즈 보호를 위해 바람직하다.When the protective film is etched using the protective polyimide pattern as an etch mask, the pads must be exposed for connection to the external terminals, but the fuse protection may be due to the residual thickness of a portion of the silicon oxide film forming the protective film, such as 2000 angstroms, above the fuse. Preferred for
보호용 폴리이미드 패턴을 형성할 때에는 퓨즈와 최상 배선 사이의 오버랩 마아진(overlap margin)을 고려해야 한다. 즉, 보호막을 건식 식각하는 과정에서 보호용 폴리이미드 패턴이 수축하고 경사지는 현상으로 인하여 퓨즈 인근 영역에 최상 배선이 드러날 수 있음을 고려해야 한다. 이런 문제를 막기 위해 보호용 폴리이미드 패턴에 의해 드러나는 퓨즈 영역과 최상 배선 사이의 이격 거리가 3μm 이상 되도록 노광 마스크를 형성하는 것이 바람직하다. 이격 거리는 폴리이미드의 성질 및 두께에 따라 달라질 수 있다.When forming a protective polyimide pattern, the overlap margin between the fuse and the top wiring must be taken into account. That is, due to the phenomenon that the protective polyimide pattern shrinks and slopes during dry etching of the protective film, the best wiring may be revealed in the area near the fuse. In order to prevent such a problem, it is preferable to form the exposure mask so that the separation distance between the fuse area and the uppermost wiring exposed by the protective polyimide pattern is 3 m or more. The separation distance may vary depending on the nature and thickness of the polyimide.
차상 배선층을 패터닝하여 퓨즈를 형성한 뒤 기판에 반사방지막(ARC:Anti Reflection Coating) 등의 버퍼막을 적층하면, 후속 퓨즈 커팅 단계에서 레이져 커팅에 의해 퓨즈 물질의 파편이 드러난 배선 인근을 오염시키고 예상치 않은 단락을 형성하는 것을 방지하는 데 도움이 될 수 있다.After forming a fuse by patterning the on-board wiring layer and laminating a buffer film such as an anti-reflection coating (ARC) on the substrate, in the subsequent fuse cutting step, laser cutting causes contamination of the vicinity of the wiring where the fragments of the fuse material are exposed. It can help to prevent the formation of shorts.
감광성 폴리이미드막은 자체가 포토레지스트와 같이 감광성을 가지므로 통상의 포토레지스트 패턴을 이용하는 패터닝 과정, 즉, 노광 및 식각 공정 대신에 폴리이미드층 자체에 대한 마스크 노광과 현상만으로 이루어진다.Since the photosensitive polyimide film itself is photosensitive like a photoresist, instead of a patterning process using a conventional photoresist pattern, i.e., an exposure and etching process, only the mask exposure and development of the polyimide layer itself are performed.
이하 도면을 참조하면서 실시예를 통해 본 발명을 상세하게 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도6을 참조하면, 하부 소자 및 배선 구조가 형성된 기판(110)에 차상 배선층을 적층, 패터닝하여 차상 배선(미도시)과 퓨즈(125)를 형성한다. 차상 배선층은 알미늄 등의 배선 금속층 상하에 베리어 메탈층을 구비하여 이루어질 수 있다. 차상 배선 및 퓨즈 위로 기판 전면에 반사방지막(ARC:Anti Reflection Coating) 등의 버퍼막(127)을 얇게 적층한다. 이어서, CVD 방법으로 층간 절연막(120)을 형성한다. 이어서, 바람직하게는 층간 절연막(120) 상면을 평탄화한다.Referring to FIG. 6, a vehicle wiring layer and a fuse 125 are formed by stacking and patterning a vehicle wiring layer on a substrate 110 on which a lower element and a wiring structure are formed. The on-vehicle wiring layer may be formed by providing a barrier metal layer above and below the wiring metal layer such as aluminum. A thin buffer layer 127 such as an anti-reflection coating (ARC) is stacked on the entire surface of the board and the fuse. Subsequently, the interlayer insulating film 120 is formed by a CVD method. Next, the upper surface of the interlayer insulating film 120 is preferably planarized.
층간 절연막(120) 위에 최상 배선층을 적층하고 패터닝하여 최상 배선(미도시)과 패드를 형성한다. 최상 배선층도 알미늄 등의 배선 금속층(140) 상하에 베리어 메탈층(130,150)을 구비하여 이루어질 수 있다. 이어서, 패드 및 최상 배선이 형성된 기판에 HDP CVD(High Density Plasma Chemical Vapor Deposition)를 이용한 실리콘 산화막(160)과 실리콘 질화막(165)을 적층하여 보호막을 형성한다.A top wiring layer is stacked and patterned on the interlayer insulating layer 120 to form a top wiring (not shown) and a pad. The uppermost wiring layer may also be provided with barrier metal layers 130 and 150 above and below the wiring metal layer 140 such as aluminum. Subsequently, a protective film is formed by stacking a silicon oxide film 160 and a silicon nitride film 165 using HDP CVD (High Density Plasma Chemical Vapor Deposition) on a substrate on which a pad and a top wiring are formed.
도7을 참조하면, 보호막 위에 감광성의 보호용 폴리이미드막을 형성한다. 보호용 폴리이미드막에 대한 마스크 노광 및 현상을 실시하여 패드 영역 및 퓨즈 영역이 제거된 보호용 폴리이미드막 패턴(191)을 형성한다. 보호용 폴리이미드 패턴(191)을 형성할 때에는 퓨즈와 최상 배선 사이의 오버랩 마아진(overlap margin)을 고려해야 한다. 즉, 보호막을 건식 식각하는 과정에서 보호용 폴리이미드 패턴(191)이 수축하고 경사지는 현상으로 인하여 퓨즈 인근 영역에 최상 배선이 드러날 수 있음을 고려해야 한다. 이런 문제를 막기 위해 보호용 폴리이미드 패턴(191)에 의해 드러나는 퓨즈 영역과 최상차상사이의 이격 거리가 3μm 이상 되도록 노광 마스크를 형성하는 것이 바람직하다. 이격 거리는 폴리이미드의 성질 및 두께에 따라 달라질 수 있다.Referring to Fig. 7, a photosensitive protective polyimide film is formed on the protective film. Mask exposure and development are performed on the protective polyimide film to form the protective polyimide film pattern 191 from which the pad region and the fuse region are removed. When forming the protective polyimide pattern 191, an overlap margin between the fuse and the uppermost wiring should be considered. That is, due to the phenomenon that the protective polyimide pattern 191 shrinks and slopes during dry etching of the protective film, the best wiring may be revealed in the area near the fuse. In order to prevent such a problem, it is preferable to form an exposure mask such that the separation distance between the fuse region exposed by the protective polyimide pattern 191 and the uppermost phase is 3 μm or more. The separation distance may vary depending on the nature and thickness of the polyimide.
이어서, 보호용 폴리이미드 패턴(191)을 이용하여 보호막(160,165)을 식각한다. 이때, 식각시 외부 단자와의 접속을 위해 패드는 드러나야 하지만, 퓨즈 위로는 층간 절연막(120)을 이루는 실리콘 산화막 일부 두께, 가령, 2000 옹스트롬 정도가 잔류하는 것이 퓨즈 보호를 위해 바람직하다.Subsequently, the protective layers 160 and 165 are etched using the protective polyimide pattern 191. At this time, although the pad should be exposed for the connection with the external terminal during etching, it is preferable for the fuse protection that a portion of the thickness of the silicon oxide layer constituting the interlayer insulating layer 120, for example, about 2000 angstroms, remains on the fuse.
본 발명에 따르면, 종래의 예에서 반도체 장치에 최상 배선층의 베리어 메탈층으로 퓨즈를 형성하고, 최상 배선층으로 패드를 형성할 때, 퓨즈와 패드를 노출시키기 위해 별도의 노광 공정을 진행해야 하는 불편을 없애며, 특히, 감광성 폴리이미드를 사용하여 보호용 폴리이미드막 패턴, 퓨즈 및 패드 오픈을 하나의 노광 공정으로 실행할 수 있다. 또한, 종래에 비트라인을 퓨즈로 사용하는 경우에 비해 퓨즈 노출을 위해 많은 상부막을 식각 제거하는 불편을 없애고 퓨즈 이용의 신뢰성을 높일 수 있다.According to the present invention, in the conventional example, when the fuse is formed with the barrier metal layer of the uppermost wiring layer and the pad is formed with the uppermost wiring layer in the semiconductor device, the inconvenience of having to perform a separate exposure process to expose the fuse and the pad is avoided. In particular, the photosensitive polyimide can be used to carry out the protective polyimide film pattern, fuse and pad opening in one exposure process. In addition, compared to the case of using a bit line as a fuse in the related art, it is possible to eliminate the inconvenience of etching away a large number of upper layers for the exposure of the fuse and to increase the reliability of using the fuse.
Claims (5)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100746631B1 (en) * | 2006-09-19 | 2007-08-08 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device having metal fuse |
| KR100754895B1 (en) * | 2006-05-10 | 2007-09-04 | 삼성전자주식회사 | Semiconductor device and method for forming the same |
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2001
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100754895B1 (en) * | 2006-05-10 | 2007-09-04 | 삼성전자주식회사 | Semiconductor device and method for forming the same |
| KR100746631B1 (en) * | 2006-09-19 | 2007-08-08 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device having metal fuse |
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