KR100542943B1 - Repair etching method of semiconductor device - Google Patents
Repair etching method of semiconductor device Download PDFInfo
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- KR100542943B1 KR100542943B1 KR1019980061457A KR19980061457A KR100542943B1 KR 100542943 B1 KR100542943 B1 KR 100542943B1 KR 1019980061457 A KR1019980061457 A KR 1019980061457A KR 19980061457 A KR19980061457 A KR 19980061457A KR 100542943 B1 KR100542943 B1 KR 100542943B1
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- 238000005530 etching Methods 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000008439 repair process Effects 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 230000000903 blocking effect Effects 0.000 claims description 41
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 27
- 229910052718 tin Inorganic materials 0.000 claims description 27
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 72
- 239000007789 gas Substances 0.000 description 7
- 210000002381 plasma Anatomy 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 210000004087 cornea Anatomy 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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Abstract
본 발명은 반도체 소자의 리페어 식각(repair etch) 방법에 관한 것으로, 반도체 소자의 제조 공정중 패시베이션(passivation) 후에 리페어 식각을 통한 산화막 식각으로 퓨즈층(fuse layer)위에 수천 Å 정도의 두께를 남기는 공정에서, 퓨즈층 위에 산화막 형성시 산화막 중간에 금속층을 삽입하여, 1단계로 산화막을 금속층에 대해 선택적으로 식각하고, 2단계로 금속층을 산화막에 대해 선택적으로 식각하고, 3단계로 산화막을 식각 하는 방법으로 리페어 식각을 하므로 산화막 식각에 대한 편차를 줄여 퓨즈층 위에 남기는 산화막의 두께를 균일하게 형성할 수 있어, 리페어 수율을 증가시킬 수 있는 반도체 소자의 리페어 식각 방법에 관하여 기술된다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair etch method of a semiconductor device, wherein a process of leaving a thickness of about several thousand micrometers on a fuse layer by oxide etching through a repair etching after passivation during a semiconductor device manufacturing process. In the method of forming an oxide film on the fuse layer, a metal layer is inserted in the middle of the oxide film, the oxide film is selectively etched with respect to the metal layer in one step, the metal layer is selectively etched with respect to the oxide film in two steps, and the oxide film is etched in three steps. Since repair etching is performed, the thickness of the oxide film remaining on the fuse layer can be uniformly formed by reducing the variation of the etching of the oxide film, thereby describing a repair etching method of a semiconductor device capable of increasing the repair yield.
Description
본 발명은 반도체 소자의 리페어 식각(repair etch) 방법에 관한 것으로, 특히 반도체 소자의 제조 공정중 패시베이션(passivation) 후에 리페어 식각을 통한 산화막 식각으로 퓨즈층(fuse layer)위에 수천 Å 정도의 두께를 남기는 공정에서, 퓨즈층 위에 산화막 형성시 산화막 중간에 산화막에 대한 식각 선택비가 높은 블로킹층(blocking layer)을 삽입한 후 다단계로 리페어 식각을 진행하므로써, 퓨즈층 위에 남기는 산화막의 두께를 균일하게 형성할 수 있는 반도체 소자의 리페어 식각 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair etch method of a semiconductor device. In particular, an oxide film etched through a repair etch after passivation during a semiconductor device manufacturing process leaves a thickness of about several thousand micrometers on a fuse layer. In the process, when the oxide layer is formed on the fuse layer, a blocking layer having a high etching selectivity with respect to the oxide layer is inserted in the middle of the oxide layer, followed by repair etching in multiple steps, thereby uniformly forming the thickness of the oxide layer remaining on the fuse layer. The present invention relates to a repair etching method of a semiconductor device.
일반적으로, 레이저(laser)에 의한 리페어를 위해서는 반도체 소자의 제조 공정중 패시베이션 후에 리페어 식각을 실시하여 퓨즈층 위에 수천 Å 정도의 일정한 두께의 산화막을 남긴다. 이때, 리페어를 용이하게 하기 위해서는 남은 산화막의 두께를 ±1000 Å 이내의 오차 범위 내에서 조절할 필요가 있다. 그러나, 리페어 식각시 식각 하여야 하는 산화막의 두께는 소자별로 차이는 있지만 20000 내지 40000 Å 에 이르며, 식각시 산화막의 증착과 식각의 균일성(uniformity)을 고려할 때 ±1000 Å 이내의 오차 범위로 조절하기가 매우 어렵다. 예를 들어, 30000Å을 식각할 때 식각 균일성이 10 % 라고 가정하면 남은 산화막의 오차는 ±3000 Å이 발생한다.In general, in order to repair by a laser, a repair etching is performed after passivation during the manufacturing process of a semiconductor device, and an oxide film having a constant thickness of about several thousand micrometers is left on the fuse layer. At this time, in order to facilitate the repair, it is necessary to adjust the thickness of the remaining oxide film within an error range within ± 1000 Hz. However, the thickness of the oxide film to be etched during repair etching varies from device to device, but varies from 20000 to 40000 Å, and is controlled within an error range of ± 1000 Å when considering the deposition of oxide and uniformity of etching during etching. Is very difficult. For example, assuming that the etching uniformity is 10% when etching 30000 ms, the error of the remaining oxide film is ± 3000 Hz.
따라서, 본 발명은 리페어 식각으로 퓨즈층 위에 남는 산화막 두께의 균일성을 개선시켜 리페어 수율을 증가시킬 수 있는 반도체 소자의 리페어 식각 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a repair etching method of a semiconductor device capable of increasing the repair yield by improving the uniformity of the oxide thickness remaining on the fuse layer by the repair etching.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 리페어 식각 방법은 퓨즈층이 형성된 반도체 기판이 제공되는 단계; 상기 퓨즈층 상에 제 1 산화막, 블로킹층 및 제 2 산화막을 순차적으로 형성하는 단계; 상기 제 2 산화막의 일부분을 상기 블로킹층이 노출되도록 식각 하는 단계; 상기 노출된 블로킹층을 상기 제 1 산화막이 노출되도록 식각 하는 단계; 및 상기 노출된 제 1 산화막을 상기 퓨즈층 상에 수천 Å의 두께가 남도록 식각 하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Repair etching method of a semiconductor device of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a fuse layer; Sequentially forming a first oxide film, a blocking layer, and a second oxide film on the fuse layer; Etching a portion of the second oxide layer to expose the blocking layer; Etching the exposed blocking layer to expose the first oxide layer; And etching the exposed first oxide film such that the thickness of the exposed first oxide film remains thousands of Å on the fuse layer.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1d는 본 발명의 실시예에 따른 반도체 소자의 리페어 식각 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of a device for describing a repair etching method of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(11) 상에 층간 절연막(12)을 형성하고, 층간 절연막(12) 상에 퓨즈층(13)을 형성한다. 퓨즈층(13)상에 제 1 산화막(14)을 형성하고, 그 상부에 블로킹층(15)을 형성한다. 블로킹층(15) 상에 제 2 산화막(16)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a semiconductor substrate 11 on which various elements for forming a semiconductor element are formed, and a fuse layer 13 is formed on the interlayer insulating layer 12. The first oxide film 14 is formed on the fuse layer 13, and the blocking layer 15 is formed thereon. The second oxide film 16 is formed on the blocking layer 15.
도 1b를 참조하면, 제 2 산화막(16) 상에 포토레지스트 패턴(17)을 형성하고, 포토레지스트 패턴(17)을 식각 마스크로 하여 블로킹층(15)이 충분히 노출될 때까지 제 2 산화막(16)을 과도 식각(over etch)한다.Referring to FIG. 1B, a photoresist pattern 17 is formed on the second oxide film 16, and the second oxide film (until the blocking layer 15 is sufficiently exposed using the photoresist pattern 17 as an etch mask). Overetch etch 16).
도 1c를 참조하면, 포토레지스트 패턴(17)을 식각 마스크로 하여 제 2 산화막(16)의 식각으로 인해 노출된 블로킹층(15)을 하부층인 제 1 산화막(14)이 충분히 노출될 때까지 과도 식각 한다.Referring to FIG. 1C, the photoresist pattern 17 is used as an etching mask until the blocking layer 15 exposed due to the etching of the second oxide layer 16 is sufficiently exposed until the lower portion of the first oxide layer 14 is sufficiently exposed. Etch it.
도 1d를 참조하면, 포토레지스트 패턴(17)을 식각 마스크로 하여 블로킹층(15)의 식각으로 인해 노출된 제 1 산화막(14)을 퓨즈층(13) 상에 수천 Å의 두께가 남도록 식각 타겟을 조절하여 식각 한다.Referring to FIG. 1D, the etching target of the first oxide layer 14 exposed due to the etching of the blocking layer 15 using the photoresist pattern 17 as an etching mask may have a thickness of several thousand μs on the fuse layer 13. Adjust by etching.
상기한 본 발명의 실시예에서, 퓨즈층(13) 상에 형성되는 산화막의 전체 두께가 30000 Å이라고 가정하면, 제 1 산화막(14)은 레이저(laser)에 의한 리페어를 위해 필요한 산화막의 두께보다 적어도 두꺼운 약 5000 Å의 두께로 형성하고, 제 2 산화막(16)은 나머지 두께인 약 25000 Å의 두께로 형성한다. 블로킹층(15)은 산화막(14 및 16)에 대해 식각 선택비가 높은 물질을 사용하여 약 5000 Å의 두께로 형성한다.In the above-described embodiment of the present invention, assuming that the total thickness of the oxide film formed on the fuse layer 13 is 30000 m 3, the first oxide film 14 is larger than the thickness of the oxide film required for repair by a laser. It is formed to a thickness of at least about 5000 kPa thick, and the second oxide film 16 is formed to a thickness of about 25000 kPa which is the remaining thickness. The blocking layer 15 is formed to a thickness of about 5000 kPa using a material having a high etching selectivity with respect to the oxide films 14 and 16.
블로킹층(15)은 별도의 공정으로 형성할 수도 있지만, 반도체 소자의 제조 공정중 금속 배선 형성 공정시 금속층을 패터닝하여 퓨즈층(13) 윗 부분에 금속층을 남겨 사용할 수 있다. 반도체 소자에 사용되는 금속층은 텅스텐(W)이나 알루미늄(Al) 등이며, 또한 이 금속층들은 통상적으로 반사방지막(TiN, Ti/TiN)과 배리어 금속층(TiN, Ti/TiN)을 포함한다. 즉, 블로킹층(15)은 산화막에 대해 식각 선택비가 높은 물질 예를 들어, Al, Ti, TiN 중 적어도 어느 하나로 형성하거나, 반도체 소자의 금속층 적용 시에는 Al, Al/Ti, Al/TiN, Al/Ti/TiN, W/Ti, W/TiN, W/Ti/TiN 중 어느 하나로 형성된다.Although the blocking layer 15 may be formed by a separate process, the metal layer may be patterned during the metal wiring forming process during the manufacturing process of the semiconductor device to leave the metal layer on the upper portion of the fuse layer 13. The metal layer used in the semiconductor device is tungsten (W), aluminum (Al), or the like, and these metal layers typically include antireflection films (TiN, Ti / TiN) and barrier metal layers (TiN, Ti / TiN). That is, the blocking layer 15 is formed of a material having a high etching selectivity with respect to the oxide film, for example, at least one of Al, Ti, TiN, or Al, Al / Ti, Al / TiN, Al when the metal layer of the semiconductor device is applied. It is formed of any one of / Ti / TiN, W / Ti, W / TiN, and W / Ti / TiN.
제 1 및 제 2 산화막(14 및 16)의 식각 공정은 CF4, CHF3, C3F8, C4F12 가스 등의 플라즈마로 진행한다. 블로킹층(15)의 식각 공정은 블로킹층(15)으로 Al, Ti, TiN, Al/Ti, Al/TiN, Al/Ti/TiN, 중 어느 하나로 형성할 경우 Cl계 가스의 플라즈마로 진행하며, 블로킹층(15)으로 W/Ti, W/TiN, W/Ti/TiN 중 어느 하나로 형성할 경우 먼저 텅스텐(W) 식각을 SF6, NF3 가스 등의 플라즈마로 진행한 후, Ti 및/또는 TiN 식각을 Cl계 가스의 플라즈마로 진행한다.The etching process of the first and second oxide films 14 and 16 proceeds with plasma such as CF 4 , CHF 3 , C 3 F 8 , and C 4 F 12 gas. When the etching process of the blocking layer 15 is formed of any one of Al, Ti, TiN, Al / Ti, Al / TiN, Al / Ti / TiN, as the blocking layer 15, the etching process proceeds to the plasma of Cl-based gas, When the blocking layer 15 is formed of any one of W / Ti, W / TiN, and W / Ti / TiN, tungsten (W) etching is first performed by plasma such as SF 6 , NF 3 gas, and then Ti and / or The TiN etching proceeds with a plasma of Cl gas.
CF4, CHF3, C3F8, C4F12 가스 등의 플라즈마는 Al, Ti, TiN 와 화학적으로 잘 반응하지 않아 제 2 산화막(16) 식각시 블로킹층(15)에 대한 식각 선택비가 높고, Cl계 가스의 플라즈마는 산화물(oxide)과 화학적으로 잘 반응하지 않아 블로킹층(15) 식각시 제 1 산화막(14)에 대한 식각 선택비가 높다. 그러나, 텅스텐을 식각할 때 사용되는 SF6, NF3 가스 등의 플라즈마는 산화물에 대한 식각 선택비가 낮기 때문에 블로킹층(15)으로 텅스텐만을 적용하기에는 적절하지 않다.Plasma, such as CF 4 , CHF 3 , C 3 F 8 , and C 4 F 12 gases, do not react chemically well with Al, Ti, and TiN, resulting in an etch selectivity with respect to the blocking layer 15 during etching of the second oxide layer 16. The plasma of the Cl-based gas does not react chemically with oxides well, and thus the etching selectivity with respect to the first oxide layer 14 is high when the blocking layer 15 is etched. However, plasmas such as SF 6 and NF 3 gas used for etching tungsten are not suitable for applying only tungsten to the blocking layer 15 because the etching selectivity to oxide is low.
블로킹층을 사용하지 않는 경우와 사용하는 경우를 비교해 보면 다음과 같다.Comparing the case of not using the blocking layer with the use case is as follows.
블로킹층을 사용하지 않는 종래의 경우, 30000 Å의 두께를 리페어 식각할 때, 식각 균일성이 10 % 라고 가정하면 ±3000 Å의 편차가 발생된다. 이 편차가 남아 있는 산화막의 편차이다.In the conventional case of not using the blocking layer, when repair etching a thickness of 30000 kPa, assuming that the etching uniformity is 10%, a deviation of ± 3000 kPa occurs. This deviation is the deviation of the remaining oxide film.
블로킹층을 사용하는 본 발명의 경우, 블로킹층 위의 산화막의 두께가 25000 Å, 블로킹층의 두께가 5000 Å, 블로킹층 아래의 산화막의 두께가 5000 Å일 때, 각 단계에서 식각 균일성이 모두 10 %, 제 1 단계에서 블로킹층에 대한 식각 선택비를 10 : 1, 제 2 단계에서 산화막에 대한 식각 선택비를 10 : 1 로 가정한다. 그리고 제 1 단계 및 제 2 단계에서 각 막을 완전히 제거하기 위하여 50 % 의 과도 식각을 한다고 가정한다. 제 1 단계에서 과도 식각을 포함한 산화막 식각 타겟은 30000 Å 이며, 식각 균일성 10 % 가정시 ±3000 Å 의 편차가 고려되나 산화막이 모두 식각 되므로, 이러한 편차는 블로킹층의 손실(loss)로 전이된다. 이때, 발생되는 블로킹층의 손실의 편차는 식각 선택비가 10 : 1 이므로 ±300 Å 이 된다. 제 2 단계에서 과도 식각을 포함한 블로킹층 식각 타겟은 7500 Å 이며, 식각 균일성 10 % 가정시 ±750 Å 이다. 여기에 제 1 단계에서 전이된 편차를 합하면 ±1050 Å 이다. 블로킹층이 모두 식각 되므로, 이러한 편차는 블로킹층 아래의 산화막 편차 ±105 Å 으로 전이된다(제 2 단계의 선택비가 10 : 1 로 가정). 제 3 단계의 산화막 5000 Å 식각시 발생되는 편차는 ±500 Å 이므로 제 2 단계에서 전이된 ±105 Å를 합하면 ±605 Å 편차가 발생된다. 이 량이 블로킹층을 사용할 때의 남아 있는 산화막의 편차가 된다.In the case of the present invention using a blocking layer, when the thickness of the oxide film on the blocking layer is 25000 kPa, the thickness of the blocking layer is 5000 kPa, and the thickness of the oxide film under the blocking layer is 5000 kPa, all of the etching uniformities are obtained at each step. 10%, the etching selectivity for the blocking layer in the first step 10: 1, the etching selectivity for the oxide film in the second step is assumed to be 10: 1. And it is assumed that 50% over etching is performed in order to completely remove the cornea in the first and second steps. In the first step, the oxide etch target including the transient etching is 30000 mW, and a deviation of ± 3000 mW is assumed in the case of 10% etching uniformity, but since all the oxide layers are etched, this deviation is transferred to the loss of the blocking layer. . At this time, the deviation of the generated blocking layer is ± 300 kW since the etching selectivity is 10: 1. In the second step, the blocking layer etch target including the transient etching was 7500 mW, and ± 750 mW assuming 10% etching uniformity. The deviation shifted in the first step is added to ± 1050 Hz. Since all of the blocking layers are etched, this deviation is shifted to an oxide film deviation of ± 105 Hz under the blocking layer (assuming that the selectivity in the second step is 10: 1). Since the deviation generated during the etching of the oxide film 5000 의 in the third step is ± 500 Å, the ± 105 Å deviation generated in the second step is combined to generate a ± 605 Å deviation. This amount is a deviation of the remaining oxide film when the blocking layer is used.
상기에서 비교된 바와 같이, 본 발명의 방법에 의해 남아 있는 산화막의 편차가 종래 방법에 비하여 크게 개선됨을 알 수 있다. 단, 이 개선의 정도는 각 단계에서의 식각 선택비에 따라 달라지며, 각 단계에서 식각 선택비가 높을수록 좇은 결과를 얻을 수 있다.As compared with the above, it can be seen that the deviation of the oxide film remaining by the method of the present invention is greatly improved compared to the conventional method. However, the degree of improvement depends on the etching selectivity at each step, and the higher the etching selectivity at each step, the more the result can be obtained.
상술한 바와 같이, 본 발명은 반도체 소자의 제조 공정중 패시베이션(passivation) 후에 리페어 식각을 통한 산화막 식각으로 퓨즈층(fuse layer)위에 수천 Å 정도의 두께를 남기는 공정에서, 퓨즈층 위에 산화막 형성시 산화막 중간에 금속층을 삽입하여, 1단계로 산화막을 금속층에 대해 선택적으로 식각하고, 2단계로 금속층을 산화막에 대해 선택적으로 식각하고, 3단계로 산화막을 식각 하는 방법으로 리페어 식각을 하므로 산화막 식각에 대한 편차를 줄여 퓨즈층 위에 남기는 산화막의 두께를 균일하게 형성할 수 있어, 리페어 수율을 증가시킬 수 있다.As described above, the present invention provides an oxide film when an oxide film is formed on a fuse layer in a process of leaving an thickness of about several thousand micrometers on a fuse layer by an oxide film etching through a passivation process during a semiconductor device manufacturing process. By inserting the metal layer in the middle, the oxide film is selectively etched with respect to the metal layer in the first step, the metal layer is selectively etched with respect to the oxide film in the second step, and the etching is performed by etching the oxide film in the third step. By reducing the deviation, the thickness of the oxide film remaining on the fuse layer can be uniformly formed, thereby increasing the repair yield.
도 1a 내지 1d는 본 발명의 실시예에 따른 반도체 소자의 리페어 식각 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of devices for describing a repair etching method of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 층간 절연막11: semiconductor substrate 12: interlayer insulating film
13: 퓨즈층 14: 제 1 산화막13: fuse layer 14: first oxide film
15: 블로킹층 16: 제 2 산화막15: blocking layer 16: second oxide film
17: 포토레지스트 패턴17: photoresist pattern
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| KR20030028062A (en) * | 2001-09-27 | 2003-04-08 | 주식회사 하이닉스반도체 | Method for fabricating fuse box in semiconductor device |
| KR20030054791A (en) * | 2001-12-26 | 2003-07-02 | 동부전자 주식회사 | Method of forming fuse for semiconductor device |
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| KR970053163A (en) * | 1995-12-11 | 1997-07-29 | 김주용 | Bonding pad formation method of semiconductor device |
| KR970052398A (en) * | 1995-12-27 | 1997-07-29 | 김광호 | Manufacturing Method of Semiconductor Device |
| KR0170436B1 (en) * | 1994-11-02 | 1999-02-01 | 김영환 | Method of manufacturing mosfet |
| KR20000003231A (en) * | 1998-06-26 | 2000-01-15 | 김영환 | Fuse box forming method of semiconductor device |
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| KR0170436B1 (en) * | 1994-11-02 | 1999-02-01 | 김영환 | Method of manufacturing mosfet |
| KR970053163A (en) * | 1995-12-11 | 1997-07-29 | 김주용 | Bonding pad formation method of semiconductor device |
| KR970052398A (en) * | 1995-12-27 | 1997-07-29 | 김광호 | Manufacturing Method of Semiconductor Device |
| KR20000003231A (en) * | 1998-06-26 | 2000-01-15 | 김영환 | Fuse box forming method of semiconductor device |
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| KR100953345B1 (en) | 2007-12-27 | 2010-04-20 | 주식회사 동부하이텍 | Method for fabricating semi-conductor device |
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