KR100237025B1 - Metal layer etching method for semiconductor material - Google Patents
Metal layer etching method for semiconductor material Download PDFInfo
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- KR100237025B1 KR100237025B1 KR1019960055897A KR19960055897A KR100237025B1 KR 100237025 B1 KR100237025 B1 KR 100237025B1 KR 1019960055897 A KR1019960055897 A KR 1019960055897A KR 19960055897 A KR19960055897 A KR 19960055897A KR 100237025 B1 KR100237025 B1 KR 100237025B1
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- 238000005530 etching Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 40
- 239000002184 metal Substances 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 title 1
- 239000007789 gas Substances 0.000 claims description 32
- 238000001020 plasma etching Methods 0.000 claims description 8
- 230000000087 stabilizing effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속층 식각 방법에 관한 것으로, 금속층상에 성장된 자연산화막 및 반사 방지막을 식각하는 과정에서 발생되는 플라즈마(Plasma)방전 및 스파킹(Sparking)을 방지하기 위하여 식각 공정시 일정 량의 N2가스를 공급하므로써 공정의 안정도를 향상시키며 소자의 수율을 증대시킬 수 있도록 한 반도체 소자의 금속층 식각 방법에 관한 것이다.The present invention relates to a method of etching a metal layer of a semiconductor device, and in order to prevent plasma discharge and sparking generated during etching of a natural oxide film and an antireflection film formed on a metal layer, The present invention relates to a method of etching a metal layer of a semiconductor device, which improves the stability of the process and increases the yield of the device by supplying N 2 gas.
Description
본 발명은 반도체 소자의 금속층 식각 방법에 관한 것으로, 특히 공정의 안정도를 향상시킬 수 있도록 한 반도체 소자의 금속층 식각 방법에 관한 것이다.The present invention relates to a method of etching a metal layer of a semiconductor device, and more particularly, to a method of etching a metal layer of a semiconductor device capable of improving process stability.
일반적으로 반도체 소자의 제조 공정에서 금속층은 알루미늄(Al)과 같은 금속으로 형성된다. 또한 금속층상에는 금속층을 패터닝하기 위한 사진 공정시 나반사로 인한 불량의 발생을 방지하기 위하여 반사 방지막이 형성되는데, 그러면 상기와 같이 이루어진 금속층을 패터닝하기 위한 종래 반도체 소자의 금속층 식각 방법을 제1도 내지 제3도를 참조하여 설명하면 다음과 같다.Generally, the metal layer is formed of a metal such as aluminum (Al) in a process of manufacturing a semiconductor device. An anti-reflection film is formed on the metal layer in order to prevent the occurrence of defects due to photolithography or reflection due to photolithography for patterning the metal layer. The method for etching a metal layer of a conventional semiconductor device for patterning the metal layer as described above, Referring to FIG. 3, the following will be described.
종래에는 제1도에 도시된 바와 같이 절연층(2)이 형성된 실리콘 기판(1)상에 알루미늄(A1)과 같은 금속을 증착하여 금속층(3)을 형성한 후 상기 금속층(3)상에 티타늄(Ti) 및 티타늄 나이트라이드(TiN)를 순차적으로 증착하여 반사 방지막(4)을 형성한다. 그리고 상기 반사 방지막(4)상에 감광막(5)을 형성한 후 패터닝하는데, 이때 노출된 상기 반사 방지막(4)의 표면에 자연산화막(6)이 성장된다. 이후 상기 패터닝된 감광막(5)을 마스크로 이용한 1차 식각 공정으로 제2도에 도시된 바와 같이 노출된 부분의 상기 자연산화막(6) 및 반사 방지막(4)을 순차적으로 제거하고 2차 식각 공정으로 실시하여 노출된 부분의 상기 금속층(3)을 식각한 다음 3차 식각공정을 실시하여 제3도에 도시된 바와 같이 잔류된 상기 금속층(3)이 완전히 제거되도록 한다. 여기서 상기 1차 내지 3차 식각 공정은 플라즈마 식각 장비에서 실시된다. 이때 반응 가스로는 BCℓ3와 Cℓ2가 공급되는데, 상기 2차 및 3차 식각 공정시에는 안정화 가스 역활을 하는 N2가스를 추가로 공급된다.Conventionally, as shown in FIG. 1, a metal such as aluminum (Al) is deposited on a silicon substrate 1 on which an insulating layer 2 is formed to form a metal layer 3, (Ti) and titanium nitride (TiN) are sequentially deposited to form an antireflective film 4. Then, a photoresist film 5 is formed on the antireflection film 4 and then patterned. At this time, a native oxide film 6 is grown on the exposed surface of the antireflection film 4. Then, as shown in FIG. 2, the natural oxide film 6 and the antireflection film 4 of the exposed portion are sequentially removed by a first etching process using the patterned photoresist layer 5 as a mask, So that the exposed metal layer 3 is etched and then subjected to a third etching process so that the remaining metal layer 3 is completely removed as shown in FIG. Wherein the first to third etching processes are performed in a plasma etching apparatus. At this time, BC 3 and C 2 are supplied as the reaction gas, and N 2 gas serving as a stabilizing gas is additionally supplied in the second and third etching processes.
그런데 상기와 같은 식각 공정을 진행하는 경우 상기 1차 식각 공정시 플라즈마 이온이 상기 식각 장비내에 설치된 가리개(Shroud)의 홀(Hole)을 통해 방출되거나 스파킹 즉, 플라즈마 방전(플라즈마가 번쩍거리는 현상)이 발생되어 일정한 식각이 이루어지지 않으며 표면의 손상이 발생된다. 그리고 상기와 같은 현상에 의해 소자의 신뢰성 및 수율이 저하된다.However, when the etching process as described above is performed, plasma ions are emitted through the holes of the shroud provided in the etching equipment during the first etching process, or sparking, that is, plasma discharge (plasma flashing phenomenon) And a uniform etching is not performed, and the surface is damaged. The reliability and yield of the device are deteriorated by the above-described phenomenon.
따라서 본 발명은 금속층상에 성장된 자연산화막 및 반사 방지막을 식각하는 과정에서 일정 량의 N2가스를 공급하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속층 식각 방법을 제공하는 데 그 목적이 있다.Accordingly, it is an object of the present invention to provide a method of etching a metal layer of a semiconductor device, which can solve the above-described disadvantages by supplying a predetermined amount of N 2 gas in the process of etching a native oxide film and an antireflection film grown on a metal layer .
상기한 목적을 달성하기 위한 본 발명은 절연층이 형성된 실리콘 기판상에 금속층 및 반사 방지막을 순차적으로 형성한 후 소정의 마스크를 이용한 1차 식각공정으로 노출된 상기 반사 방지막상에 성장된 자연산화막 및 반사 방지막을 순차적으로 제거하는 단계와, 상기 단계로부터 노출된 부분의 상기 금속층을 식각하기 위하여 2차 식각 공정을 실시한 후 잔류된 상기 금속층이 완전히 제거되도록 3차 식각 공정을 실시하는 단계로 이루어지는 반도체 소자의 금속층 식각 방법에 있어서, 상기 1차 내지 3차 식각 공정은 반응 가스인 BCℓ3및 Cℓ2가스와 안정화 가스인 N2가스가 각각 공급되는 분위기하에서 실시되는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a metal layer and an antireflection film on a silicon substrate having an insulating layer formed thereon, And a third step of performing a third etching process so as to completely remove the remaining metal layer after performing a second etching process to etch the metal layer of the exposed portion from the step of removing the anti- in the etching method of the metal layer, the first to third etching process it is characterized in that the reaction performed under the gas BCℓ 3 and Cℓ 2 gas and the stabilizing gas, N 2 atmosphere in which the gas is supplied, respectively.
제1도 내지 제3도는 종래 반도체 소자의 금속층 식각 방법을 설명하기 위한 소자의 단면도.FIG. 1 is a cross-sectional view of a conventional device for explaining a method of etching a metal layer of a semiconductor device. FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1 : 실리콘 기판 2 : 절연층1: silicon substrate 2: insulating layer
3 : 금속층 4 : 반사 방지막3: metal layer 4: antireflection film
5 : 감광막 6 : 자연산화막5: photosensitive film 6: natural oxide film
이하, 상기 제1도 내지 제3도를 재 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the above first to third drawings.
본 발명에 따른 반도체 소자의 금속층 식각 방법은 상기 제1도 내지 제3도를 통해 설명된 종래의 금속층 식각 방법과 동일한 순서로 이루어지지만, 본 발명은 1차 식각 공정시 플라즈마 방전 및 스파킹이 발생되지 않도록 공정 조건을 개선한 것이다.Although the method of etching a metal layer of a semiconductor device according to the present invention is performed in the same manner as the conventional metal layer etching method described with reference to FIGS. 1 to 3, the present invention can be applied to a plasma etching method in which plasma discharge and sparking The process conditions are improved.
먼저, 상기 1차 식각 공정은 150 내지 250 mT의 압력이 유지되는 플라즈마 식각 장비에 400 내지 500 와트(W)의 고주파 전력(RF Power)이 인가되며 반응 가스인 80 내지 100 SCCM의 BCℓ3및 5 내지 15 SCCM의 Cℓ2가스와 안정화 가스인 10 내지 20 SCCM의 N2가스가 각각 공급되는 분위기하에서 20 내지 30 초동안 실시된다.First, in the first etching process, RF power of 400 to 500 W is applied to a plasma etching apparatus maintaining a pressure of 150 to 250 mT, and BCℓ 3 and 5 of a reaction gas of 80 to 100 SCCM are applied. To 15 SCCM of C l 2 gas and 10 to 20 SCCM of N 2 gas, respectively, for 20 to 30 seconds.
상기 2차 식각 공정은 150 내지 250 mT의 압력이 유지되는 상기 플라즈마식각 장비에 150 내지 250 와트(W)의 고주파 전력이 인가되며 반응 가스인 70 내지 80 SCCM의 BCℓ3및 30 내지 40 SCCM의 Cℓ2가스와 안정화 가스인 20 내지 30 SCCM의 N2가스가 각각 공급되는 분위기하에서 실시된다.In the second etching process, RF power of 150 to 250 W is applied to the plasma etching apparatus maintained at a pressure of 150 to 250 mT, and a BC 3 of 70 to 80 SCCM and a C 3 of 30 to 40 SCCM It is carried out in the second gas and stabilize the gas atmosphere is from 20 to 30 SCCM N 2 gas is supplied to each.
그리고 상기 3차 식각 공정은 50 내지 150 mT의 압력이 유지되는 상기 플라즈마 식각 장비에 400 내지 500 와트(W)의 고주파 전력이 인가되며 반응 가스인 70 내지 80 SCCM의 BCℓ3및 45 내지 55 SCCM의 Cℓ2가스와 안정화 가스인 20 내지 30 SCCM의 N2가스가 각각 공급되는 분위기하에서 실시된다.In the third etching process, a high frequency power of 400 to 500 W is applied to the plasma etching apparatus maintained at a pressure of 50 to 150 mT, and a reaction gas of 70 to 80 SCCM BC 3 and 45 to 55 SCCM C < 2 > gas and 20 to 30 SCCM of N 2 gas which is a stabilizing gas are supplied, respectively.
이때 상기 1차 식각 공정시 안정화 가스로 공급되는 N2가스의 량은 여러번의 실험 과정을 통해 최상의 식각 조건이 유지되도록 설정되었는데, 이는 상기 N2가스의 량에 따른 알루미늄(Al)으로 형성된 상기 금속층(3)의 식각비 변화를 관찰하므로써 가능해졌다.At this time, the amount of N 2 gas supplied to the stabilizing gas during the primary etching process is set so as to maintain the best etching condition through a number of experimental procedures. This is because the amount of N 2 gas supplied to the metal layer (3). ≪ / RTI >
상기 실험 결과 N2가스가 공급되지 않는 경우 상기 금속층(3)의 식각비는 1650Å/Min이었고, 10 SCCM의 N2가스가 공급되는 경우 상기 금속층(3)의 식각비는 1850Å/Min이었으며, 20 SCCM의 N2가스가 공급되는 경우 상기 금속층(3)의 식각비는 1752 Å/Min이었다. 따라서 상기 금속층(3)의 상태 및 공정 효율을 양호하게 유지시키기 위하여 상기 N2가스의 공급량을 10 내지 20 SCCM으로 설정하였다.As a result of the experiment, when the N 2 gas was not supplied, the etch rate of the metal layer 3 was 1650 Å / Min. When the N 2 gas of 10 SCCM was supplied, the etch rate of the metal layer 3 was 1850 Å / When N 2 gas of SCCM was supplied, the etching rate of the metal layer 3 was 1752 Å / Min. Therefore, in order to maintain the state of the metal layer 3 and the process efficiency well, the supply amount of the N 2 gas is set to 10 to 20 SCCM.
상술한 바와 같이 본 발명에 의하면 금속층상에 성장된 자연산화막 및 반사 방지막을 식각하는 과정에서 일정 량의 질소(N2)를 공급하므로써 플라즈마 방전 및 스파킹의 발생이 방지되어 공정의 안정도가 향상되며, 따라서 소자의 수율이 증대될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, a certain amount of nitrogen (N 2 ) is supplied in the process of etching the native oxide film and the antireflection film grown on the metal layer, thereby preventing plasma discharge and sparking, , And thus the yield of the device can be increased.
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| Country | Link |
|---|---|
| KR (1) | KR100237025B1 (en) |
-
1996
- 1996-11-21 KR KR1019960055897A patent/KR100237025B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980037181A (en) | 1998-08-05 |
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