KR970006933B1 - Forming method of conductive layer in semiconductor device - Google Patents
Forming method of conductive layer in semiconductor device Download PDFInfo
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- KR970006933B1 KR970006933B1 KR1019940012274A KR19940012274A KR970006933B1 KR 970006933 B1 KR970006933 B1 KR 970006933B1 KR 1019940012274 A KR1019940012274 A KR 1019940012274A KR 19940012274 A KR19940012274 A KR 19940012274A KR 970006933 B1 KR970006933 B1 KR 970006933B1
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- conductive layer
- teos film
- layer
- semiconductor device
- photoresist
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims description 16
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 18
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 229920001940 conductive polymer Polymers 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000006117 anti-reflective coating Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
Description
제1A도 내지 제1F도는 본 발명에 의한 반도체 소자의 도전층을 제조하는 방법을 설명하기 위해 도시한 소자의 단면도1A to 1F are cross-sectional views of a device shown for explaining a method of manufacturing a conductive layer of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1: 기판 2: 폴리실리콘층1: substrate 2: polysilicon layer
3: 텅스텐 실리사이드층 4: TEOS막3: tungsten silicide layer 4: TEOS film
5A, 5B: 제1 및 2포토레지스트 10: 도전층5A, 5B: First and Second Photoresist 10: Conductive Layer
A: 주변회로영역 B: 셀영역A: peripheral circuit area B: cell area
C: 노치(notch)부C: notch
본 발명은 반도체 소자의 도전층 제조방법에 관한 것으로, 특히 반사율(reflectance index)이 높은 도전물(예를들어, 텅스텐 실리사이드, 알루미늄 등)을 이용하여 소자에서 요구되는 도전층을 형성하기 위해 패턴닝(patterning)할 때 도전층의 단면형상(profile)을 양호하게 하기 위하여, 반사율이 높은 도전물상에 반사율이 낮고 제거가 용이한 TEOS막을 얇게 증착한 후 패턴닝 공정을 실시하므로 단면형상이 양호한 도전층을 얻을 수 있는 반도체 소자의 도전층 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a conductive layer of a semiconductor device, and more particularly, to patterning a conductive layer required for the device using a conductive material having a high reflectance index (for example, tungsten silicide, aluminum, etc.). In order to improve the profile of the conductive layer during patterning, a thin layer of TEOS film having low reflectance and easy removal is deposited on the conductive material having high reflectivity, followed by a patterning process, so that the conductive layer has a good cross-sectional shape. It relates to a method for producing a conductive layer of a semiconductor device can be obtained.
일반적으로, 반도체 소자의 제조공정중 워드라인, 비트라인 또는 금속배선등을 형성할 때 실리사이드 또는 알루미늄등을 많이 사용하고 있다. 그런데 실리사이드 또는 알루미늄은 반사율(R.I)이 매우 높다. 예를들어 텅스텐 실리사이드는 R.I≒110 정도이고, 알루미늄은 R.I≒200 정도이다. 최근 반도체 소자가 고집적화 되어감에 따라 토폴러지(Topology)는 심회되어가고, 특히 셀영역과 주변회로 영역 사이는 토폴러지가 더욱 심사하다. 따라서 반사율이 높은 도전물을 이용하여 소자에서 요구되는 도전층을 형성하고자 할때 심화된 토폴러지로 인하여 패턴닝 공정을 통해 양호한 단면형상을 얻기가 어렵다.In general, silicides or aluminum are frequently used to form word lines, bit lines, or metal interconnections during the manufacturing process of semiconductor devices. However, silicide or aluminum has a very high reflectance (R.I). For example, tungsten silicide is about R.I ≒ 110 and aluminum is about R.I ≒ 200. As semiconductor devices have recently been highly integrated, topologies have been deepened, and in particular, topologies have been examined between cell regions and peripheral circuit regions. Therefore, when the conductive layer required for the device is formed by using a conductive material having high reflectance, it is difficult to obtain a good cross-sectional shape through the patterning process due to the deep topology.
종래에는 반도체 소자의 도전층을 제조하기 위하여, 포토레지스트만을 사용하거나, 또는 도전물위에 반사율이 낮은 ARC(Anti-Reflective Coating)층 예를들어 질화물(nitride) 또는 TiN등을 얇게 형성하여 패턴닝 공정으로 도전층을 형성하였다. 포트레지스트만을 사용할 경우 토폴러지가 낮은 주변회로 영역의 SCUM 제거와 토폴러지가 높은 셀영역의 노치(notch) 및 포트레지스트의 단면형상 제어(Photoresist profile control)가 어려운 문제가 있고, ARC층을 적용할 경우 포토레지스트의 단면형상 제어가 쉬워 도전층의 단면형상을 양호하게 만들 수 있으나 패턴화된 도전층상에 남아있는 ARC층을 제거하기 위한 공정이 필요하며 노치 개선에도 한계가 있다.Conventionally, in order to manufacture a conductive layer of a semiconductor device, a patterning process may be performed by using only a photoresist or by forming a thin antireflective coating (ARC) layer such as nitride or TiN on the conductive material. The conductive layer was formed. If only the resist is used, it is difficult to remove the SCUM of the peripheral area with low topology and notch of the cell area with high topology, and to control the photoresist profile of the photoresist, and to apply the ARC layer. In this case, it is easy to control the cross-sectional shape of the photoresist, so that the cross-sectional shape of the conductive layer can be made good, but a process for removing the ARC layer remaining on the patterned conductive layer is required, and there is a limit in notch improvement.
이와같이 토폴러지가 심화된 곳에 반사율이 높은 도전물로 소자에서 요구되는 도전층을 형성할 때 마스크 작업시 노치 및 넥킹(necking)없이 패턴닝하는 것이 매우 어렵다 마스크 공정시 형성된 노치 포인트(notch point)는 포토레지스트의 두께가 낮은 부분에서는 식각후에 최종 패턴닝시 노치 또는 도전층의 단선의 주요원인으로 작용하여 소자의 수율저하 및 질을 저하시킨다.As such, when the conductive layer required for the device is formed of a conductive material having high reflectivity where the topology is increased, it is very difficult to pattern without notching and necking during masking. In the part where the thickness of the photoresist is low, it acts as a main cause of disconnection of the notch or conductive layer during final patterning after etching, thereby lowering the yield and quality of the device.
따라서, 본 발명은 포토레지스트와 도전물사이에 TEOS막을 형성하여 이를 하드 마스크(hard mask)로 사용하므로써 상기한 문제점을 해결할 수 있는 반도체 소자의 도전층을 제조하는 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a conductive layer of a semiconductor device which can solve the above problems by forming a TEOS film between a photoresist and a conductive material and using the TEOS film as a hard mask.
이러한 목적을 달성하기 위한 본 발명의 도전층 형성방법은 소정의 공정을 거친 기판(1)상에 소자에서 요구되는 도전층을 형성하기 위한 소정의 도전물을 증착한 후 그 상부에 TEOS막(4)을 소정 두께로 형성하는 단계와, 상기 단계로부터 TEOS막(4)상에 마스크 작업을 통하여 주변회로부분과 셀부분에 패턴화된 제1 및 2포토레지스트(5A, 5B)를 각각 형성하는 단계와, 상기 단계로부터 제1 및 2포토레지스터(5A, 5B)식각 장벽층으로 하여 노출부위의 TEOS막(4)을 식각하는 단계와, 상기 단계로부터 제1 및 2포토레지스트(5A, 5B)와 제1 및 2포토레지스트(5A, 5B)의 하부에 담아있는 TEOS막(4)을 식각장벽층으로 하여 노출부위의 도전물을 식각하는 단계와, 상기 단계로부터 제1 및 2포트레지스트(5A, 5B)를 제거한 후, HF 또는 BOE 습식식각용액에 담그어 중합체 및 남아있는 TEOS막(4)을 제거하여 반도체 소자에서 요구되는 단면형상을 갖는 도전층(10)을 형성하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the conductive layer forming method of the present invention deposits a predetermined conductive material for forming a conductive layer required for a device on a substrate 1 that has been subjected to a predetermined process, and then the TEOS film 4 thereon. ) And forming patterned first and second photoresists 5A and 5B on the peripheral circuit portion and the cell portion, respectively, by masking on the TEOS film 4 from the above step. And etching the TEOS film 4 on the exposed portion using the first and second photoresist 5A and 5B as an etching barrier layer from the above step, and the first and second photoresist 5A and 5B from the step; Etching the conductive material on the exposed portion using the TEOS film 4 contained under the first and second photoresist 5A and 5B as an etch barrier layer, and the first and second port resists 5A, 5B) is removed and then immersed in HF or BOE wet etching solution to polymer and remaining TEOS membrane (4) is removed to form a conductive layer 10 having a cross-sectional shape required for the semiconductor element.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1A도 내지 제1F도는 본 발명에 의한 반도체 소자의 도전층을 제조하는 방법을 설명하기 위해 도시한 소자의 단면도로서, 제1A도는 소정의 공정을 거쳐 토폴러지가 심화된 기판(1)상에 도전물로 폴리실리콘과 텅스텐 실리사이드를 순차적으로 증착하여 폴리실리콘층(2)과 텅스텐 실리사이드층(3)의 이중층으로 형성하고, 그 상부에 TEOS막(4)을 500∼800Å 정도로 형성한 상태를 도시한 것이다.1A to 1F are cross-sectional views of a device shown to explain a method for manufacturing a conductive layer of a semiconductor device according to the present invention, and FIG. 1A is a plan view on a substrate 1 having a deeper topology. Polysilicon and tungsten silicide were sequentially deposited as a conductive material to form a double layer of the polysilicon layer 2 and the tungsten silicide layer 3, and the TEOS film 4 was formed at about 500 to 800 Å on the top. It is.
상기 TEOS막(4)은 Si(OC2H5)4의 조성식으로 이루어지며, 최종 공정으로 폴리머를 제거하기 위한 HF 또는 BOE 습식식각 용액에 웨이퍼를 담글 때 담그는 시간(dipping time)을 최소화하기 위하여 TEOS를 조밀화(densilfy)시키지 않는다.The TEOS film 4 is composed of a Si (OC 2 H 5 ) 4 composition, and in order to minimize the dipping time when the wafer is immersed in HF or BOE wet etching solution to remove the polymer in the final process It does not densilfy TEOS.
제1B도는 상기 TEOS막(4)상에 마스크 작업을 통하여 주변회로영역(A)과 셀영역(B)에 패턴화된 제1 및 2포토레지스터(5A, 5B)를 각각 형성한 상태를 도시한 것이다. 이때 주변영역부분(A)의 포토레지스트(5A)는 난반사에 의한 노치부(C)가 형성된다. TEOS막(4)이 하부층인 텅스텐 실리사이드층(3)보다 반사율이 낮기때문에 노치부(C)는 작게 형성되지만 반사율이 높은 텅스텐 실리사이드층(3)을 그대로 사용할 경우 노치부(C)는 더욱 커지게 되어 제1포토레지스트(5A)의 단면형상은 더욱 악화되며, 그로인하여, 전술한 바와같이 소자에서 요구되는 단면형상을 갖는 도전층을 얻기가 어렵게 된다.FIG. 1B shows a state where the first and second photoresist 5A and 5B patterned in the peripheral circuit region A and the cell region B are formed on the TEOS film 4 by masking, respectively. will be. At this time, the photoresist 5A of the peripheral region portion A is formed with a notch portion C due to diffuse reflection. Since the TEOS film 4 has a lower reflectance than the lower tungsten silicide layer 3, the notch portion C is formed small, but when the tungsten silicide layer 3 having high reflectance is used as it is, the notch portion C becomes larger. As a result, the cross-sectional shape of the first photoresist 5A is further deteriorated, whereby it becomes difficult to obtain a conductive layer having the cross-sectional shape required for the device as described above.
제1C도는 제1 및 2포토레지스트(5A, 5B)를 식각장벽층으로 하여 노출된 부위의 TEOS막(4)을 식각한 상태를 도시한 것이다. TEOS막(14) 식각시 제1 및 2포토레지스트(5A, 5B)의 식각손실을 최소화시키기 위하여 CF4플라즈마를 통하여 TEOS막(4)을 제거한다.FIG. 1C shows a state in which the TEOS film 4 in the exposed portion is etched using the first and second photoresists 5A and 5B as etch barrier layers. The TEOS film 4 is removed through the CF 4 plasma to minimize the etch loss of the first and second photoresist 5A and 5B during the etching of the TEOS film 14.
한편, 공정의 단순화를 위하여 하부층인 텅스텐 실리사이드층(3) 식각제인 SF6와 Cℓ2개스를 이용하여 TEOS막(4)을 제거할 수 있다. 즉, SF6와 Cℓ2개스를 사용한 한번의 공정으로 TEOS막(4) 및 텅스텐 실리사이드층(3)을 식각할 수 있어 생산성 향상 및 장비관리가 용이한 잇점이 있다.In order to simplify the process, the TEOS film 4 may be removed using SF 6 and C 1 gas, which are the tungsten silicide layer 3 etchant as the lower layer. That is, since the TEOS film 4 and the tungsten silicide layer 3 can be etched in one process using SF 6 and C 2 gas, productivity and equipment management can be easily improved.
제1D도는 상기 TEOS막(4)이 제거되어 노출된 부분의 텅스텐 실리사이드층(4)을 Cℓ2또는 Cℓ2와 SF6개스를 이용하여 식각한 상태를 도시한 것이다. 상기 텅스텐 실리사이드층(4)이 식각되는 동안 제1 및 2포토레지스트(5A, 5B)도 일부 식각되는데, 이로인하여 제1포토레지스트(5A) 하부의 TEOS막(4)의 일부가 노출되게 된다. 텅스텐 실리사이드층(4)의 식각은 노출된 TEOS막(4)의 모서리부(D)가 최소한 150∼200Å 정도 남을때까지 실시한다.FIG. 1D shows a state in which the tungsten silicide layer 4 of the portion exposed by removing the TEOS film 4 is etched using C 2 or C 2 and SF 6 gas. While the tungsten silicide layer 4 is etched, some of the first and second photoresists 5A and 5B are also etched, thereby exposing a part of the TEOS film 4 under the first photoresist 5A. The tungsten silicide layer 4 is etched until the edges D of the exposed TEOS film 4 remain at least about 150 to 200 Å.
한편, 본 발명의 실시예에서는 TEOS막(4)을 500∼800Å 정도로 증착하였으나 텅스텐 실리사이드의 증착두께를 고려하면서 상기와 같이 노출된 TEOS막(4)의 모서리부(D)가 최소한 150∼200Å 정도 남겨야 되는점을 고려하여 최초의 TEOS막(4)의 증착두께를 설정한다.Meanwhile, in the exemplary embodiment of the present invention, the TEOS film 4 is deposited at about 500 to 800 GPa, but the edge portion D of the exposed TEOS film 4 is at least about 150 to 200 GPa while considering the deposition thickness of tungsten silicide. In consideration of the remaining points, the deposition thickness of the first TEOS film 4 is set.
제1E도는 제1 및 2포트레지스트(5A, 5B)와 그 하부의 TEOS막(4)을 식각 장벽층으로 하여 노출된 부위의 폴리실리콘층(2)을 Cℓ2또는 Cℓ2와 HBr 개스를 이용하여 식각한 상태를 도시한 것이다. 상기 폴리실리콘층(2)이 식각되는 동안 제1 및 2포트레지스트(5A, 5B)도 일부 식각되고, 또한 제1포토레지스트(5A) 하부의 노출된 TEOS막(4)도 식각되어진다 그런데 폴리와 TEOS의 식각선택비는 폴리: TEOS=100: 1∼150 : 1 정도로 높은 식각 선택비를 갖기 때문에 TEOS의 식각 손실은 1분당 20∼30Å 정도로 매우 작다. 즉 제1포토레지스트(5A)의 노치부(C)로 인하여 TEOS막(4)이 노출되더라도 충분히 식각장벽층 역할을 할 수 있어 도전층으로서의 폴리실리콘층 및 텅스텐 실리사이드층(2 및 3)의 식각 단면형상의 불량을 유발시키지 않는다. TEOS막(4)내에는 산소와 탄소가 포함되어 있어 Cℓ2, Cℓ2와 HBr, Cℓ2와 O2등의 식각제(etch chemistries)와 반응이 원활히 이루어지는 중합화(polymerization) 및 재결합(recombination) 특성이 있어 얇은 두께로도 포토레지스트와 같은 마스크 역할을 충분히 한다.FIG. 1E shows the polysilicon layer 2 of the exposed portion using C1 2 or C1 2 and HBr gas using the first and second pot resists 5A and 5B and the TEOS film 4 under the etch barrier layer. Shows the state of etching. While the polysilicon layer 2 is etched, the first and second port resists 5A and 5B are partially etched, and the exposed TEOS film 4 under the first photoresist 5A is also etched. The etching selectivity of TEOS is as high as poly: TEOS = 100: 1 to 150: 1 so that the etching loss of TEOS is very small, about 20 ~ 30Å / min. That is, even if the TEOS film 4 is exposed due to the notch C of the first photoresist 5A, the polysilicon layer and the tungsten silicide layers 2 and 3 as the conductive layers can be sufficiently etched. Does not cause bad cross-sectional shape. Polymerization and recombination in which the TEOS film 4 contains oxygen and carbon and reacts easily with etch chemistries such as C 2 , C 2 and HBr, and C 2 and O 2 . Because of its characteristics, even a thin thickness serves as a mask like a photoresist.
제1F도는 상기 제1 및 2포토레지스트(5A, 5B)를 O2플라즈마를 이용하여 제거하고, 식각공정중에 발생된 Si 계통의 중합체(polymer)를 제거하기 위해 HF 또는 BOE 습식식각용액에 웨이퍼를 담그는데, 이때 TEOS막(4)도 제거되어져 소자에서 요구되는 안정된 단면형상을 갖는 도전층(10)이 형성된 상태를 도시한 것이다.FIG. 1F illustrates the removal of the first and second photoresists 5A and 5B using an O 2 plasma, and a wafer in HF or BOE wet etching solution to remove the Si-based polymer generated during the etching process. In this case, the TEOS film 4 is also removed so that the conductive layer 10 having a stable cross-sectional shape required by the device is formed.
제lA도 내지 제1F도를 참조하여 설명한 상기 본 발명의 실시예는 도전물로서 폴리실리콘층과 텅스텐 실리사이드층의 이중층을 갖는 폴리사이드 구조의 도전층을 형성하는 경우를 설명하였지만, 금속배선등을 형성할 때 많이 사용하는 알루미늄 합금을 도전물로하여 상기한 공정방법으로 안정된 단면형상을 갖는 도전층을 얻을 수 있다.Although the embodiment of the present invention described with reference to FIGS. 1A to 1F has described a case where a conductive layer having a polyside structure having a double layer of a polysilicon layer and a tungsten silicide layer as a conductive material has been described, metal wiring and the like are described. The conductive layer having a stable cross-sectional shape can be obtained by the above-described process method using an aluminum alloy commonly used for forming as a conductive material.
본 발명에 의하면, 토폴러지가 심화된 부분에서 안정된 단면형상을 갖는 도전층을 얻기 위하여 반사율이 낮고 제거가 용이한 TEOS막을 하드 마스크로 사용한다.According to the present invention, a low reflectance and easy removal TEOS film is used as a hard mask in order to obtain a conductive layer having a stable cross-sectional shape in a portion where the topology is increased.
상술한 바와같이 소자에서 요구되는 도전층 제조시 TEOS막을 하드 마스크로 사용하므로써, 하프 마이크론(half micron) 선폭의 소자의 경우 패턴닝을 위해i-line급 스탭퍼(Stepper)를 사용해야 하지만 G-line급 스텝퍼로도 사용가능하게 하며, TEOS막은 최종공정인 중합제 제거공정시 자연제거되어 공정을 단순화 시키며, 또한 노치 개선을 통한 생산성, 소자수율 및 질을 향상시킨다.As described above, since the TEOS film is used as a hard mask when manufacturing the conductive layer required for the device, an i -line stepper must be used for patterning in the case of a device having a half micron line width, but a G-line level is used. It can also be used as a stepper, and TEOS membrane is naturally removed during the final polymer removal process, simplifying the process and improving productivity, device yield and quality through improved notch.
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