KR20030046932A - a method for forming contact hole of semiconductor device - Google Patents

a method for forming contact hole of semiconductor device Download PDF

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Publication number
KR20030046932A
KR20030046932A KR1020010077270A KR20010077270A KR20030046932A KR 20030046932 A KR20030046932 A KR 20030046932A KR 1020010077270 A KR1020010077270 A KR 1020010077270A KR 20010077270 A KR20010077270 A KR 20010077270A KR 20030046932 A KR20030046932 A KR 20030046932A
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South Korea
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contact hole
layer
forming
inorganic
antireflection film
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KR1020010077270A
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Korean (ko)
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백운석
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주식회사 하이닉스반도체
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Priority to KR1020010077270A priority Critical patent/KR20030046932A/en
Publication of KR20030046932A publication Critical patent/KR20030046932A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

PURPOSE: A method for forming a contact hole in a semiconductor device is provided to be capable of increasing the aspect ratio of contact hole. CONSTITUTION: An interlayer dielectric(102), a polysilicon layer(103) and an inorganic anti-reflective layer(104) are sequentially formed on a stop layer(101). The inorganic anti-reflective layer(104) is selectively etched using a photoresist pattern(105) as a mask. At this time, polymers(106) are formed at both sidewalls of the photoresist pattern. The exposed polysilicon layer(103) is selectively etched. Then, a contact hole is formed by selectively etching the interlayer dielectric(102) using the inorganic anti-reflective layer and the polysilicon layer as a mask.

Description

반도체 소자의 콘택홀 형성방법{a method for forming contact hole of semiconductor device}A method for forming contact hole of semiconductor device

본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 0.1㎛ 이하 사이즈의 높은 종횡비 콘택홀(High Aspect Ratio Hole Define)을 형성하는 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device for forming a high aspect ratio hole hole having a size of 0.1 μm or less.

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택홀 형성방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

도 1a에 도시한 바와 같이 스톱 레이어층(11)상에 층간 절연막(12)을 형성하고, 상기 층간 절연막(12)상에 유기 반사방지막(Organic ARC)(13)을 형성한 후, 상기 유기 반사방지막(13)상에 포토레지스트(14)를 증착하고, 노광 및 현상공정을 이용하여 상기 포토레지스트(14)를 패터닝한다. 이때, 상기 유기 반사방지막(13)은 난반사 또는 간섭현상을 줄여 마스크 패턴 형성이 잘 되도록 한다.As shown in FIG. 1A, an interlayer insulating film 12 is formed on the stop layer layer 11, and an organic antireflection film 13 is formed on the interlayer insulating film 12. The photoresist 14 is deposited on the protective film 13, and the photoresist 14 is patterned using an exposure and development process. In this case, the organic antireflection film 13 may reduce diffused reflection or interference to form a mask pattern well.

그리고 상기 포토레지스트(14)의 두께는 0.7∼1㎛ 정도이고, 상기 층간 절연막(12)의 두께는 3㎛이상이다.The thickness of the photoresist 14 is about 0.7 to 1 m, and the thickness of the interlayer insulating film 12 is 3 m or more.

이어, 상기 패터닝된 포토레지스트(14)를 마스크로 이용하여 상기 유기 반사방지막(12)을 식각한다.Subsequently, the organic anti-reflection film 12 is etched using the patterned photoresist 14 as a mask.

도 1b에 도시한 바와 같이 상기 패터닝된 포토레지스트(14) 및 유기 반사방지막(13)을 마스크로 이용하여 상기 스톱 레이어층(11)이 선택적으로 노출되도록 층간 절연막(12)을 식각하여 콘택홀(15)을 형성한다.As shown in FIG. 1B, the interlayer insulating layer 12 is etched to selectively expose the stop layer layer 11 using the patterned photoresist 14 and the organic antireflective layer 13 as a mask to form a contact hole ( 15).

이때, 상기 패터닝된 포토레지스트(14)가 식각 진행중 화학(Chamical)반응 또는 스퍼터닝(Sputtering) 현상으로 인해 손실(Loss)이 발생된다. 그리고 상기 포토레지스트(14)의 상부 가장자리 부분은 화학반응과 스퍼터닝 현상이 다른 부분보다 잘 일어나기 때문에 포토레지스트(14)에 패싯(facet) 현상이 나타난다.In this case, a loss occurs due to a chemical reaction or sputtering during the etching of the patterned photoresist 14. The upper edge portion of the photoresist 14 has a facet phenomenon in the photoresist 14 because chemical reaction and sputtering occur better than other portions.

따라서, 상기 포토레지스트(14)를 마스크로 이용하여 상기 층간 절연막(12)을 식각하여 콘택홀(15) 형성시 상기 층간 절연막(12) 일부도 식각되어 도 1c와 같이 상기 콘택홀(15) 탑(Top)부분에 슬로프(slope)가 발생한다.Accordingly, when the interlayer insulating layer 12 is etched using the photoresist 14 as a mask to form the contact hole 15, a part of the interlayer insulating layer 12 is also etched, as shown in FIG. 1C. There is a slope in the (Top) part.

즉, 종래의 반도체 소자의 콘택홀 형성방법에 있어서는 유기 난반사 방지막과 포토레지스트를 마스크로 이용하여 콘택홀 형성시 식각 진행중 포토레지스트에 패싯 현상이 발생하여 콘택홀 상부의 탑에 슬로프가 발생한다.That is, in the conventional method of forming a contact hole in a semiconductor device, a facet phenomenon occurs during photolithography during etching during contact hole formation using an organic anti-reflective coating and a photoresist as a mask, thereby generating a slope on the top of the contact hole.

따라서, 슬로프를 갖는 콘택홀에 플러그 형성시 보이드 현상이 발생하고, 패턴이 조밀한 곳에서는 브리지(bridge)를 유발한다.Therefore, voids occur when plugs are formed in contact holes having slopes, and bridges are caused where the patterns are dense.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 무기 반사방지막과 폴리층을 형성한 후, 마스크 패턴을 형성하므로 0.1㎛ 이하에서 필요한 0.1㎛ 이하 사이즈의 고종횡비를 갖는 콘택홀을 형성할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and after forming the inorganic anti-reflection film and the poly layer, the mask pattern is formed to form a contact hole having a high aspect ratio of 0.1 ㎛ or less size required in 0.1 ㎛ or less It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device.

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택홀 형성방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성방법을 나타낸 공정 단면도2A to 2E are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101 : 스톱 레이어층 102 : 층간 절연막101: stop layer layer 102: interlayer insulating film

103 : 폴리층 104 : 무기 반사방지막103: poly layer 104: inorganic antireflection film

105 : 포토레지스트 106 : 폴리머105: photoresist 106: polymer

107 : 콘택홀 108 : 플러그107: contact hole 108: plug

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 콘택홀 형성방법은 스톱 레이어층상에 층간 절연막, 폴리층, 무기 반사방지막을 차례로 형성하는 단계와, 상기 무기 반사방지막상에 포토레지스트 패턴을 형성하고, 상기 무기 반사방지막을 식각시 상기 포토레지스트 패턴에 폴리머가 생성되는 단계, 상기 노출된 폴리층을 식각하는 단계와, 상기 무기 반사방지막 및 폴리층을 마스크로 이용하여 상기 층간 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention includes sequentially forming an interlayer insulating film, a poly layer, and an inorganic antireflection film on a stop layer layer, and forming a photoresist pattern on the inorganic antireflection film. When the inorganic anti-reflection film is etched, a polymer is formed in the photoresist pattern, the exposed poly layer is etched, and the interlayer insulating film is etched by using the inorganic anti-reflection film and the poly layer as a mask. And forming a hole.

또한, 상기 무기 반사방지막 식각시 HBr 가스를 이용하는 것이 바람직하다.In addition, it is preferable to use HBr gas when etching the inorganic anti-reflection film.

또한, 상기 무기 반사방지막을 마스크로 이용하여 CxFy, CHxFy의 가스로 콘택홀 형성할 경우 자연적으로 제거되는 것이 바람직하다.In addition, when the contact hole is formed of a gas of C x F y , CH x F y by using the inorganic anti-reflection film as a mask, it is preferably removed.

또한, 상기 콘택홀 형성후, 인산을 이용하여 상기 무기 반사방지막을 제거하는 것이 바람직하다.In addition, after the contact hole is formed, it is preferable to remove the inorganic antireflection film by using phosphoric acid.

또한, 상기 무기 반사방지막의 두께는 300∼600Å인 것이 바람직하다.In addition, the inorganic antireflection film preferably has a thickness of 300 to 600 kPa.

또한, 상기 폴리층의 두께는 1800∼2000Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said poly layer is 1800-2000 kPa.

또한, 상기 포토레지스트 패턴의 두께는 5000∼7000Å인 것이 바람직하다.Moreover, it is preferable that the thickness of the said photoresist pattern is 5000-7000 GPa.

이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 콘택홀 형성방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of forming a contact hole in a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성방법을 나타낸 공정 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

도 2a에 도시한 바와 같이 스톱 레이어층(101)상에 층간 절연막(102)을 형성하고, 상기 층간 절연막(102)상에 폴리층(103), 무기 반사방지막(Inorganic ARC)(104)을 차례로 형성한다. 이때, 상기 무기 반사방지막(104)의 두께는 300∼600Å이고, 상기 폴리층(103)의 두께는 1800∼2000Å이다. 그리고 상기 무기 반사방지막(104)은 SiON이다.As shown in FIG. 2A, an interlayer insulating film 102 is formed on the stop layer layer 101, and a poly layer 103 and an inorganic anti-reflection film (Inorganic ARC) 104 are sequentially formed on the interlayer insulating film 102. Form. At this time, the thickness of the inorganic antireflection film 104 is 300 to 600 kPa, and the thickness of the poly layer 103 is 1800 to 2000 kPa. The inorganic antireflection film 104 is SiON.

이어, 상기 무기 반사방지막(104)상에 포토레지스트(105)를 증착하고, 노광 및 현상공정을 이용하여 상기 포토레지스트(105)를 패터닝한다. 이때, 상기 포토레지스트(105)의 두께는 5000∼7000Å이다.Subsequently, a photoresist 105 is deposited on the inorganic antireflection film 104, and the photoresist 105 is patterned by using an exposure and development process. At this time, the thickness of the photoresist 105 is 5000 to 7000 GPa.

도 2b에 도시한 바와 같이 상기 패터닝된 포토레지스트(105)를 마스크로 이용하여 상기 폴리층(103)이 선택적으로 노출되도록 상기 무기 반사방지막(104)을 식각한다. 이때, 상기 식각공정은 HBr 가스를 이용하여 상기 무기 반사방지막(104)을 식각하므로 폴리머(106)가 다량 발생하여 상기 패터닝된 포토레지스트(105) 측면에 폴리머(106)가 흡착된다.As shown in FIG. 2B, the inorganic anti-reflection film 104 is etched to selectively expose the poly layer 103 using the patterned photoresist 105 as a mask. In this case, since the inorganic anti-reflection film 104 is etched using HBr gas, a large amount of polymer 106 is generated and the polymer 106 is adsorbed onto the sidewall of the patterned photoresist 105.

따라서, 상기 무기 반사방지막(104)은 상기 패터닝된 포토레지스트(105)에서 구현한 콘택홀 사이즈보다 0.05∼0.1㎛보다 작게 구현할 수 있다.Therefore, the inorganic antireflection film 104 may be smaller than 0.05 to 0.1 μm than the contact hole size implemented by the patterned photoresist 105.

도 2c에 도시한 바와 같이 상기 폴리머(106)가 흡착된 포토레지스트(105) 및 무기 반사방지막(104)을 마스크로 이용하여 상기 노출된 폴리층(103)을 식각한 후, 상기 패터닝된 포토레지스트(105)를 제거하고, 세정공정을 실시한다.As shown in FIG. 2C, the exposed poly layer 103 is etched using the photoresist 105 and the inorganic anti-reflection film 104 having the polymer 106 adsorbed thereon as a mask, and then the patterned photoresist is etched. (105) is removed and a washing step is performed.

도 2d에 도시한 바와 같이 상기 무기 반사방지막(104)과 폴리층(103)을 마스크로 이용하여 상기 층간 절연막(102)을 선택적으로 식각하여 콘택홀(107)을 형성한다.As shown in FIG. 2D, the interlayer insulating film 102 is selectively etched using the inorganic antireflection film 104 and the poly layer 103 as a mask to form a contact hole 107.

이때, 상기 식각 공정시 CxFy, CHxFy의 가스를 이용하여 상기 콘택홀(107)을 형성할 경우 자연적으로 상기 무기 반사방지막(104)이 제거된다.In this case, when the contact hole 107 is formed using gas of C x F y and CH x F y during the etching process, the inorganic anti-reflection film 104 is naturally removed.

여기서, 상기 폴리층(103)을 마스크로 사용함으로써 상기 층간 절연막(102)에 대한 선택비가 포토레지스트를 사용하는 경우보다 5배 이상 높기 때문에 상기 층간 절연막(102) 탑(Top)부분이 손실되는 현상이 발생하지 않는다.Here, the use of the poly layer 103 as a mask causes loss of the top portion of the interlayer insulating film 102 because the selectivity to the interlayer insulating film 102 is five times higher than that of the photoresist. This does not happen.

도 2e에 도시한 바와 같이 상기 결과물 상부에 도전층을 증착하고 CMP 공정을 이용하여 상기 콘택홀(107)에 매립되도록 플러그(108)를 형성한다.As shown in FIG. 2E, a conductive layer is deposited on the resultant, and a plug 108 is formed to be filled in the contact hole 107 using a CMP process.

이때, 상기 도전층이 폴리층일 경우 상기 폴리 식각을 실시하고, 상기 도전층이 텅스텐일 경우 SF6와 Cl2가스를 이용하여 식각한다.In this case, when the conductive layer is a poly layer, the poly etching is performed, and when the conductive layer is tungsten, etching is performed using SF 6 and Cl 2 gas.

이상에서 설명한 바와 같이 본 발명의 반도체 소자의 콘택홀 형성방법에 의하면, 무기 반사방지막를 HBr 가스로 식각하여 포토레지스트 측면에 폴리머를 형성시켜 마스크에서 형성된 홀 사이즈보다 0.05∼0.1㎛ 정도 작은 사이즈의 홀을 형성할 수 있다.As described above, according to the method for forming a contact hole of the semiconductor device of the present invention, the inorganic antireflection film is etched with HBr gas to form a polymer on the side surface of the photoresist to form a hole having a size of 0.05 to 0.1 占 퐉 smaller than the hole size formed in the mask. Can be formed.

또한, 무기 반사방지막과 폴리층을 마스크로 이용하여 층간 절연막을 식각하므로 포토레지스트보다 층간 절연막에 대한 선택비를 높일 수 있어 높은 깊이를 갖는 홀도 상부에 탑 슬로프가 발생하지 않는다.In addition, since the interlayer insulating film is etched by using the inorganic antireflection film and the poly layer as a mask, the selectivity of the interlayer insulating film can be higher than that of the photoresist, so that a top slope does not occur even in a hole having a high depth.

따라서, 콘택홀에 플러그 형성시 보이드 현상이 발생하지 않고, 패턴이 조밀한 곳에서도 브리지를 유발하지 않는다.Therefore, voids do not occur when the plug is formed in the contact hole, and the bridge is not induced even where the pattern is dense.

Claims (7)

스톱 레이어층상에 층간 절연막, 폴리층, 무기 반사방지막을 차례로 형성하는 단계와;Sequentially forming an interlayer insulating film, a poly layer, and an inorganic antireflection film on the stop layer layer; 상기 무기 반사방지막상에 포토레지스트 패턴을 형성하고, 상기 무기 반사방지막을 식각시 상기 포토레지스트 패턴에 폴리머가 생성되는 단계;Forming a photoresist pattern on the inorganic antireflection film, and forming a polymer on the photoresist pattern when the inorganic antireflection film is etched; 상기 노출된 폴리층을 식각하는 단계와;Etching the exposed poly layer; 상기 무기 반사방지막 및 폴리층을 마스크로 이용하여 상기 층간 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And forming a contact hole by etching the interlayer insulating layer using the inorganic antireflection film and the poly layer as a mask. 제 1 항에 있어서,The method of claim 1, 상기 무기 반사방지막 식각시 HBr 가스를 이용하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein HBr gas is used to etch the inorganic anti-reflection film. 제 1 항에 있어서,The method of claim 1, 상기 무기 반사방지막을 마스크로 이용하여 CxFy, CHxFy의 가스로 콘택홀 형성할 경우 자연적으로 제거되는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And forming a contact hole with a gas of C x F y and CH x F y by using the inorganic anti-reflection film as a mask. 제 1 항에 있어서,The method of claim 1, 상기 콘택홀 형성후, 인산을 이용하여 상기 무기 반사방지막을 제거하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And forming the inorganic antireflection film using phosphoric acid after the contact hole is formed. 제 1 항에 있어서,The method of claim 1, 상기 무기 반사방지막의 두께는 300∼600Å인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.And a thickness of the inorganic antireflection film is 300 to 600 kPa. 제 1 항에 있어서,The method of claim 1, 상기 폴리층의 두께는 1800∼2000Å인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The thickness of said poly layer is 1800-2000 micrometers, The contact hole formation method of the semiconductor element characterized by the above-mentioned. 제 1 항에 있어서,The method of claim 1, 상기 포토레지스트 패턴의 두께는 5000∼7000Å인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The thickness of said photoresist pattern is 5000-7000 GPa, The contact hole formation method of the semiconductor element characterized by the above-mentioned.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100457046B1 (en) * 2002-08-07 2004-11-10 삼성전자주식회사 Method for forming a contact in semiconductor device process
KR100710193B1 (en) * 2005-12-28 2007-04-20 동부일렉트로닉스 주식회사 Method for forming semi-conductor device
KR100827485B1 (en) * 2006-08-16 2008-05-06 동부일렉트로닉스 주식회사 Method for manufacturing in semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100457046B1 (en) * 2002-08-07 2004-11-10 삼성전자주식회사 Method for forming a contact in semiconductor device process
KR100710193B1 (en) * 2005-12-28 2007-04-20 동부일렉트로닉스 주식회사 Method for forming semi-conductor device
KR100827485B1 (en) * 2006-08-16 2008-05-06 동부일렉트로닉스 주식회사 Method for manufacturing in semiconductor device

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