KR100605872B1 - Semiconductor devices and A method for forming the same - Google Patents

Semiconductor devices and A method for forming the same Download PDF

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KR100605872B1
KR100605872B1 KR1020040050254A KR20040050254A KR100605872B1 KR 100605872 B1 KR100605872 B1 KR 100605872B1 KR 1020040050254 A KR1020040050254 A KR 1020040050254A KR 20040050254 A KR20040050254 A KR 20040050254A KR 100605872 B1 KR100605872 B1 KR 100605872B1
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fuse
insulating film
semiconductor device
forming
interlayer insulating
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KR20060001197A (en
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김형기
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

본 발명은 반도체소자 및 그 형성방법에 관한 것으로, 퓨즈의 리페어 공정을 용이하게 실시할 수 있도록 하기 위하여, 제1퓨즈와 제2퓨즈가 복층구조로 구비되고, 퓨즈부 오픈영역의 중앙부에서 상기 제1퓨즈와 이웃하는 제2퓨즈가 서로 교차하며 대칭되는 평면구조로 구비되는 퓨즈부를 형성하여 퓨즈의 리페어 공정시 공정마진을 확보하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same. In order to facilitate a repair process of a fuse, a first fuse and a second fuse are provided in a multilayer structure, and the first fuse and the second fuse are formed in the center of the open area of the fuse unit. It is a technology for securing a process margin during the repair process of the fuse by forming a fuse unit having a planar structure in which one fuse and a neighboring second fuse cross each other and are symmetrical, thereby improving the characteristics and reliability of the semiconductor device.

Description

반도체소자 및 그 형성방법{Semiconductor devices and A method for forming the same}Semiconductor devices and A method for forming the same

도 1 은 종래기술에 따른 반도체소자의 퓨즈부를 도시한 평면도.1 is a plan view showing a fuse unit of a semiconductor device according to the prior art.

도 2 는 본 발명에 따른 반도체소자의 퓨즈부를 도시한 평면도.2 is a plan view showing a fuse of the semiconductor device according to the present invention.

도 3a 내지 도 3g 는 상기 도 2 의 ⓐ-ⓐ 절단면을 따른 반도체소자의 형성방법을 도시한 단면도 및 평면도.3A to 3G are cross-sectional views and plan views illustrating a method of forming a semiconductor device along the cutting line ⓐ-ⓐ of FIG. 2.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11,21 : 퓨즈부 오픈영역 13 : 퓨즈11,21: Fuse part open area 13: Fuse

23 : 제1퓨즈 24 : 제1층간절연막23: first fuse 24: first interlayer insulating film

25 : 제2퓨즈 27 : 제2층간절연막25: second fuse 27: second interlayer insulating film

29 : 감광막패턴 100 : 반도체기판29: photosensitive film pattern 100: semiconductor substrate

본 발명은 반도체소자 및 그 형성방법에 관한 것으로, 특히 퓨즈 블로잉 ( fuse blowing )을 통한 리페어 공정의 특성을 향상시킬 수 있도록 하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a technology for improving the characteristics of a repair process through fuse blowing.                         

일반적으로, 퓨즈를 리페어 하는 방법은 동일한 층에 일정한 간격으로 라인 형태의 폴리실리콘층 또는 메탈층 등과 같이 도전층으로 이루어진 퓨즈를 레이저 광으로 조사하여 끊어줌으로써 리던던시에 어드레스를 할당하여 이루어진다. In general, a method of repairing a fuse is performed by assigning an address to redundancy by irradiating and cutting off a fuse made of a conductive layer such as a polysilicon layer or a metal layer in a line shape at regular intervals on the same layer by laser light.

반도체소자의 크기가 감소함에 따라 퓨즈간 간격도 줄어들기 때문에 하나의 퓨즈를 레이저로 절단하여 리페어할 때 레이저 광에 의해 이웃하는 퓨즈가 영향을 받게 됨으로써 에러를 유발하고 리페어가 필요한 어드레스를 할당할 수 없게 된다. As the size of semiconductor devices decreases, the gap between fuses also decreases, so when a fuse is cut with a laser and repaired, the neighboring fuses are affected by the laser light, causing errors and assigning addresses that require repair. There will be no.

도 1 은 종래기술에 따른 반도체소자를 도시한 평면도로서, 퓨즈부 오픈영역을 도시한 것이다. 1 is a plan view illustrating a semiconductor device according to the related art, and illustrates a fuse area open area.

도 1을 참조하면, 상기 퓨즈부 오픈영역(11)은 라인/스페이스 패턴 형태로 형성된 다수의 퓨즈(13)가 노출된 형태로 구비된다. Referring to FIG. 1, the fuse part open area 11 is provided in a form in which a plurality of fuses 13 formed in a line / space pattern form are exposed.

그러나, 반도체소자가 고집적화됨에 따라 상기 라인/스페이스 패턴의 선폭이 감소되고 퓨즈 리페어 공정을 실시하기 위하여 레이저로 상기 퓨즈(13)를 절단하는 경우 이웃하는 퓨즈(3)가 절단될 수 있어 예정된 리페어 공정을 용이하게 실시할 수 없다. However, as semiconductor devices are highly integrated, the line / space pattern has a reduced line width, and when the fuse 13 is cut by a laser to perform a fuse repair process, the neighboring fuse 3 may be cut, and thus a predetermined repair process may be performed. Cannot be easily carried out.

이상에서 설명한 바와 같이 종래기술에 따른 반도체소자 및 그 형성방법은, 반도체소자의 고집적화에 따른 라인/스페이스 형태의 퓨즈가 이웃하는 퓨즈가 근접되어 리페어 공정시 이웃하는 퓨즈를 손상시킬 수 있어 반도체소자의 리페어에 필요한 어드레스를 할당 할 수 없게 된다. As described above, the semiconductor device and the method of forming the same according to the related art are adjacent to fuses adjacent to the line / space type fuse due to the high integration of the semiconductor devices, which may damage neighboring fuses during the repair process. The address required for the repair cannot be assigned.

본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, 서로 다른 층에 구비되는 두 개의 퓨즈가 퓨즈부 오픈 영역 내에서 교차하여 서로 대칭인 형태로 형성됨으로써 고집적화된 반도체소자의 퓨즈 리페어 공정시 공정마진을 확보할 수 있도록 하는 반도체소자 및 그 형성방법을 제공하는데 그 목적이 있다. The present invention is to solve the problem according to the prior art, two fuses provided in different layers are formed in a symmetrical form to cross each other in the fuse area open area during the fuse repair process of the highly integrated semiconductor device SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of forming the same, which ensure a margin.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자는, In order to achieve the above object, a semiconductor device according to the present invention,

제1퓨즈와 제2퓨즈가 복층구조로 구비되고,The first fuse and the second fuse is provided in a multilayer structure,

퓨즈부 오픈영역의 중앙부에서 상기 제1퓨즈와 이웃하는 제2퓨즈가 서로 교차하며 대칭되는 평면구조로 구비되는 것과,The first fuse and the neighboring second fuse in the central portion of the fuse portion open area is provided with a planar structure that cross each other and symmetrical,

상기 제1퓨즈와 제2퓨즈는 플레이트전극의 TiN, 플레이트전극의 폴리실리콘 및 비트라인 도전층 중에서 선택된 임의의 한가지로 구비되는 것과,The first fuse and the second fuse is provided with any one selected from TiN of the plate electrode, polysilicon of the plate electrode and the bit line conductive layer,

상기 제1퓨즈와 제2퓨즈의 표면은 각각 2500 ∼ 5000 Å 두께의 절연막이 구비되되, The surface of the first fuse and the second fuse is provided with an insulating film of 2500 ~ 5000 Å thickness, respectively,

상기 절연막은 산화막이나 질화막으로 구비되거나, 상기 절연막은 HDP 산화막, PE-TEOS 산화막, SOG 산화막, BPSG 산화막, SiON 막 및 이들의 조합으로 이루어지는 군에서 선택된 임의의 한가지로 구비되는 것을 특징으로 한다. The insulating film may be provided as an oxide film or a nitride film, or the insulating film may be provided with any one selected from the group consisting of HDP oxide film, PE-TEOS oxide film, SOG oxide film, BPSG oxide film, SiON film, and combinations thereof.

또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 형성방법은, In addition, the method of forming a semiconductor device according to the present invention to achieve the above object,

반도체기판 상에 제1퓨즈를 형성하고 그 상부에 제1층간절연막을 형성하는 공정과,Forming a first fuse on the semiconductor substrate and forming a first interlayer insulating film thereon;

상기 제1층간절연막 상부에 제2퓨즈를 패터닝하되, 퓨즈부 오픈영역의 중앙 부에서 상기 제1퓨즈와 이웃하는 제2퓨즈가 서로 교차하며 대칭되는 평면구조로 패터닝하는 공정과,Patterning a second fuse on the first interlayer insulating layer, and patterning the second fuse in a planar structure in which the first fuse and the second fuse adjacent to each other cross each other and are symmetrical at a central portion of an open area of the fuse part;

전체표면상부에 제2층간절연막을 형성하고 소정두께 식각하는 공정과,Forming a second interlayer insulating film over the entire surface and etching a predetermined thickness;

상기 제1퓨즈 상측의 제2층간절연막 및 소정두께의 제1층간절연막을 식각하는 공정을 포함하는 것을 특징으로 한다. And etching the second interlayer insulating film on the upper side of the first fuse and the first interlayer insulating film having a predetermined thickness.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2 는 본 발명에 따른 반도체소자의 퓨즈부를 도시한 평면도이다. 2 is a plan view illustrating a fuse of a semiconductor device according to the present invention.

상기 도 2 는 이웃하는 두 개의 퓨즈(23,25)가 퓨즈부 오픈영역(21) 내에서 서로 교차되어 대칭되는 형태로 구비되는 것을 도시한다. FIG. 2 shows that two neighboring fuses 23 and 25 are provided in a symmetrical form in the fuse part open area 21.

도 3a 내지 도 3g 는 본 발명의 실시예에 따른 반도체소자의 형성방법을 도시한 평면도 및 단면도로서, 상기 단면도는 상기 도 2 의 ⓐ-ⓐ 절단면을 따라 도시한 것이다. 3A to 3G are plan and cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention. The cross-sectional view is taken along the line ⓐ-ⓐ of FIG. 2.

도 3a 내지 도 3c 를 참조하면, 반도체기판(100) 상에 제1퓨즈(23)를 패터닝하고 전체표면상부에 5000 Å 이상의 두께로 제1층간절연막(24)을 형성한다. 3A through 3C, the first fuse 23 is patterned on the semiconductor substrate 100, and a first interlayer insulating film 24 is formed on the entire surface of the semiconductor substrate 100 to a thickness of 5000 GPa or more.

그 다음, 상기 제1층간절연막(24) 상에 제2퓨즈(25)를 형성한다. Next, a second fuse 25 is formed on the first interlayer insulating film 24.

여기서, 상기 제2퓨즈(25)는 퓨즈부 오픈영역(21)의 중앙부에서 이웃하는 상기 제1퓨즈(23)와 서로 교차하며 서로 대칭되는 평면구조로 패터닝된 것이다. Here, the second fuse 25 is patterned in a planar structure crossing each other with the neighboring first fuses 23 at the center of the fuse-open area 21 and being symmetrical with each other.

도 3d를 참조하면, 상기 제2층간절연막(27)을 식각하되, 상기 제2퓨즈(25) 상부에 2500 ∼ 5000 Å 두께만을 남기며 실시한 것이다. Referring to FIG. 3D, the second interlayer insulating layer 27 is etched, leaving only 2500 to 5000 mm thick on the second fuse 25.

도 3e 내지 도 3g 를 참조하면, 상기 제2층간절연막(27) 상부에 감광막패턴(29)을 형성한다. 3E to 3G, a photosensitive film pattern 29 is formed on the second interlayer insulating film 27.

이때, 상기 감광막패턴(29)은 퓨즈용 마스크(미도시)를 이용한 노광 및 현상공정으로 형성한 것으로, 상기 제2퓨즈(25)의 측면으로 2500 ∼ 5000 Å 두께의 제2층간절연막(27)을 남길 수 있도록 형성된 것이다. In this case, the photosensitive film pattern 29 is formed by an exposure and development process using a mask for fuse (not shown), and the second interlayer insulating film 27 having a thickness of 2500 to 5000 으로 toward the side of the second fuse 25. It is formed to leave.

그 다음, 상기 감광막패턴(29)을 마스크로 하여 상기 제2층간절연막(27) 및 제1층간절연막(24)을 식각하여 상기 제1퓨즈(23) 상부에 2500 ∼ 5000 Å 두께의 제1층간절연막(24)만을 남긴다. Next, the second interlayer insulating film 27 and the first interlayer insulating film 24 are etched using the photosensitive film pattern 29 as a mask, and the first interlayer having a thickness of 2500 to 5000 m is disposed on the first fuse 23. Only the insulating film 24 is left.

그 다음, 상기 감광막패턴(29)을 제거하여 퓨즈의 리페어 공정을 용이하게 실시할 수 있도록 공정마진을 확보한다. Next, the process margin is secured to remove the photoresist pattern 29 so that the fuse repair process can be easily performed.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자 및 그 형성방법은, 퓨즈의 리페어 공정시 퓨즈부 오픈영역으로 노출되는 퓨즈의 절단시 공정 마진을 확보하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the semiconductor device and the method for forming the same according to the present invention improve process characteristics and reliability of the semiconductor device by securing a process margin during cutting of the fuse exposed to the open area of the fuse unit during the repair process of the fuse, and thereby the semiconductor. It provides an effect that enables high integration of the device.

Claims (6)

제1퓨즈와 제2퓨즈가 복층구조로 구비되고,The first fuse and the second fuse is provided in a multilayer structure, 퓨즈부 오픈영역의 중앙부에서 상기 제1퓨즈와 이웃하는 제2퓨즈가 서로 교차하며 대칭되는 평면구조로 구비되는 것을 특징으로 하는 반도체소자.The semiconductor device according to claim 1, wherein the first fuse and a neighboring second fuse intersect with each other and are symmetrical with each other at a central portion of the fuse part open area. 제 1 항에 있어서, The method of claim 1, 상기 제1퓨즈와 제2퓨즈는 플레이트전극의 TiN, 플레이트전극의 폴리실리콘 및 비트라인 도전층 중에서 선택된 임의의 한가지로 구비되는 것을 특징으로 하는 반도체소자.The first fuse and the second fuse is a semiconductor device, characterized in that any one selected from TiN of the plate electrode, polysilicon of the plate electrode and the bit line conductive layer. 제 1 항에 있어서, The method of claim 1, 상기 제1퓨즈와 제2퓨즈의 표면은 각각 2500 ∼ 5000 Å 두께의 절연막이 구비되는 것을 특징으로 하는 반도체소자.The surface of the first fuse and the second fuse is a semiconductor device, characterized in that each provided with an insulating film of 2500 to 5000 Å thickness. 제 3 항에 있어서, The method of claim 3, wherein 상기 절연막은 산화막이나 질화막으로 구비되는 것을 특징으로 하는 반도체소자.The insulating film is a semiconductor device, characterized in that provided as an oxide film or a nitride film. 제 3 항에 있어서, The method of claim 3, wherein 상기 절연막은 HDP 산화막, PE-TEOS 산화막, SOG 산화막, BPSG 산화막, SiON 막 및 이들의 조합으로 이루어지는 군에서 선택된 임의의 한가지로 구비되는 것을 특징으로 하는 반도체소자.The insulating film is any one selected from the group consisting of HDP oxide film, PE-TEOS oxide film, SOG oxide film, BPSG oxide film, SiON film and combinations thereof. 반도체기판 상에 제1퓨즈를 형성하고 그 상부에 제1층간절연막을 형성하는 공정과,Forming a first fuse on the semiconductor substrate and forming a first interlayer insulating film thereon; 상기 제1층간절연막 상부에 제2퓨즈를 패터닝하되, 퓨즈부 오픈영역의 중앙부에서 상기 제1퓨즈와 이웃하는 제2퓨즈가 서로 교차하며 대칭되는 평면구조로 패터닝하는 공정과,Patterning a second fuse on the first interlayer insulating layer, and patterning the second fuse in a planar structure in which the first fuse and the second fuse adjacent to each other cross each other and are symmetrical at a central portion of an open area of the fuse part; 전체표면상부에 제2층간절연막을 형성하고 소정두께 식각하는 공정과,Forming a second interlayer insulating film over the entire surface and etching a predetermined thickness; 상기 제1퓨즈 상측의 제2층간절연막 및 소정두께의 제1층간절연막을 식각하는 공정을 포함하는 반도체소자의 형성방법.And etching the second interlayer insulating film on the upper side of the first fuse and the first interlayer insulating film having a predetermined thickness.
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