CN102263011B - Semiconductor structure manufacturing method - Google Patents
Semiconductor structure manufacturing method Download PDFInfo
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- CN102263011B CN102263011B CN2010101880284A CN201010188028A CN102263011B CN 102263011 B CN102263011 B CN 102263011B CN 2010101880284 A CN2010101880284 A CN 2010101880284A CN 201010188028 A CN201010188028 A CN 201010188028A CN 102263011 B CN102263011 B CN 102263011B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The invention discloses a semiconductor structure manufacturing method, which comprises the following steps of: providing a substrate, wherein the substrate is divided into a fuse region with a fuse structure and a bonding pad region with a bonding pad, the fuse structure comprises a first anti-etching layer on a surface layer and the bonding pad comprises a second anti-etching layer on the surface layer; forming a protective layer; forming a photoresist layer on the protective layer, patterning the photoresist layer and forming an opening in the photoresist layer, wherein the opening exposes the protective layer at a part of a bonding pad position, at a fuse structure position and on the two sides of the fuse structure position; performing primary etching until the first anti-etching layer of the fuse region and the second anti-etching layer of the bonding pad region are exposed at the same time; and performing secondary etching to remote the second anti-etching layer on the surface layer of the bonding pad and the first anti-etching layer on the surface layer of the fuse structure. In the method, a process of performing single photoetching and then sequentially performing the primary and secondary etching is adopted to reduce photoetching times.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly the manufacture method of a kind of weld pad and fuse-wires structure.
Background technology
Along with the improvement of semiconductor process technology and the raising of integrated circuit complexity, semiconductor components and devices is affected by various defective also more easily, and the inefficacy of single components and parts such as transistor or memory cell, tends to cause the functional defect of whole integrated circuit.Common solution is to form some connecting lines that can fuse in integrated circuit, and fuse (fuse) structure namely is to guarantee the availability of integrated circuit.
Generally speaking, fuse-wires structure be used for to connect the redundant circuit (redundancycircuit) of integrated circuit, when defective appears in circuit, with fuse failure, repairs or replaces the circuit that produces defective with redundant circuit.Fuse-wires structure when memory chip production is finished, if wherein there is partial memory cell the function problem to occur, just can replace with redundant memory cell by fuse-wires structure in being usually used in internal memory, realizes the purpose of repairing.In addition, fuse-wires structure also is common in the programmable circuit, according to user's needs, uses fuse-wires structure that the standard logical unit in the circuit is programmed, in order to realize specific function.
Chinese invention patent discloses CN1979817A number and discloses existing a kind of cross-sectional view that comprises the semiconductor structure of weld pad and fuse-wires structure.Please refer to Fig. 1; substrate 100 comprises pad zone 101 and fuse region 103; described pad zone 101 is used to form weld pad 102; described fuse region 103 is used to form fuse-wires structure 104; being formed with the substrate 100 formation protective layers 106 of weld pad 102 with fuse-wires structure 104, wherein be formed with metal-oxide semiconductor transistor construction, wire or other semiconductor elements (not shown) in the substrate 100.Then; carry out Twi-lithography technique and twice etching technique; wherein a photoetching and etching technics comprise and protect with photoresist fuse region 103, form opening 108 in the protective layer 106 of pad zone 101, expose the technique such as weld pad 102, and another time photoetching and etching technics comprise protect with photoresist pad zone 101, in the protective layer 106 of fuse region 103, form opening 110 and stay partial protection layer 106 on fuse-wires structure 104 with as the follow-up technique such as using of laser preparing of carrying out.
Owing to when forming opening 108 with opening 110, need to carry out Twi-lithography and adopting the twice photomask, having consumed more time and production cost.
Therefore, need a kind of new fuse-wires structure and the manufacture method of weld pad, effectively to solve the problems of the technologies described above.
Summary of the invention
The purpose that the present invention solves is to provide a kind of manufacture method of semiconductor structure, to reduce process complexity.
For achieving the above object, the invention provides a kind of manufacture method of semiconductor structure, comprising:
Substrate is provided, and described substrate is divided into fuse region and pad zone, and described fuse region is formed with fuse-wires structure, described pad zone is formed with weld pad, described fuse-wires structure and weld pad interval, described fuse-wires structure comprise first etch-resistant layer on top layer, and described weld pad comprises second etch-resistant layer on top layer;
Form protective layer, described protective layer covers weld pad, fuse-wires structure and substrate;
Form photoresist layer and carry out graphically at protective layer, in described photoresist layer, form opening, described opening expose the protective layer of part of solder pads position, described opening also expose the fuse-wires structure position and outside the protective layer of two side portions;
Carry out the etching first time, until fuse region exposes the first etch-resistant layer, pad zone exposes the second etch-resistant layer simultaneously;
Carry out the etching second time, second etch-resistant layer on the top layer of removal weld pad and first etch-resistant layer on fuse-wires structure top layer.
Optionally, described first time etching to the etching speed of protective layer greater than the etching speed to weld pad and fuse-wires structure, described second time etching to the etching speed of weld pad and fuse-wires structure greater than the etching speed to substrate or protective layer.
Optionally, described first time, etching adopted CF
4, O
2, CHF
3Mist with Ar.
Optionally, CF
4Gas supply flow be 780～820sccm, O
2Gas supply flow be 8～12sccm, CHF
3Gas supply flow be 18～22sccm, the gas supply flow of Ar is 80～120sccm; Supply gas pressure is about 150mTorr.
Optionally, described second time, etching adopted Cl
2With BCl
3Mist.
Optionally, Cl
2Gas supply flow be 25～35sccm, BCl
3Gas supply flow be 35～45sccm; Supply gas pressure is about 8mTorr.
Optionally, described first time, etching adopted different etching machine bench to carry out with etching for the second time, and described first time, etching adopted the etching machine bench of etching insulator to carry out, and described first time, etching adopted the etching machine bench of etching metal to carry out.
Optionally, described the first etch-resistant layer and the second etch-resistant layer adopt antireflection material.
Optionally, described first anti-etching and the second etch-resistant layer employing titanium nitride material.
Optionally, the protective layer thickness that described weld pad and fuse-wires structure top covers is identical, so that outside weld pad and fuse-wires structure are exposed to simultaneously during etching for the first time.
Compared with prior art; technique scheme has the following advantages: by forming respectively the first etch-resistant layer and the second etch-resistant layer at fuse-wires structure and weld pad top layer; form the protective layer that exposes simultaneously the part of solder pads position in the photoresist layer on protective layer; and the fuse-wires structure position and outside the opening of protective layer of two side portions; an i.e. step photoetching forms pad zone opening and fuse region opening simultaneously; in follow-up etching process, fuse region and pad zone are carried out etching simultaneously like this; namely only adopted a photoetching then to carry out successively the technique of twice etching; reduce the photoetching number of times, saved time and cost.
To fuse region and pad zone etching the time; utilize different etching gas to the high selectivity of weld pad, fuse-wires structure and protective layer etching; Avoids or reduces is to the weld pad that do not have photoresist protection or the destruction of fuse-wires structure when the etching protective layer; Avoids or reduces is to the destruction of the protective layer that do not have photoresist protection when etching weld pad and fuse-wires structure, thereby guarantees the performance of whole semiconductor structure.
Description of drawings
Fig. 1 is a kind of generalized section with existing semiconductor structure of weld pad and fuse-wires structure;
Fig. 2 is the schematic flow sheet according to the semiconductor structure of the formation of the specific embodiment of the invention;
Fig. 3 to 8 is the cross-sectional view according to the semiconductor structure of the formation of the specific embodiment of the invention.
Embodiment
In the forming process of weld pad and fuse-wires structure, in order to improve device reliability, usually need to carry out Twi-lithography technique and etching technics, once be to protect with photoresist fuse region, in the protective layer of pad zone, form opening, expose weld pad, then divest the photoresist of fuse region; Another time is to protect with photoresist pad zone, forms opening in the protective layer of fuse region, and stays partial protection layer on fuse-wires structure, with as follow-up usefulness of carrying out laser preparing, then divests the photoresist of pad zone.Owing to need to carry out Twi-lithography and using the twice photomask, needing to consume more time and production cost.
For the problems referred to above; the present invention at the spin coating photoresist layer after protective layer; on same mask plate, form simultaneously the figure of weld pad and fuse-wires structure; utilize a photoetching; in photoresist layer, form simultaneously the figure of weld pad and fuse-wires structure, utilize two kinds of gas with various etching protective layers, then utilize the second board etching weld pad and fuse-wires structure; thereby avoid carrying out the photoetching second time, simplify production procedure and Decrease production cost.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
Fig. 2 provides the schematic flow sheet according to the semiconductor structure of the formation of the specific embodiment of the invention, comprising:
Step S1: substrate is provided, described substrate is divided into fuse region and pad zone, described fuse region is formed with fuse-wires structure, described pad zone is formed with weld pad, described fuse-wires structure and weld pad interval, described fuse-wires structure comprises first etch-resistant layer on top layer, and described weld pad comprises second etch-resistant layer on top layer;
Step S2: form protective layer, described protective layer covers weld pad, fuse-wires structure and substrate;
Step S3: form photoresist layer and carry out graphically at protective layer, in described photoresist layer, form opening, described opening expose the protective layer of part of solder pads position, described opening also expose the fuse-wires structure position and outside the protective layer of two side portions;
Step S4: carry out the etching first time, until fuse region exposes the first etch-resistant layer, pad zone exposes the second etch-resistant layer simultaneously;
Step S5: carry out the etching second time, second etch-resistant layer on the top layer of removal weld pad and first etch-resistant layer on fuse-wires structure top layer.
Be elaborated below in conjunction with accompanying drawing, at first, execution in step S1: substrate is provided, described substrate is divided into fuse region and pad zone, described fuse region is formed with fuse-wires structure, and described pad zone is formed with weld pad, described fuse-wires structure and weld pad interval, described fuse-wires structure comprises first etch-resistant layer on top layer, and described weld pad comprises second etch-resistant layer on top layer.Accordingly, please refer to Fig. 3, substrate 200 comprises pad zone 201 and fuse region 203, and pad zone 201 tops of substrate 200 are formed with weld pad 202, and fuse region 203 tops of substrate 200 are formed with fuse-wires structure 204.In the present embodiment, described weld pad 202 and fuse-wires structure 204 with physical vapour deposition (PVD) (PVD) process deposits above substrate 200.
The material of described substrate 200 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, and described substrate 200 can also be epitaxial layer structure on silicon-on-insulator (SOI, Silicon On Insulator) structure or the silicon.
The circuit that described weld pad 202 is used for forming in the substrate is electrically connected with extraneous other interface circuits, it is not the part of fuse-wires structure, in actual process, weld pad can be made with fuse-wires structure, and therefore the present invention is directed to the technology of making simultaneously weld pad and fuse-wires structure carries out this improvement.Described weld pad 202 comprises first conductive layer 241 and the first etch-resistant layer 242 that covers the first conductive layer 241 of lower floor, and described fuse-wires structure 204 comprises second conductive layer 211 and the second etch layer 212 that covers the second conductive layer 211 of lower floor.
Further, described the first conductive layer 241, the second conductive layer 211 adopt the same layer material to form, and namely the two thickness is identical, and material can be comprised of copper, aluminium or albronze, so that weld pad 202 has good electric conductivity with fuse-wires structure 204.In the present embodiment, the first conductive layer 241, the second conductive layer 211 are 1% albronze for copper content.
Described the first etch-resistant layer 242, the second etch-resistant layer 212 adopt the same layer material to form, be that the two thickness is identical, further, described the first etch-resistant layer 242 and the second etch-resistant layer 212 can adopt the antireflection material preparation, again further, described the first etch-resistant layer 242 and the second etch-resistant layer 212 can be titanium nitride (TiN).
Described weld pad 202 is 2000 to 12000 with the thickness of fuse-wires structure 204
Be preferably 6000 to 10000
Preferably, described weld pad 202 is 8000 with the thickness of fuse-wires structure 204
Wherein, described the first etch-resistant layer 242 accounts for 1/11～1/9 of whole weld pad 202 thickness, is preferably 1/10, and described the second etch-resistant layer 212 accounts for 1/11～1/9 of whole fuse-wires structure 204 thickness, is preferably 1/10.
It should be noted that; why cover the second etch-resistant layer 212 at the second conductive layer 211; mainly be to differ enough large for the etching speed for specific etching machine bench or etching gas between the material of utilizing protective layer 206 and the second etch-resistant layer 212; be that they have larger etching selection ratio; the destruction of etching ion pair weld pad 202 and fuse-wires structure 204 in the time of can reducing etching protective layer 206 like this; when reducing simultaneously etching the second etch-resistant layer 212 to protective layer 206 etching with substrate 200; preventing from being corrupted to other semiconductor element below the substrate 200, and can in a step photoetching, form simultaneously the opening figure of fuse region and pad zone.
Execution in step S2: form protective layer, described protective layer covers weld pad, fuse-wires structure and substrate.Accordingly, please refer to Fig. 4, form protective layer 206, described protective layer 206 covers weld pad 202, fuse-wires structure 204 and substrate 200.The material of described protective layer 206 is selected from silica, organic silicate glass, Pyrex etc., is preferably silica in the present embodiment, and its manufacture method is chemical vapour deposition (CVD) (CVD).The thickness of described protective layer 206 depends primarily on the concrete structure of weld pad in the actual process 202 and fuse-wires structure 204, and in the present embodiment, the thickness of protective layer 206 between 15000 dusts, is preferably 8000～10000 between 5000 dusts
Execution in step S3: form photoresist layer and carry out graphical at protective layer; in described photoresist layer, form opening, described opening expose the protective layer of part of solder pads position, described opening also expose the fuse-wires structure position and outside the protective layer of two side portions.Specifically please refer to Fig. 5; the step of described formation photoresist layer mainly comprises: apply photoresist (Photo Resist at protective layer 206; PR) and toast; coating thickness is 10 nanometer to 10000 nanometers, and baking temperature is that 50 degrees centigrade to 250 degrees centigrade, stoving time are 10 seconds to 1000 seconds.
Then utilize mask plate that photoresist is exposed, develops, namely photoresist is carried out graphically, thus formation photoresist layer 220 as shown in Figure 5.After graphical, described photoresist layer 220 all is formed with opening at pad zone 201 and fuse region 203, the opening of described pad zone 201 exposes the protective layer of part of solder pads 202 positions, and with reference to Fig. 5, the subregion Q3 of weld pad 202 end positions is protected by photoresist layer 220; The opening of described fuse region 203 exposes the protective layer of fuse-wires structure 204 position Q1 part, and simultaneously, the opening of described fuse region 203 also exposes the protective layer zone Q2 of two side portions outside fuse-wires structure 204 positions.
Execution in step S4: carry out the etching first time, until fuse region exposes the first etch-resistant layer, pad zone exposes the second etch-resistant layer simultaneously.Specifically please refer to Fig. 6; after carrying out the etching first time; form the first opening 208 at pad zone 201; form the second opening 210 and groove 209 at fuse region 203; described the first opening 208 exposes the first etch-resistant layer 242; described the second opening 210 and groove 209 expose the part substrate 200 outside the second etch-resistant layer 212 and fuse-wires structure 204 both sides, and the protective layer of the protective layer zone Q2 that is not namely protected by photoresist layer 220 also is etched away.
Among the present invention; when the first time, etching proceeded to the second upper etch-resistant layer 212 of fuse-wires structure 204 and weld pad 202 or the first etch-resistant layer 242; needing to continue etching goes down; until expose substrate 200; the most deeply degree that is etching reaches the least significant end of fuse-wires structure, and for pad zone 201 and since for the first time the etching speed of the etching ion pair protective layer 206 in the etching much larger than the etching speed to the first etch-resistant layer 242; therefore, be equivalent to stop at the first etch-resistant layer 242.
In the present embodiment, protective layer 206 thickness of pad zone 201 and fuse region 203 are identical, certainly, even if protective layer 206 thickness in two districts are not identical, also can not destroy enforcement of the present invention.Specifically the reasons are as follows: when protective layer 206 thickness of pad zone 201 and fuse region 203 are not identical, if the protective layer 206 of pad zone 201 is thinner, outside the first etch-resistant layer 242 of pad zone 201 can at first be exposed to, because the etching speed of etching ion pair the first etch-resistant layer 242 in the etching is much smaller than protective layer 206 for the first time, thereby the protective layer 206 that covers the fuse region 203 of thicker protective layer 206 is etched away, and when exposing substrate 200, be exposed to first outer the first etch-resistant layer 242 and also only can be etched away seldom, can not affect the carrying out of later step; Vice versa.
What need explain is, described first time, etching can be selected from the etching machine bench of etching insulator commonly used, just to select as far as possible to etch-resistant layer 212 etch rates slow and fast to protective layer 206 etch rates.Here no longer this class board is enumerated one by one.
In the present embodiment, described first time, the etching machine bench of etching was the RIE board that is suitable for dry etching, and main etching gas is CF
4, O
2, CHF
3Mist with Ar.Wherein, CF
4Gas supply flow be 780～820sccm, O
2Be 8～12sccm, CHF
3Be 18～22sccm, Ar is 80～120sccm; Pressure is about 150mTorr in the etching cavity; Etch period is determined according to the thickness of protective layer to be etched 206, if protective layer thickness is 8000～10000
Etch period is 130～160s.Described etching gas to protective layer 206 and to the etching selection ratio of the first etch-resistant layer 242, the second etch-resistant layer 212 greater than 10: 1.
Execution in step S5: carry out the etching second time, second etch-resistant layer on the top layer of removal weld pad and first etch-resistant layer on fuse-wires structure top layer.
Because sheltering of photoresist layer 220 forms cross-section structure as shown in Figure 7.Please refer to shown in Figure 7ly, part the first etch-resistant layer 242 that is exposed to the weld pad 202 under the etching ionic environment has been etched away, exposes the first conductive layer 241, to weld mutually with the pin of outside in follow-up encapsulation process; The second etch-resistant layer 212 of fuse region 203 is removed simultaneously, exposes the second conductive layer 211 of fuse-wires structure 204.In the etching, can remove the substrate 200 that part exposes for the second time, thereby strengthen the degree of depth of groove 209.
Need to prove; protective layer 206 outside fuse-wires structure 204 both sides is etched away and the purpose that forms groove 209 is to isolate the protective layer 206 of fuse-wires structure 204 and its both sides; preventing that the residual sheet that forms after fuse-wires structure 204 fusing from sticking on the both sides protective layer 206 causes short circuit; the protective layer 206 of therefore isolating fuse-wires structure 204 and its both sides can increase the success rate of repairing.Simultaneously, different from fuse-wires structure 204, weld pad 202 two end portions embed in the protective layer 206, can increase like this adhesion between weld pad 202 and the protective layer 206, prevent that weld pad 202 breaks away from semiconductor structure 20.
It should be noted that the etching selection of metal pair insulator is higher in described second time of the etching.That is to say; for the second time the etching gas in the etching to the etching speed of the first etch-resistant layer 242, the second etch-resistant layer 212 much larger than the etching speed to substrate 200 or protective layer 206; the substrate 200 that can prevent like this second groove 209 belows is subject to for the second time etching impact greatly, affects the performance of the element of substrate 200 belows.
What need explain is, described second time, etching can adopt the board that is usually used at present the etching metal to carry out, and described second time, etching will be selected as far as possible to substrate 200 etch rates slow etching machine bench or etching gas.Here no longer this class board is enumerated one by one.
As an optimisation technique scheme, be etched in the RIE board that is suitable for dry etching for the second time and carry out, the second etching gas is Cl
2With BCl
3Mist.Wherein, Cl
2Gas supply flow be 25～35sccm, BCl
3Be 35～45sccm; The interior pressure of etching cavity is 8mTorr approximately; Etch period is determined according to the thickness of the first etch-resistant layer 241 to be etched and the second etch-resistant layer 212, if the first etch-resistant layer 241 and the second etch-resistant layer 212 thickness are 600～1000
Etch period is for being 13～15s.Under above-mentioned etching condition, in the etching, the etching selection ratio of the first etch-resistant layer 241 and 212 pairs of protective layers 206 of the second etch-resistant layer is greater than 5 for the second time.
In addition, described the first etching machine bench can be the different similar board of the identical just etching gas of equipment from described the second etching machine bench, more preferably, also can adopt different platform, can avoid like this in etching process, changing the process of etching gas, shorten the process time.
Step S6: carry out subsequent treatment.After described etch process, also can carry out the step of stripping photolithography glue-line 206, and the surface of the semiconductor structure 20 after the etching is cleaned, remove etch residue and particulate, thereby form the semiconductor structure as shown in Figure 8 20 that satisfies the demands.
As mentioned above, the present invention forms the figure of weld pad and fuse-wires structure simultaneously on same mask plate, utilize a photoetching, in photoresist layer, form simultaneously the figure of weld pad and fuse-wires structure, adopt the single photoetching then to carry out successively the technique of twice etching, reduce the photoetching number of times, saved time and cost.Utilize simultaneously different etching gas for the high selectivity of weld pad, fuse-wires structure and protective layer; Avoids or reduces is to the weld pad that do not have photoresist protection or the destruction of fuse-wires structure when the etching protective layer; when etching weld pad and fuse-wires structure, avoid or less of the protective layer that do not have photoresist protection and the destruction of substrate, thereby guarantee the performance of whole semiconductor structure.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the manufacture method of a semiconductor structure comprises:
Substrate is provided, and described substrate is divided into fuse region and pad zone, and described fuse region is formed with fuse-wires structure, described pad zone is formed with weld pad, described fuse-wires structure and weld pad interval, described fuse-wires structure comprise first etch-resistant layer on top layer, and described weld pad comprises second etch-resistant layer on top layer;
Form protective layer, described protective layer covers weld pad, fuse-wires structure and substrate;
Form photoresist layer and carry out graphically at protective layer, in described photoresist layer, form opening, described opening expose the protective layer of part of solder pads position, described opening also expose the fuse-wires structure position and outside the protective layer of two side portions;
Carry out the etching first time, until fuse region exposes the first etch-resistant layer, pad zone exposes the second etch-resistant layer simultaneously;
Carry out the etching second time, second etch-resistant layer on the top layer of removal weld pad and first etch-resistant layer on fuse-wires structure top layer.
2. manufacture method as claimed in claim 1; it is characterized in that: described first time etching to the etching speed of protective layer greater than the etching speed to weld pad and fuse-wires structure, described second time etching to the etching speed of weld pad and fuse-wires structure greater than the etching speed to substrate or protective layer.
3. manufacture method as claimed in claim 1 is characterized in that: described etching employing first time CF
4, O
2, CHF
3Mist with Ar.
4. manufacture method as claimed in claim 3 is characterized in that: CF
4Gas supply flow be 780～820sccm, O
2Gas supply flow be 8～12sccm, CHF
3Gas supply flow be 18～22sccm, the gas supply flow of Ar is 80～120sccm; Supply gas pressure is 150mTorr.
5. manufacture method as claimed in claim 1 is characterized in that: described etching employing second time Cl
2With BCl
3Mist.
6. manufacture method as claimed in claim 5 is characterized in that: Cl
2Gas supply flow be 25～35sccm, BCl
3Gas supply flow be 35～45sccm; Supply gas pressure is 8mTorr.
7. manufacture method as claimed in claim 1, it is characterized in that: described first time, etching adopted different etching machine bench to carry out with etching for the second time, the etching machine bench of described etching employing first time etching insulator carries out, and the etching machine bench of described etching employing second time etching metal carries out.
8. manufacture method as claimed in claim 1 is characterized in that: described the first etch-resistant layer and the second etch-resistant layer employing antireflection material.
9. manufacture method as claimed in claim 1 is characterized in that: described the first etch-resistant layer and the second etch-resistant layer employing titanium nitride material.
10. manufacture method as claimed in claim 1 is characterized in that: described weld pad is identical with the protective layer thickness that the fuse-wires structure top covers, so that outside weld pad and fuse-wires structure are exposed to simultaneously during etching for the first time.
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| CN1979817A (en) * | 2005-12-01 | 2007-06-13 | 联华电子股份有限公司 | Semiconductor structure and its preparing process |
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| KR101055857B1 (en) * | 2008-07-09 | 2011-08-09 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device having a fuse and a pad |
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| CN1893018A (en) * | 2005-06-30 | 2007-01-10 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN1979817A (en) * | 2005-12-01 | 2007-06-13 | 联华电子股份有限公司 | Semiconductor structure and its preparing process |
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