JPH08204015A - Production of semiconductor device and semiconductor device - Google Patents

Abstract

PURPOSE: To prevent a silicon substrate from being exposed during etching for making an opening and suppress the current leakage between a fuse wiring and silicon substrate by forming a second insulation film before forming a cover insulation film, etc., and forming the cover insulation film, etc., thereafter. CONSTITUTION: A fuse wiring 3 is formed on a first insulation film 2 formed on a silicon substrate 1, and a second insulation film 8 is formed in such an area that the opening area to be opened in a fourth insulation film (cover insulation film) to be formed thereon is included and in a larger area than the area. Then, third insulation films 10 and 11 is formed on the substrate 1, covering the first and second insulation films 2 and 8 and an aluminum pad 4 is formed thereon, then a cover insulation film 5 is formed on the substrate 1, covering the pad 4 and wiring 3. Further, the cover and third insulation films 5, 10 and 11 on the pad 4 and wiring 3 are opened so as to expose the pad 4 and wiring 3. Thus the substrate 1 can be prevented from being exposed, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a redundant circuit for cutting a fuse with a laser and a semiconductor device manufactured by the method.

[0002]

2. Description of the Related Art The above semiconductor device uses polysilicon wiring or polycide wiring as fuse wiring.

When the fuse wiring is cut by irradiating the laser light, it is necessary to open a window in the cover insulating film on the fuse wiring in order to prevent the strength of the laser light from being lowered by the cover insulating film. The process of opening a window in the cover insulating film on the fuse wiring is performed using aluminum (A
l) The number of steps is reduced by using the same lithography process as the process of opening a window in the cover insulating film on the pad.

Next, a conventional example of a process of opening a window in the cover insulating film on the fuse wiring and the aluminum pad will be described. 3A and 3B are explanatory views of a conventional example.

FIG. 3A is a plan view and FIG. 3B is a sectional view taken along the line AA. In the figure, 1 is a silicon (Si) substrate, 2 is a field insulating film (field oxide film), 3 is a fuse wiring, polycide wiring or polysilicon wiring, 4 is an aluminum pad, 5 is a cover insulating film, and 6 is on the fuse wiring. , 7 is an opening on the aluminum pad, 10 is an interlayer insulating film, and is silicon dioxide (CVDSiO ₂ ) formed by vapor phase growth.
The film, 11 is an interlayer insulating film, which is a phosphorus-containing phosphosilicate glass (PSG) film.

Here, the cover insulating film on the fuse wiring 3
Since the etching for opening 5 is performed by oxide film type etching, the field oxide film in the part not covered with aluminum or polysilicon is etched and the surface of the silicon substrate is exposed.

[0007]

In the conventional example, an exposed portion of the silicon substrate is formed in the opening on the fuse wiring, causing a current leak between the fuse wiring and the silicon substrate.

It is an object of the present invention to prevent the silicon substrate from being exposed and prevent current leakage between the fuse wiring and the silicon substrate during etching for opening the cover insulating film on the fuse wiring.

[0009]

To solve the above problems, 1) in a method of manufacturing a semiconductor device having a redundant circuit for cutting a fuse, fuse wiring is formed on a first insulating film deposited on a semiconductor substrate. Then, a second step is performed in a region including a planned opening region of a fourth insulating film, which will be described later, formed on the fuse wiring and larger than the planned opening region.
Forming an insulating film, and then forming a third insulating film on the semiconductor substrate to cover the first and second insulating films,
A step of forming an aluminum pad thereon in a region other than the fuse wiring, a step of forming a fourth insulating film on the semiconductor substrate, covering the aluminum pad and the fuse wiring, and Opening the fourth and third insulating films on the aluminum pad and the fuse wiring,
A method of manufacturing a semiconductor device, comprising: the step of exposing the aluminum pad and the fuse wiring; or 2) the manufacturing method according to the above-mentioned 1, wherein the insulating film at the peripheral portion of the opening of the fuse wiring is surrounded by the peripheral portion. This is achieved by a semiconductor device formed to be thicker.

[0010]

In the present invention, in the same photolithography process,
When a window is opened in the cover insulating film (fourth insulating film) on the fuse wiring and the aluminum pad, the second insulating film according to the present invention is provided in an area including an opening on the fuse wiring and larger than the opening. Formed before film formation such as cover insulating film,
After that, a cover insulating film or the like is formed to thicken the insulating film on the opening on the fuse wiring, and then this is etched. By increasing the thickness of the insulating film in the opening, the thickened field insulating film (first
The silicon substrate is not exposed to prevent erosion of the insulating film).

[0011]

1 (A) and 1 (B) are structural explanatory views of the present invention.
The figure shows the structure after etching the openings. Fig. 1 (A) is a plan view and Fig. 1 (B) is a sectional view taken along the line AA.

In the figure, 1 is a silicon (Si) substrate, 2 is a first insulating film and a field insulating film, 3 is a fuse wiring and polysilicon wiring, 4 is an aluminum pad, 5 is a fourth insulating film and is a cover insulation. Membrane, 6 is the opening on the fuse wire,
7 is an opening on the aluminum pad, 8 is a second insulating film according to the present invention (which is etched to form a sidewall), and 9 leaves the second insulating film on the opening. Is an interlayer insulating film (third insulating film), a CVD SiO ₂ film, and 11 is an interlayer insulating film, PSG) film. This structure is characterized in that the insulating film on the peripheral portion of the opening on the fuse wiring is thickly formed in a frame shape.

Next, the manufacturing process will be described. Figure 2
(A)-(D) is explanatory drawing of the Example of the manufacturing process of this invention. In FIG. 2 (A), by a selective oxidation method, on a silicon substrate 1 as a field insulating film (first insulating film), to form a SiO ₂ film 2 having a thickness of 5000 Å, the thickness of 2000Å as a fuse interconnect thereon Vapor deposition (CVD) of polysilicon wiring 3
It is formed by a method and a lithography process.

Then, a CVD SiO ₂ film 8 having a thickness of 1500 to 2000 Å is grown as a _second insulating film according to the present invention on the substrate.
As shown in Fig. 2 (B), CVD is performed by a normal lithography process.
The SiO ₂ film 8 is patterned to leave a region larger than the opening on the fuse wiring.

An example of etching conditions for the CVD SiO ₂ film 8 at the time of patterning is shown below. Reactive gas: CF ₄ CHF ₃ Gas flow rate: 100 SCCM 100 SCCM Gas pressure: 0.4 Torr RF power: 800 W Here, the CVD SiO ₂ film 8 which is the second insulating film is patterned to form an opening on the fuse wiring. The reason for removing the area other than the larger area is that ion implantation for forming the source / drain of the FET formed in the removed area in a later step cannot be performed.

In FIG. 2 (C), a 1500 Å-thick CVD SiO ₂ film 10 and a 5000 Å-thick boron-containing phosphosilicate glass (BPSG) film 11 are grown as an interlayer insulation film (third insulation film) on the substrate. To do. An aluminum pad 4 having a thickness of 10000Å for bonding is formed on this.

Then, a BPSG film 5 having a thickness of 7,000 Å is formed as a cover insulating film (fourth insulating film) on the substrate by the CVD method. In FIG. 2D, an opening 6 on the fuse wiring 3 and an opening 7 on the aluminum pad 4 are formed in the cover insulating film and the interlayer insulating film by a normal lithography process.

An example of etching conditions of the insulating film for forming the opening at this time is shown below. Reaction gas: O ₂ CHF ₃ Gas flow rate: 24 SCCM 65 SCCM Gas pressure: 80 mTorr RF power: 1600 W The second insulating film according to the present invention is CVD SiO 2 on the side surface of the opening on the fuse wiring 3 after etching. ₂ Membrane 8 remains. The field insulation film 2 by the thickness of the CVD SiO ₂ film 8
Since the upper insulating film to be etched becomes thicker, the erosion of the field insulating film 2 during opening etching is reduced.

Although the polysilicon film is used for the fuse wiring in the embodiment, it is needless to say that the same effect can be obtained by using the polycide film.

[0020]

According to the present invention, the exposure of the silicon substrate can be prevented during the etching for opening the cover insulating film on the fuse wiring, and the leakage of current between the fuse wiring and the silicon substrate can be prevented. .

[Brief description of drawings]

FIG. 1 is a structural explanatory view of the present invention.

FIG. 2 is an explanatory diagram of an example of a manufacturing process of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 Silicon substrate as a semiconductor substrate 2 Thermal oxide SiO ₂ film as the first insulation film (field insulation film) 3 Polysilicon wiring as a fuse wiring 4 Aluminum pad 5 PSG film as a fourth insulation film (cover insulation film) 6 Fuse wiring Upper opening 7 Opening on aluminum pad 8 CVD SiO ₂ film by the second insulating film according to the present invention 9 Etching mask for leaving the second insulating film on the opening 10 Third insulating film (interlayer insulation) Film) CVD SiO ₂ film 11 third insulating film (interlayer insulating film) BPSG film

Claims (2)

[Claims] 1. A step of forming a fuse wiring on a first insulating film deposited on a semiconductor substrate, and a planned opening area of a fourth insulating film which will be described later and formed on the fuse wiring. And a step of forming a second insulating film in a region larger than the planned opening region, and then forming a third insulating film on the semiconductor substrate to cover the first and second insulating films and A step of forming an aluminum pad in a region other than the fuse wiring, a step of forming a fourth insulating film on the semiconductor substrate to cover the aluminum pad and the fuse wiring, and then the aluminum pad And a step of exposing the fourth and third insulating films on the fuse wiring to expose the aluminum pad and the fuse wiring. 2. A semiconductor device manufactured by the manufacturing method according to claim 1, wherein the insulating film at the peripheral portion of the opening of the fuse wiring is formed thicker than the periphery of the peripheral portion.