JP2000332116A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a fuse constituting part of a redundancy circuit. SOLUTION: The base metal BLM of a CCB bump 5 is formed on a surface protection film 10 where an inorganic insulating film 10a and a PIQ film 10b are stacked, and the fuse 8 which constitutes part of the redundancy circuit is formed only on the inorganic insulating film 10a. Further, the fuse 8 is formed of the same material with the base metal BLM, but a disconnection part 8a of the fuse 8 is formed of only one metal layer 9a of the base metal BLM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a redundant circuit.

[0002]

2. Description of the Related Art In recent years, in a semiconductor integrated circuit device,
Improvements in circuit functions and storage capacity have been promoted. However, with the improvement in circuit functions and the increase in storage capacity, it has become difficult to keep the production yield of semiconductor chips at a practical level or higher. This is because the elements and wirings become finer and the semiconductor chip becomes larger, so that the defect occurrence rate due to foreign matters and the like becomes higher.

As a technique for suppressing a decrease in the manufacturing yield of semiconductor chips due to the occurrence of the defect, there is a redundant configuration technique.

In the redundant configuration technique, a spare element that can be replaced with a defective portion is provided in a semiconductor chip in advance, and when a defect occurs, the defective chip is replaced with the spare element to rescue the semiconductor chip. It is. Switching between the defective portion and the spare element is performed by cutting a fuse constituting a part of the redundant circuit.

Several methods have been proposed for forming a fuse that constitutes a part of a redundant circuit. For example, Japanese Patent Application Laid-Open No. HEI 5-114655 discloses a method of forming a fuse from the viewpoint of easy disconnection processing. A method is disclosed in which the same material as the base metal of the solder bump is used, and the fuse is cut only by one metal layer of the base metal.

[0006]

However, the present inventor has found the following problems in the prior art.

That is, in the underfill sealing in which a resin is provided between the semiconductor chip and the substrate to reduce the stress generated in the solder bumps due to the mismatch in the coefficient of thermal expansion between the semiconductor chip and the substrate, A polyimide resin film (hereinafter, referred to as a PIQ film) is used for the surface protection film. The metal layer serving as a cut portion of the fuse is usually made of chromium (Cr). However, since this Cr is hard and brittle, a fuse made of Cr is formed on a PIQ film which is a soft heat-resistant polymer resin. Was formed, it was considered that the fuse was broken by heat treatment at a certain temperature or higher in the manufacturing process. In addition, there is a possibility of breakage due to a difference in thermal expansion coefficient in a reliability test after assembly.

An object of the present invention is to provide a technique capable of improving the reliability of a fuse forming a part of a redundant circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) the semiconductor integrated circuit device of the present invention comprises a plurality of Con
trolled collapse Bonding
A base metal for bumps (hereinafter referred to as CCB) is formed on an upper layer of a surface protective film in which an inorganic insulating film and an organic insulating film are sequentially stacked from the lower layer, and a plurality of fuses forming a part of a redundant circuit are formed on the inorganic insulating film. While being formed only on the insulating film,
The fuse is constituted by at least a part of the constituent material of the base metal for the CB bump.

(2) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device according to (1), the semiconductor chip is mounted on the package substrate via the CCB bump, and the gap between the semiconductor chip and the package substrate is under. It is sealed with a fill resin.

(3) In the semiconductor integrated circuit device of the present invention, in the semiconductor integrated circuit device of (1), the thickness of the organic insulating film is 0.5 to 10 μm.

(4) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1), wherein a protective film made of an organic insulating film is formed at least on a cut region of the fuse.

(5) A semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1), wherein the surface of the inorganic insulating film is flattened.

(6) In the semiconductor integrated circuit device of the present invention, in the semiconductor integrated circuit device of (1), an organic insulating film is provided so as to surround a plurality of fuses, and the organic insulating film is provided between adjacent fuses. A dummy pattern made of an insulating film is arranged.

(7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of patterning an inorganic insulating film on the uppermost wiring formed on the semiconductor substrate, and a step of forming an organic insulating film on the inorganic insulating film. After depositing the film, patterning the organic insulating film, removing the organic insulating film at least in a region where a fuse forming a part of the redundant circuit is formed, and removing at least a part of the base metal for the CCB bump. Simultaneously forming a pattern of a base metal for CCB bumps and a fuse constituting a part of a redundant circuit using constituent materials.

(8) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of patterning an inorganic insulating film on the uppermost wiring formed on the semiconductor substrate, and a step of forming an organic insulating film on the upper layer of the inorganic insulating film. After depositing the film, patterning the organic insulating film, removing the organic insulating film at least in a region where a fuse forming a part of the redundant circuit is formed, and removing at least a part of the base metal for the CCB bump. A step of simultaneously patterning a base metal for CCB bumps and a fuse constituting a part of a redundant circuit by using a constituent material; and a step of covering at least a cut region of the fuse with a protective film made of an organic insulating film. Things.

(9) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, an inorganic insulating film is formed in a pattern on an uppermost layer wiring formed on a semiconductor substrate, and the inorganic insulating film is opened to form a through hole. Forming a plug inside the through-hole by flattening the surface of the conductive film after depositing the conductive film on the inorganic insulating film and flattening the surface of the inorganic insulating film after forming the inorganic insulating film. And depositing an organic insulating film on the inorganic insulating film, forming a pattern of the organic insulating film, and removing the organic insulating film in a region where a fuse forming at least a part of the redundant circuit is formed. , C
A step of simultaneously forming a pattern of the base metal for the CCB bump and a fuse constituting a part of the redundant circuit using at least a part of the constituent material of the base metal for the CB bump.

According to the above-described means, in a package employing underfill sealing, a PIQ film which is a soft organic film for preventing peeling under a base metal for CCB bumps and an inorganic insulating film is formed under the PIQ film. Under the formed but hard and brittle fuse, PI
Only the inorganic insulating film is formed without forming the Q film. Thereby, stress applied to the fuse due to a difference in thermal expansion coefficient or the like in a heat treatment in a manufacturing process or a reliability test after assembly can be reduced, and breakage of the fuse can be prevented.

Further, according to the above means (4) and (8), by providing the protective film immediately above the fuse, voids immediately above the fuse due to process variations when filling the underfill resin or the like can be obtained. Generation, peeling of the underfill resin, etc. can be prevented, and corrosion of the fuse due to accumulation of moisture on the fuse can be prevented.

According to the above means (5) and (9), the surface of the inorganic insulating film under the fuse is flattened, so that the step difference under the fuse is relaxed and the fine processing of the fuse is facilitated. Etch residue of the metal layer forming the fuse can be prevented.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device having a fuse constituting a part of a redundant circuit according to an embodiment of the present invention, and FIG. And FIGS. 3 and 4 are plan views of the entire fuse.

As shown in FIG. 1, pad electrodes 3 and 4 are formed on upper and lower surfaces of a package substrate 2 constituting the package 1, respectively. The package substrate 2 is made of, for example, a ceramic material such as alumina, borosilicate glass or mullite, or a build-up wiring board. The pad electrodes 3 and 4 are electrically connected to each other by an internal wiring made of, for example, tungsten or molybdenum formed inside the package substrate 2.
The internal wiring may be a through-hole or a multilayer wiring connected by the through-hole.

Although not shown, for example, a CCB (Controlled Colla
Pse Bonding) bump or PGA (Pin Grid A)
The package 1 and the outside are connected by electrode pads 3.

Further, CCB bumps 5 are bonded to the electrode pads 4 on the upper surface of the package substrate 1. The CCB bump 5 is made of, for example, a lead (Pb) / Sn alloy containing about 1 to 10% by weight of tin (Sn) (melting point: 320 to 330 ° C.).
S) containing about 3% by weight of silver (Ag).
It is made of an n / Ag alloy (melting point: about 250 to 260 ° C.).

The space between the semiconductor chip 6 and the package substrate 2 is filled with an underfill resin 7 for mechanically reinforcing the CCB bumps 5 and improving the connection life. The underfill resin 7 is made of, for example, an epoxy resin.

The CCB bump 5 is formed on a base metal (CCB bump base metal) B formed on the main surface side of the semiconductor chip 6.
Joined to LM. That is, the semiconductor chip 6
It is mounted on the pad electrode 4 of the package substrate 2 via the CCB bump 5. BLM stands for Ball Limitin
g Metalization.

On the main surface of the semiconductor chip 6, a semiconductor integrated circuit device such as a static random access memory (SRAM) circuit or a dynamic RAM (DRAM) with logic is formed. Semiconductor integrated circuit devices are, for example, CMOS (Complementary Metal Oxide Semi)
conductor) or a CMOS semiconductor device such as Bi-CMOS (Bipolar-CMOS).

Although not shown, for example, a plurality of predetermined logic circuit blocks and a plurality of memory circuit blocks having the same word / bit configuration are arranged on the main surface of the semiconductor chip 6. A memory cell is formed. The spare memory cell is a spare memory cell that is replaced when a defective memory cell occurs. That is, a redundant circuit is formed in the semiconductor chip 6. A fuse for switching between the defective memory cell and the spare memory cell, which will be described later, is formed, for example, in the memory circuit block, and avoids peeling which is likely to occur around the semiconductor chip 6. Is formed in a region close to.

Next, the structures of the base metal BLM and the fuse 8 will be described with reference to FIG.

First, the base metal BLM is constituted by, for example, three types of metal layers 9a to 9c laminated in order from the bottom. The lowermost metal layer 9a is made of, for example, Cr or titanium (Ti), and has a thickness of, for example, 0.03 to 0.3.
It is about 2 μm. The intermediate metal layer 9b is made of, for example, nickel (Ni) or copper (Cu), and has a thickness of, for example, about 0.3 to 3 μm. Further, the uppermost metal layer 9c is made of, for example, gold (Au) and has a thickness of, for example, about 0.05 to 0.2 μm. Therefore,
The structure of the base metal BLM is Au / Ni / Cr, A
u / Cu / Cr, Au / Ni / Ti, Au / Cu / Ti
Is proposed. The intermediate metal layer 9b has a Ni—C
A u alloy or a Ni-tungsten (W) alloy can also be used.

The base metal BLM constituted by such metal layers 9 a to 9 c is electrically connected to the lead electrode 12 which is the uppermost layer wiring of the semiconductor chip 6 through the through hole 11 a formed in the surface protection film 10. Have been.

A CCB bump 5 formed by a lift-off method, a metal mask evaporation method, or the like is bonded on the base metal BLM. When mounting the semiconductor chip 6 on the package substrate 2, the base metal BLM may be connected to the CCB bump 5 bonded to the electrode pad 3 of the package substrate 2.

The surface protective film 10 is the final insulating film among the insulating films formed on the semiconductor chip 6. Base metal B
The surface protective film 10 under the LM is composed of the inorganic insulating film 1 in order from the lower layer.
0a and the PIQ film 10b are laminated. The thickness of the inorganic insulating film 10a is, for example, 0.5 to 3 μm.
The thickness of the PIQ film 10b is determined in consideration of its adhesiveness and the relief of a step, and is about 0.5 to 10 μm.

The inorganic insulating film 10a is mainly made of, for example, silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ) or a laminated film of SiO ₂ and Si ₃ N ₄ . The structure is as follows: Si ₃ N ₄
/ SOG (Spin On Glass) / SiO ₂ , Si ₃ N ₄ /
SiO ₂ , SiO ₂ / Si ₃ N ₄ , SiO ₂ / SOG /
Si ₃ N / SiO ₂ / SOG / Si ₃ N ₄ / SiO ₂ ,
SiO ₂ / Si ₃ N ₄ / SiO ₂ , SiO ₂ , SiO ₂
/ SOG / SiO ₂ etc. are proposed. The structure and film thickness are (1) flatness of the Cr fuse portion, (2) mechanical strength and moisture resistance of the insulating film, (3) cross-sectional shape of the through hole, workability, and (4) when the Cr fuse is cut. And the ease of cutting, and (5) film stress of the insulating film (wafer warpage). The PIQ film 10b is made of an inorganic insulating film 10a.
Generated by peeling of the interface between the resin and the underfill resin 7
It is provided to prevent the CB bump 5 from breaking.

The extraction electrode 12 is made of, for example, an aluminum (Al) film, an Al-Si alloy film, an Al-Si-Cu film,
W / Al / W laminated film, titanium nitride (TiN) / Al / T
It comprises an iN laminated film, a TiN / Ti / Al / Ti / TiN laminated film, a Cr / Cu / Cr laminated film, a TiN / Cu laminated film, etc., and is electrically connected to the semiconductor integrated circuit formed on the main surface of the semiconductor chip 6. It is connected. Its thickness is 0.3 ~
It is about 5 μm.

Next, the fuse 8 is connected to the above-described base metal B.
It is made of the constituent material of LM. By the way, if the cut portion 8a of the fuse 8 is formed of three types of metal layers 9a to 9c of the base metal BLM, it becomes difficult to perform a cutting process using a laser or the like. Therefore, the cut 8 of the fuse 8
a is composed of, for example, only the metal layer 9a.
That is, the cut portion 8a is constituted only of the Cr layer, for example. The advantages of using Cr as a constituent material of the fuse 8 include that it can be formed at the same time as the formation of the base metal BLM and that the corrosion resistance of Cr is superior to that of Al.

Both ends of the metal layer 9a, that is, the fuse 8
Are through holes 1 formed in the surface protective film 10.
1b, they are electrically connected to the lead electrode 12 which is the uppermost layer wiring of the semiconductor chip 6, respectively. However, non-cut portion 8b _1, 8b ₂ of the fuse 8, the metal layer 9a~9c is formed by laminating in this order from below.

Further, the surface protective film 10 under the fuse 8
Is composed only of the inorganic insulating film 10a. P
When the fuse 8 is formed on the IQ film 10b, 300 to 3
When the heat treatment at 50 ° C. is performed, the fuse 8 on the PIQ film 10b is easily broken due to a difference in thermal expansion coefficient from the PIQ film 10b, and cutting by a laser or the like becomes difficult. Therefore, the PIQ film 10b is not provided under the fuse 8.

FIG. 3 shows an example of a layout diagram of the fuse 8. A plurality of fuses 8 are arranged as needed. The cut portion 8a of each fuse 8 is thinner than other portions so as to be easily cut. Furthermore, the cutting point 8
Drawer a and under one non-cut portion 8b ₁ electrode 1
By arranging 2a, disconnection failure of fuse 8 due to a step in the base is suppressed, and lead electrode 12a
Has a function as a damage stopper to the base.

Each fuse 8 is separated by a PIQ film 10b. This increases the area occupied by the entire region where the fuses 8 are formed, but it is possible to suppress short-circuit failure between the adjacent fuses 8 due to the remaining etch of the metal layer 9a due to the step of the base.

FIG. 4 shows another example of a layout diagram of the fuse 8. A PIQ film 10b is provided so as to surround the entire region where the fuse 8 is formed. With this, PIQ
The area of the opening of the film 10b increases, and the PIQ film 10b
However, the area occupied by the fuses 8 as a whole can be relatively smaller than the fuse layout shown in FIG.

In order to prevent short-circuiting between adjacent fuses 8 due to the remaining etching of the metal layer 9a due to the step of the base, the PIQ film 10 is provided between adjacent fuses 8.
The rectangular patterns 10b ₁ may be arranged comprising b. From

Next, a process using a photosensitive PIQ, which is an example of a method of manufacturing the semiconductor integrated circuit device according to the first embodiment, will be described with reference to FIGS. Here, after a method for forming the fuse 8 is described, a method for cutting the fuse 8 will be briefly described, and further, a process until the semiconductor chip 6 is packaged will be briefly described. The steps from the step of forming the fuse 8 to the step of cutting are steps to be performed before the semiconductor chip 6 is separated from the semiconductor wafer (not shown).

First, as shown in FIG. 5, after depositing an inorganic insulating film 10a on the extraction electrode 12 made of, for example, Al, a resist film (not shown) is deposited on the inorganic insulating film 10a. This is patterned by a lithography technique to form a resist pattern. Next, using the resist pattern as a mask, the inorganic insulating film 1 is used.
After processing 0a, the resist pattern is removed to form through holes 11a and 11b.

Next, as shown in FIG.
After applying a photosensitive PIQ film 10b on the upper layer of
The Q film 10b is exposed and developed by a lithography technique, and then subjected to a curing bake at about 320 to 350 ° C. Here, the developing solution for the photosensitive PIQ film is an organic developing solution, and the Al lead electrode 12 does not corrode.
Thereby, the inorganic insulating film 10a and the PIQ film 10b
Is formed.

Next, as shown in FIG. 7, the PIQ film 10b
On the metal layers 9a to 9c by sputtering, for example.
9c is sequentially deposited from the lower layer. Next, using the resist pattern as a mask, the metal layer 9c and the metal layer 9b are sequentially processed by, for example, a wet etching method, and then the resist pattern is removed to form a pattern of the metal layers 9c and 9b. The metal layer 9c is made of Au, and the metal layer 9b is
In the case of i, the metal layers 9c and 9b are wet-etched with an iodine-based solution.

Subsequently, using the resist pattern as a mask, the metal layer 9a is processed by, for example, a dry etching method, and then the resist pattern is removed to form a metal layer 9a, thereby simultaneously forming the fuse 8 and the base metal BLM. .

In the pattern formation of the metal layers 9a, 9b and 9c, the metal layers 9b and 9c and the metal layer 9a were processed using different resist patterns.
It is also possible to form the metal layers 9a, 9b, 9c with one resist pattern by using side etching when processing b, 9c by wet etching.

As described above, the fuse 8 and the underlying metal BLM
Are formed at the same time, there is no need to manufacture a new mask for forming the fuse 8, and there is no need to add a new manufacturing process for forming the fuse 8.

Next, after a probe test is performed on each semiconductor chip on the semiconductor wafer, a laser beam (energy beam) is applied to, for example, a cut portion 8a of a predetermined fuse 8 based on the test result. Then, the fuse 8 is cut. Since the cut portion 8a of the fuse 8 is constituted by only one metal layer 9a, it is possible to cut the fuse 8 with relatively low energy.

Then, after performing the probe test again, the semiconductor chips are separated from the semiconductor wafer by means such as dicing. Then, after mounting only non-defective products among the separated semiconductor chips 6 on the package substrate 2 having the bumps provided with the CCB bumps 5, the underfill resin 7 is filled between the semiconductor chip 6 and the package substrate 2. Then, the package 1 is manufactured.

In the manufacturing process, the base metal BLM
Although the method of mounting the semiconductor chip 6 on the package substrate 2 with the bumps provided with the CCB bumps 5 by performing the probe inspection as it is has been described, the CCB bumps 5 may be bonded on the base metal BLM.

In this method, first, a solder is formed on a base metal BLM by, for example, a lift-off method or a metal mask vapor deposition.

Next, after performing a probe test on each semiconductor chip on the semiconductor wafer, a laser beam is applied to, for example, a cut portion 8a of a predetermined fuse 8 based on the result of the test, and the fuse 8 Disconnect.

Then, after performing the probe test again,
The solder is sphericalized by wet back to form the CCB bumps 5, and then the semiconductor chips are separated from the semiconductor wafer. Then, after mounting only good products of the separated semiconductor chips 6 on the package substrate 2, an underfill resin 7 is interposed between the semiconductor chip 6 and the package substrate 2.
And the package 1 is manufactured.

Next, a process using a non-photosensitive PIQ, which is another example of the method of manufacturing the semiconductor integrated circuit device according to the first embodiment, will be described with reference to FIGS.

First, as shown in FIG. 8, a first inorganic insulating film 1 is formed on an upper layer of a lead electrode 12 made of, for example, Al.
After depositing 0a _1, although not shown, it is deposited the first inorganic insulating film 10a ₁ resist film on which to form a resist pattern is patterned by a lithographic technique. Next, after a resist pattern is processed first inorganic insulating film 10a ₁ as a mask, a through hole 11a by removing the resist pattern, 11b is formed, then, first to the first layer of the inorganic insulating film 10a ₁ depositing a second inorganic insulating film 10a _2. This second inorganic insulating film 10a
Reference numeral ₂ is provided to prevent Al constituting the extraction electrode 12 from being corroded by an alkaline developer in a later step.

Next, as shown in FIG. 9, after applying the non-photosensitive PIQ film 10b to the second layer of the inorganic insulating film 10a _2, although not shown, a resist film on the PIQ film 10b Deposited and exposed by lithography technology,
By performing the developing process, the resist film is patterned to form a resist pattern, and at the same time, the PIQ film 10b is processed with an alkali developing solution used in the developing process. Then, for example, a dry etching method, the second processing the inorganic insulating film 10a _2, then after removing the resist pattern is subjected to curing bake of about 320-350 ° C..

Thereafter, the same manufacturing method as that using the photosensitive PIQ is used, as shown in FIG.
The fuse 8 and the underlying metal BLM are simultaneously formed on the Q film 10b.

Further, after performing a probe test on each semiconductor chip on the semiconductor wafer, a laser beam is applied to a cut portion 8a of a predetermined fuse 8 based on the result of the test, for example. Disconnect.

Thereafter, a probe test is performed again to separate the semiconductor chips from the semiconductor wafer. Then, after mounting only non-defective products among the separated semiconductor chips 6 on the package substrate 2 having the bumps provided with the CCB bumps 5, the underfill resin 7 is filled between the semiconductor chip 6 and the package substrate 2. Then, the package 1 is manufactured.

As described above, according to the first embodiment, in the package 1 employing the underfill sealing, the C
Under the base electrode BLM on which the CB bump 5 is formed, a PIQ film 1 which is a soft organic film for preventing peeling is provided.
Although 0b is formed, the PIQ film 10b is not formed under the fuse 8 having a hard and brittle property, and only the inorganic insulating film 10a is formed. Thereby, stress applied to the fuse 8 due to a difference in thermal expansion coefficient in a heat treatment in a manufacturing process or a reliability test after assembly can be reduced, and breakage of the fuse 8 can be prevented.

(Embodiment 2) FIG. 11 is a sectional view showing a main part of a base metal BLM and a fuse 8 according to another embodiment of the present invention.

As shown in FIG. 11, the fuse 8 is covered and protected by the fuse protection film 13. The fuse protection film 13 is made of, for example, a PIQ film,
Except for the upper surface of the LM, it is deposited on almost the entire main surface of the semiconductor chip 6. The thickness of the fuse protection film 13 is set, for example, in a range of about 0.05 to 0.5 μm.

Next, an example of a method of forming the base metal BLM and the fuse 8 according to the second embodiment will be described.

First, in the same manner as in the first embodiment,
As shown in FIG. 7 or FIG. 10, the surface protection film 1 composed of the inorganic insulating film 10a and the PIQ film 10b is formed on the lead electrode 12 which is the uppermost layer wiring of the semiconductor chip 6.
After patterning 0, a base metal BLM and a fuse 8 are formed.

Next, solder is formed on the underlying metal BLM by, for example, a lift-off method or metal mask evaporation.

Next, after performing a probe test on each semiconductor chip on the semiconductor wafer, based on the result of the test, for example, a laser beam is irradiated to a cut portion 8a of a predetermined fuse 8, and the fuse 8 Disconnect.

Thereafter, the probe inspection is performed again, and the solder is made spherical by wet back to form the CCB bump 5. Next, a photosensitive PI is coated on the entire surface of the semiconductor wafer.
After applying the Q film, the PIQ film is exposed and developed by a lithography technique to obtain a PI around the CCB bump.
The Q protection film 13 is formed by opening the Q film and then performing baking at about 320 to 350 ° C. Note that the fuse protection film 13 may be patterned only on the fuse 8.

Next, the semiconductor chips are separated from the semiconductor wafer. Then, after mounting only good products among the separated semiconductor chips 6 on the package substrate 2, the underfill resin 7 is filled between the semiconductor chip 6 and the package substrate 2 to manufacture the package 1.

In the above-described manufacturing process, the pattern formation of the fuse protection film 13 is performed after the CCB bump 5 is formed on the base metal BLM, but may be performed before the CCB bump 5 is formed. Thus, the step of connecting to the package substrate 2 provided with the CCB bumps and the curing and baking step can be performed in the same step. According to these methods, it is possible to find out a defect in the resin immediately above the fuse 8 by a chip inspection after dicing.

As described above, according to the second embodiment, by providing the fuse protection film 13, generation of voids immediately above the fuse due to process variation or the like when filling the underfill resin 7, or underflow of the underfill resin 7. Separation of the fill resin 7 can be prevented, and corrosion of the fuse 8 due to accumulation of moisture on the fuse 8 can be prevented.

(Embodiment 3) FIG. 12 is a sectional view showing a main part of a base metal BLM and a fuse 8 according to another embodiment of the present invention.

As shown in FIG. 12, in order to ease the step of the base and facilitate the fine processing of the fuse 8, the fuse 8
The surface of the inorganic insulating film 10a constituting the lower surface protective film 10 is flattened.

Next, an example of a method of forming the base metal BLM and the fuse 8 according to the fourth embodiment will be described.

First, the inorganic insulating film 10 is formed on the extraction electrode 12 formed of, for example, a TiN / Al / TiN laminated film.
After depositing the inorganic insulating film 10a,
A resist film is deposited on a, and is patterned by lithography to form a resist pattern.
Next, using the resist pattern as a mask, the inorganic insulating film 10
After processing a, the resist pattern is removed to form through holes 11a and 11b. Next, the surface of the inorganic insulating film 10a is planarized by, for example, a chemical mechanical polishing (Chemical Vapor Deposition; CMP) method.

Next, a metal film is formed on the inorganic insulating film 10a.
For example, after depositing W, the surface of the metal film is flattened by the CMP method, so that the metal film is
The plug 14 is buried in the inside of 11b.

Next, in the same manner as in the first embodiment,
After patterning the surface protection film 10 composed of the inorganic insulating film 10a and the PIQ film 10b, the base metal BLM and the fuse 8 are formed.

Next, after performing a probe test on each semiconductor chip on the semiconductor wafer, based on the result of the test, a laser beam is applied to, for example, a cut portion 8a of a predetermined fuse 8, and the 8 is cut.

Thereafter, a probe test is performed again, and a face mark is attached to a semiconductor chip that has not passed the test, and then the semiconductor chip is separated from the semiconductor wafer. Then, only the non-defective semiconductor chips 6 among the separated semiconductor chips 6 are
After mounting on the package substrate 2 with the bumps 5 provided with the B bumps 5, an underfill resin 7 is filled between the semiconductor chip 6 and the package substrate 2 to manufacture the package 1.

As described above, according to the third embodiment, the inorganic insulating film 10 constituting the surface protection film 10 under the fuse 8
By flattening the surface of b, the step difference in the base of the fuse 8 is alleviated to facilitate the fine processing of the fuse 8, and the metal layer 9a constituting the fuse 8 can be prevented from being left unetched.

(Embodiment 4) FIG. 13 is a sectional view showing a main part of a base metal BLM and a fuse 8 according to another embodiment of the present invention.

The fuse 8 has the same structure as the fuse 8 shown in FIG. 2 of the first embodiment, and the surface protection film 10 under the fuse 8 is constituted only by the inorganic insulating film 10a. I have. Further, as shown in FIG.
The surface protection film 10 under the base metal BLM is also an inorganic insulating film 10a.
It consists only of.

As described above, according to the third embodiment, the PIQ film 10b or the through holes 11a, 11b is not provided under the base metal BLM.
Etc. can be given a margin in processing accuracy, and processing in the manufacturing process can be facilitated.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

[0089]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, in a semiconductor chip mounted via a CCB bump on a package adopting underfill sealing, breakage and corrosion of a fuse constituting a part of a redundant circuit formed on the semiconductor chip are performed. Can be prevented, and furthermore, the remaining etching of the metal layer constituting the fuse can be prevented, so that the reliability of the fuse can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device having a fuse forming a part of a redundant circuit according to an embodiment of the present invention;

FIG. 2 is a sectional view of a main part of a fuse constituting a part of a redundant circuit of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is an example of a plan view of a main part of a fuse constituting a part of a redundant circuit of a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 4 is another example of a plan view of a main part of a fuse constituting a part of a redundant circuit of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 5 is an explanatory diagram of an example of a method of manufacturing a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 6 is an explanatory diagram illustrating an example of a method of manufacturing a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 7 is an explanatory diagram illustrating an example of a method of manufacturing a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 8 is an explanatory diagram of another example of a method of manufacturing a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 9 is an explanatory diagram of another example of a method of manufacturing a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 10 is an explanatory diagram of another example of a method of manufacturing a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 11 is a sectional view of a main part of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 12 is a sectional view of a main part of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 13 is a sectional view of a main part of a fuse constituting a part of a redundant circuit of a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Package 2 Package board 3 Pad electrode 4 Pad electrode 5 CCB bump 6 Semiconductor chip 7 Underfill resin 8 Fuse 8a Cut part 8b ₁ Non-cut part 8b ₂ Non-cut part 9a Metal layer 9b Metal layer 9c Metal layer 10 Surface protective film 10a Inorganic insulating film 10a ₁ First inorganic insulating film 10a ₂ Second inorganic insulating film 10b PIQ film 10b ₁ Rectangular pattern 11a Through hole 11b Through hole 12 Leader electrode 12a Leader electrode 13 Fuse protective film 14 Plug BLM Base metal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Kikuchi 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Eiko Ando 6--16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Ikuo Yoshida 6-chome, Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center F-term (reference) 5F064 BB13 BB14 BB40 CC12 CC16 DD42 DD48 EE32 EE33 EE34 FF02 FF27 FF32 FF33 FF42 FF60 GG10

Claims (10)

[Claims] A plurality of electrode conductor patterns formed on a semiconductor chip are formed on an upper layer of a surface protection film in which an inorganic insulating film and an organic insulating film are sequentially stacked from a lower layer, and the plurality of electrode conductor patterns form a part of a redundant circuit. Wherein the fuse is formed only on the inorganic insulating film, and the fuse is formed of at least a part of the material of the electrode conductor pattern. 2. The semiconductor integrated circuit device according to claim 1, wherein said electrode conductor pattern is a base metal for CCB bumps. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor chip is mounted on a package substrate via CCB bumps, and a gap between the semiconductor chip and the package substrate is sealed with an underfill resin. And a semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein said organic insulating film has a thickness of 0.5 to 10 μm. 5. The semiconductor integrated circuit device according to claim 1, wherein a protective film made of an organic insulating film is formed at least on a cut region of said fuse. 6. The semiconductor integrated circuit device according to claim 1, wherein a surface of said inorganic insulating film is flattened. 7. The semiconductor integrated circuit device according to claim 1, wherein said organic insulating film surrounds a plurality of said fuses, and a dummy pattern made of said organic insulating film is arranged between adjacent ones of said fuses. A semiconductor integrated circuit device characterized in that: 8. A process of patterning an inorganic insulating film on an uppermost layer wiring formed on a semiconductor substrate, and
(b) After depositing an organic insulating film on the inorganic insulating film,
Patterning the organic insulating film, removing the organic insulating film in a region where a fuse forming at least a part of a redundant circuit is formed, and (c) removing at least a part of the constituent material of the electrode conductor pattern. Forming a pattern of the electrode conductor pattern and a fuse constituting a part of the redundant circuit at the same time by using the method. 9. (a) a step of patterning an inorganic insulating film on the uppermost wiring formed on the semiconductor substrate;
(b) After depositing an organic insulating film on the inorganic insulating film,
Patterning the organic insulating film, removing the organic insulating film in a region where a fuse forming at least a part of a redundant circuit is formed, and (c) removing at least a part of the constituent material of the electrode conductor pattern. A step of simultaneously patterning the electrode conductor pattern and a fuse constituting a part of the redundant circuit, and (d) a step of covering at least a cut region of the fuse with a protective film made of an organic insulating film. A method for manufacturing a semiconductor integrated circuit device, comprising: 10. An inorganic insulating film is formed in a pattern on an uppermost layer wiring formed on a semiconductor substrate, a through hole is formed by opening the inorganic insulating film, and then the inorganic insulating film is formed. (B) depositing a conductive film on the inorganic insulating film and then flattening the surface of the conductive film to form a plug inside the through hole (C) depositing an organic insulating film on top of the inorganic insulating film, patterning the organic insulating film, and forming the organic insulating film in a region where a fuse forming at least a part of a redundant circuit is formed. And (d) using at least a part of the constituent material of the electrode conductor pattern, simultaneously forming a pattern of the electrode conductor pattern and a fuse constituting a part of the redundant circuit. Semiconductor integrated circuit characterized by Manufacturing method of the device.