JP2004134640A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the truncation precision of a fuse by improving the recognizing precision of a registration mark (target). <P>SOLUTION: Third layer wiring M3 composed of a TiN film M3a, an Al alloy film M3b and a TiN film M3c is formed on the upper part of a semiconductor substrate 1 wherein the fuse F is formed. A passivation film 41 and a polyimide resin film 43 are formed on the upper part of the third layer wiring, and a seed layer 45 is formed. A Cu film 49a and an Ni film 49b are formed by a plating method, the seed layer 45 which became unnecessary is etched, and re-wiring 49 and the target T are formed. The Ni film 49b exposed from a second pad PAD 2 is subjected to pretreatment like alkaline cleaning, and an Au film 53 is formed. The position of the target T is recognized by laser light RB, the position of the fuse F is determined from the position of the target T, and the fuse F is cut. As a result, the erosion of the target T caused by an etchant and a pretreatment solution can be prevented. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to an alignment mark used for cutting a fuse.
[0002]
[Prior art]
A CSP (chip) is a package that can realize a smaller and thinner package than wire bonding (wire bonding) that electrically connects a bonding pad portion on the surface of an IC (Integrated Circuit) chip to an external terminal of the package with a gold wire or the like. There has been proposed a mounting mode in which a projection (bump) electrode formed on a pad portion is used for connection with an external terminal, such as a size package.
[0003]
This CSP is a general term for packages having a size equal to or slightly larger than the size of a semiconductor chip. 1) It is easy to increase the number of pins. 2) The space between bump electrodes can be increased, and the diameter of the bump electrodes can be increased. For reasons such as possible, there is a type in which bump electrodes are arranged in an area on the surface of a chip (a so-called area array structure).
[0004]
In order to manufacture an IC having this area array structure, for example, wiring for connecting a pad portion arranged along a peripheral portion of a chip and a bump electrode arranged in an area on the entire surface of the chip, that is, so-called rewiring is required. Become.
[0005]
[Problems to be solved by the invention]
On the other hand, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a non-volatile memory (EEPROM: Electrically Erasable Programmable Read Only Memory in an electrically programmable eraseable memory, an electrically writable and erasable memory, and the like) are produced. The production yield is improved by providing a redundant function for relieving the problem.
[0006]
This is because a memory cell column and a memory cell row for redundancy repair are prepared in advance in the semiconductor integrated circuit device, and when a defective memory cell column occurs in the memory array, an address signal entering the defective memory cell is provided. Is input to a memory cell column (row) for redundancy repair so that a desired memory operation is performed.
[0007]
Switching between the defective memory cell and the redundancy repair memory cell is performed by cutting a fuse connected to the address switching circuit. For cutting the fuse, a laser fusing method or the like is employed.
[0008]
The present inventors are engaged in research and development of a semiconductor integrated circuit device (semiconductor device). When a fuse of a semiconductor integrated circuit device is cut by a laser, the position of the fuse is determined with high accuracy by using Al (aluminum). ) Is used to form a target (alignment mark).
[0009]
That is, after recognizing the position of the target, the position of the fuse is recognized again from the relationship between the target and the position of the fuse, and the fuse is cut.
[0010]
In particular, with the miniaturization of elements, fuses are formed with a fine pitch, for example, with a width of about 1 μm and an interval of about 5 μm with a short pitch. In such a case, in order to cut a desired fuse accurately and to cut the fuse so as not to affect an adjacent fuse, the positioning accuracy of the target is important.
[0011]
However, when the present inventors attempted to cut a fuse in a semiconductor integrated circuit device using the above-described rewiring, target recognition failure occurred.
[0012]
Further, the present inventors have investigated the cause, and as a result, it has been found that the cause of the recognition failure is corrosion (erosion) of the target.
[0013]
That is, as will be described in detail later, in the apparatus using the rewiring, a process of forming the rewiring and a process of forming the bump electrode exist after the pattern of the target Al is formed.
[0014]
For example, when the rewiring is formed by the electrolytic plating method, an etching process of the seed layer is performed, and when a solder bump is used as a bump electrode, an Au (gold) film is formed as a base film. As a pre-treatment for forming a gold film, cleaning using an acid or alkali-based liquid is performed.
[0015]
At the time of such a treatment, the surface of the target was corroded by the etching solution or the cleaning solution, resulting in recognition failure.
[0016]
SUMMARY OF THE INVENTION An object of the present invention is to improve the recognition accuracy of an alignment mark and improve the cutting accuracy of a fuse.
[0017]
Another object of the present invention is to improve the yield of semiconductor integrated circuit devices and to improve the characteristics thereof.
[0018]
The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0019]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0020]
(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; and (b) forming a first conductive film in the chip region. Forming a two-conductive film; (c) forming a first insulating film on the second conductive film; and (d) removing the first insulating film on the second conductive film. (E) forming a third conductive film extending from the first pad region to the second pad region on the second conductive film. Forming a fourth conductive film in the same layer as the third conductive film on the scribe region; and (f) forming a second insulating film on the third conductive film and the fourth conductive film. And (g) a second insulating film on the second pad region of the third conductive film. Removing, those having the steps of cutting the (h) wherein (g) after the step, the first conductive film based on the position of the fourth conductive film.
[0021]
The first conductive film is, for example, a fuse, and performs a redundancy repair of, for example, a memory cell by cutting the fuse in the step (h). The second conductive film is, for example, a film having an Al film. The first insulating film is an inorganic film, and is a film that attenuates the reflected light intensity of the second conductive film. The third and fourth conductive films are, for example, films having a Cu film. The second insulating film is, for example, a polyimide resin film.
[0022]
(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; and (b) forming a first conductive film in the chip region. Forming a second conductive film on the scribe region, forming a third conductive film in the same layer as the second conductive film; and (c) forming the second and third conductive films. Forming a first insulating film on the film, and (d) exposing at least a part of the third conductive film by removing the first insulating film on the second and third conductive films. Exposing a first pad region of the second conductive film; (e) forming a second insulating film on the second and third conductive films; and (f) forming the second conductive film. Removing the second insulating film on the conductive film to expose the first pad region. (G) leaving the second insulating film so as to cover the exposed region of the third conductive film; and (g) removing the second pad from the first pad region on the second conductive film. Forming a fourth conductive film extending to the region, and (h) after the step (g), confirming the position of the exposed region of the third conductive film via the second insulating film. Cutting the first conductive film on the basis of the position.
[0023]
The first conductive film is, for example, a fuse, and performs a redundancy repair of, for example, a memory cell by cutting the fuse in the step (h). The second and third conductive films are, for example, films having an Al film. The first insulating film is an inorganic film, and is a film that attenuates reflected light intensity of the second and third conductive films. The fourth conductive film is, for example, a film having a Cu film. The second insulating film is, for example, a polyimide resin film.
[0024]
(3) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; and (b) forming a first conductive film in the chip region. Forming a first wiring having a two-conductive film and a third conductive film thereon, and forming a pattern having the second conductive film and a third conductive film thereabove in the scribe region; (C) forming a first insulating film on the first wiring and the pattern; and (d) removing the first insulating film on the first wiring and the pattern to form the first wiring. Exposing a first pad region of the third conductive film to constitute, and exposing at least a part of the third conductive film to constitute the pattern; and (e) a first pad on the first wiring Extends from area to second pad area Forming a second wiring that is one having the steps of cutting the first conductive film on the basis of the position of the (f) after step (e), the exposed region of said pattern.
[0025]
The first conductive film is, for example, a fuse, and performs a redundancy repair of, for example, a memory cell by cutting the fuse in the step (f). The first wiring and the pattern include, for example, a second conductive film containing Al as a main component, and a third conductive film made of a TiN film on the second conductive film. The first insulating film is an inorganic film, and is a film that attenuates reflected light intensity of the second and third conductive films. The second wiring is, for example, a wiring having a Cu film.
[0026]
(4) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region; and (b) the chip region and a scribe line. Forming a groove in the region, (c) forming a second conductive film in the groove, (d) forming a first insulating film on the second conductive film, e) exposing the first pad region on the second conductive film by removing the first insulating film on the second conductive film in the chip region; and (f) exposing the second conductive film. Forming a third conductive film extending from the first pad region to the second pad region on the film; and (g) forming the third conductive film in the scribe region after the step (f). The position is confirmed through the first insulating film, and the second position is determined based on the position. And cutting the conductive film, and has a.
[0027]
The first conductive film is, for example, a fuse, and performs a redundancy repair of, for example, a memory cell by cutting the fuse in the step (g). The second conductive film is, for example, a film containing Cu as a main component. The first insulating film is an inorganic film, and transmits light reflected by the second conductive film. The third conductive film is, for example, a film having a Cu film.
[0028]
(5) A semiconductor integrated circuit device according to the present invention includes: (a) a first conductive film formed in a chip region of a semiconductor substrate; (b) a second conductive film formed in the chip region; A) a first insulating film formed on the second conductive film and exposing a first pad region of the second conductive film; and (d) a first insulating film from the first pad region on the second conductive film. A third conductive film extending to the two pad regions, (e) a fourth conductive film formed on the outer peripheral portion of the chip region and having the same configuration as the third conductive film, and (f) And a bump electrode formed on the second pad region of the third conductive film.
[0029]
The first conductive film is, for example, a fuse. The fuse is cut to perform, for example, redundancy repair of a memory cell. The second conductive film is, for example, a film having an Al film. The first insulating film is an inorganic film, and is a film that attenuates the reflected light intensity of the second conductive film. The third and fourth conductive films are, for example, films having a Cu film. The outer peripheral portion of the chip region refers to, for example, a scribe region remaining on the outer peripheral portion of the chip region when a wafer-like substrate is cut along a scribe line. The bump electrode is made of, for example, solder.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0031]
(Embodiment 1)
FIG. 1 is a plan view showing a semiconductor wafer W (semiconductor substrate 1) on which the semiconductor integrated circuit device of the present embodiment is formed.
[0032]
As illustrated, the semiconductor wafer W has a plurality of substantially rectangular chip areas CA, and the plurality of chip areas CA are partitioned by the scribe areas SA. A target T, which will be described in detail later, is formed on the scribe area.
[0033]
Next, a semiconductor integrated circuit device according to an embodiment of the present invention will be described according to a method for manufacturing the same.
[0034]
First, a semiconductor element is formed on the semiconductor substrate 1. The semiconductor element has various structures, and a detailed description thereof is omitted here. For example, FIG. 2 shows an example of a structure of a DRAM memory cell.
[0035]
As shown in FIG. 2, an element isolation 3 and a p-type well 5 in which an insulating film such as a silicon oxide film is embedded are formed in a semiconductor substrate 1. MISFET Qt is formed.
[0036]
The information transfer MISFET Qt has a gate electrode G formed on the semiconductor substrate 1 with a gate insulating film 7 interposed therebetween, and the source and drain regions 9 and 11 formed in the semiconductor substrate 1 on both sides of the gate electrode G. Have. The gate electrode G is formed of a laminated film of a polycrystalline silicon film 13a, a WN (tungsten nitride) film 13b, and a W (tungsten) film 13c, and a silicon nitride film 15 is formed thereon. A silicon nitride film 17 is formed on the side wall of the gate electrode G and the like. Plugs P1b and P1a are formed on the source and drain regions 9 and 11, and a plug P2a is formed on the plug P1a. A bit line BL is formed. An information storage capacitor C is formed on the plug P1b via the plug P2b. The information storage capacitive element C includes, for example, an upper electrode 21 made of a TiN (titanium nitride) film, a capacitive insulating film 23 made of a tantalum oxide film, and a lower electrode 25 made of a polycrystalline silicon film.
[0037]
Here, 27a to 27e are interlayer insulating films made of, for example, a silicon oxide film or the like.
[0038]
In addition to such a memory element, various elements such as a MISFET (Metal Insulator Semiconductor Effect Transistor) constituting a peripheral circuit are formed in the chip area CA described with reference to FIG.
[0039]
FIG. 3 is an enlarged view near the chip area CA in FIG. As shown in the figure, there are a plurality of memory areas MA in a chip area CA, and a redundant memory area RA at an end of this area. In addition, a portion between the memory regions MA is a peripheral circuit region PA in which MISFETs and the like constituting the peripheral circuit are formed.
[0040]
For example, a fuse area FA is arranged in the peripheral circuit area PA. For example, a plurality of linear conductive patterns (for example, about 1 μm in width) are formed at a narrow pitch (about 5 μm).
[0041]
By appropriately cutting the fuse, for example, an address signal which enters a defective memory cell is input to a memory cell column for redundancy repair to perform redundancy repair.
[0042]
This fuse can be formed of the same film as the conductive film forming the memory cell and the wiring.
[0043]
For example, the fuse F shown in FIG. 4 can be formed of the same film as the gate electrode G configuring the DRAM memory cell shown in FIG. Note that, in FIG. 4, descriptions of memory cells, other semiconductor elements, plugs for connecting these to wiring, and the like are omitted (the same applies to the following drawings). 4 to 13 are a cross-sectional view of a main part of the substrate in the chip area CA and the scribe area SA, and a partial enlarged view or a plan view of the main part.
[0044]
As shown in FIG. 4, on the fuse F, for example, a silicon oxide film 31 is formed as an insulating film, and further, a first layer wiring M1 is formed thereon. The first layer wiring M1 and the fuse F are connected via a plug P1. As described above, when the fuse F is formed of the same film as the gate electrode G forming the memory cell, the silicon oxide film 31 corresponds to, for example, the silicon oxide films 27a and 27b in FIG. Further, the first layer wiring M1 corresponds to, for example, the bit line BL in FIG.
[0045]
For example, a silicon oxide film 32 is formed as an insulating film on the first layer wiring M1, and a second layer wiring M2 is formed thereon. The second layer wiring M2 and the first layer wiring M1 are connected via a plug P2. For example, the silicon oxide film 32 corresponds to the silicon oxide films 27c to 27e in FIG.
[0046]
On the second layer wiring M2, for example, a silicon oxide film 33 is formed as an insulating film, and a plug P3 is formed in the silicon oxide film 33. The plug P3 serves as a connection portion between the second layer wiring M2 and a third layer wiring M3 described later.
[0047]
Next, as shown in FIG. 5, for example, a TiN film M3a, an Al (aluminum) alloy film M3b, and a TiN film M3c are sequentially deposited on the silicon oxide film 33 and the plug P3, and are patterned into a desired shape. The layer wiring M3 is formed.
[0048]
Next, a silicon oxide film (lower layer) such as a TEOS film and a silicon nitride film (upper layer) are sequentially deposited as a protective film on the third layer wiring M3 and the like by, for example, a CVD (Chemical Vapor Deposition) method. A passivation film 41 is formed. Note that the passivation film 41 may be configured as a single layer.
[0049]
Next, the passivation film 41 on the third-layer wiring M3 is removed by dry etching to expose the first pad portion PAD1.
[0050]
During the dry etching of the passivation film 41, the TiN film M3c of the first pad portion PAD1 is removed.
[0051]
At this time, the insulating film (31 to 33, etc.) on the fuse F may be removed. This is because the insulating film on the fuse F is made thinner so that the fuse F can be easily cut by a laser.
[0052]
Next, a photosensitive polyimide resin film 43 is spin-coated on the passivation film 41 and subjected to heat treatment (pre-bake). Next, the polyimide resin film is exposed and developed to expose the first pad portion PAD1 and the groove 42, and to expose the scribe area SA. Next, heat treatment (post bake) at about 350 ° C. is performed to cure (cure) the polyimide resin film.
[0053]
Next, as shown in FIG. 6, a seed layer (feeding layer) 45 is formed on the polyimide resin film 43 including on the first pad portion PAD1. The seed layer 45 is formed of, for example, a laminated film of a Cr (chromium) film and a Cu (copper) film. The seed layer 45 may be composed of, for example, a laminated film of a TiN film and a Cu film.
[0054]
Next, a resist film R having a long groove 47 extending from an upper portion of the first pad portion PAD1 to a region for forming a second pad portion PAD2 described later is formed on the seed layer 45 by using a photolithography technique.
[0055]
Here, an approximately L-shaped groove 47t having a width of about 10 μm for forming the target T is also formed on the scribe area SA (see FIG. 13).
[0056]
Next, a Cu film 49a is formed inside the grooves 47 and 47t by electrolytic plating. In order to form the Cu film 49a, the substrate 1 is immersed in a plating solution for Cu to fix the seed layer 45 to the minus (−) electrode, and the seed layer 45 at the bottom of the grooves 47 and 47t not covered with the resist film R is formed. A Cu film 49a is deposited on the surface of the layer 45.
[0057]
Thereafter, a Ni (nickel) film 49b is formed on the Cu film 49a inside the grooves 47 and 47t by an electrolytic plating method. In order to form the Ni film 49b, the substrate 1 is immersed in a plating solution for Ni, the seed layer 45 is fixed to a minus (-) electrode, and the Cu at the bottom of the grooves 47 and 47t not covered with the resist film R is formed. A Ni film 49b is deposited on the surface of the film 49a.
[0058]
Thereafter, as shown in FIG. 7, after removing the resist film R, the unnecessary seed layer 45 is removed by wet etching using the Cu film 49a and the Ni film 49b as a mask. As an etching solution for the Cu film, for example, sulfuric acid and hydrogen peroxide is used, and as an etching solution for the Cr film, for example, a mixed solution of potassium permanganate and sodium metasilicate is used.
[0059]
As a result, a redistribution wiring 49 including the Cu film 49a, the Ni film 49b and the seed layer 45 and the target T are formed. FIG. 12 is a partially enlarged view of the target T portion in FIG. FIG. 13 is a plan view of a main part of the target T portion. Instead of the Cu film 49a and the Ni film 49b, a Cr film, a laminated film of a Cu film and a Cr film may be formed by, for example, a sputtering method.
[0060]
In this rewiring, for example, since it is difficult to form a bump electrode on the first pad portion PAD1 which is densely formed around the chip region CA or in the center, the bump electrode is formed over the entire surface of the chip region CA. When the first pad portion PAD1 is arranged at a wider interval than the first pad portion PAD1, it serves to connect the first pad portion PAD1 to a bump electrode (a second pad portion PAD2 described later). In addition, the rewiring can be said to be a wiring for relocating the first pad portion PAD1 having a smaller space to the second pad portion PAD2 having a larger space. Alternatively, it can be said that the wiring is for changing the interval between the pad portions.
[0061]
The seed layer 45 below the redistribution wiring 49 has a role of improving the adhesive strength between the Cu film 49a and the polyimide resin film 43 therebelow, and a role of preventing Cu from diffusing into the polyimide resin film 43. Fulfill.
[0062]
The reason why the Ni film 49b is stacked on the Cu film 49a is to prevent the formation of an undesired product due to the contact between the later-described solder bump electrode 55 and the Cu film 49a. Also, the Ni film has good adhesiveness to a polyimide resin film to be formed thereafter. In addition, other than Ni, Cr, Ti, TiN, Ta (tantalum), TaN (tantalum nitride), WN (tungsten nitride), or the like may be used.
[0063]
Next, as shown in FIG. 8, a polyimide resin film 51 having an opening in the second pad portion PAD2, the groove 42, and the scribe area SA on the rewiring 49 is formed. The polyimide resin film 51 can be formed in the same manner as the polyimide resin film 43. That is, a photosensitive polyimide resin film is spin-coated and heat-treated. Next, after exposing and developing the polyimide resin film to open the second pad portion PAD2 and the scribe area SA, a heat treatment (post bake) at about 350 ° C. is performed to cure (cur) the polyimide resin film.
[0064]
Next, an Au film 53 is formed by an electroless plating method on the Ni film 49b exposed at the opening (second pad portion PAD2) of the polyimide resin film 51. First, an ashing (ashing) process is performed. A treatment such as alkali degreasing treatment and acid washing is performed.
[0065]
That is, since an organic contaminant layer such as an oxide film or a polyimide resin residue is formed on the Ni film 49b of the second pad portion PAD2, first, the organic contaminant layer is formed by ashing using oxygen. Remove.
[0066]
Next, alkali degreasing and acid cleaning are performed to remove the oxide film and activate the surface of the Ni film 49b. For the alkali degreasing treatment, for example, a sodium metasilicate solution is used. The acid cleaning is performed using hydrochloric acid (HCl).
[0067]
Next, an Au film 53 is deposited on the Ni film 49b exposed from the second pad portion PAD2 by an electroless plating method. As the Au plating solution, for example, a gold sodium sulfite-based plating solution is used. This plating method utilizes the difference in the ionization tendency of Ni and Au to form an Au film 53 by substituting them, and is called a displacement plating method among electroless plating methods. At this time, the Au film 53 is also formed on the target T.
[0068]
The reason why the Au film 53 is formed on the Ni film 49b of the second pad portion PAD2 is to improve the wettability of the solder bump electrode 55 formed on the second pad portion PAD2. The “wetability” refers to, for example, the degree of familiarity between the alloy solder and the Au film when the alloy solder of Sn (tin) and Pb (lead) is mounted on the second pad portion PAD2. Note that a barrier metal film may be formed between the Au film, such as using a laminated film of a Ni film and an Au film or a laminated film of a NiCu (nickel copper) film and an Au film instead of the Au film 53.
[0069]
Next, for example, a probe needle is brought into contact with the Au film 53 on the second pad portion PAD2 to perform a test (P test) to determine whether the memory cell electrically connected to the second pad portion PAD2 is good or bad. I do. From this determination result, a memory cell to be repaired is determined, and a fuse F to be cut is specified. The P test may be performed using the first pad portion PAD1.
[0070]
Next, the semiconductor wafer W is set on the laser rescue machine, and the target T is irradiated with the laser beam RB to recognize the position of the target T as shown in FIG. 9, and then the position of the fuse F is determined from the position of the target T. I do.
[0071]
For example, in order to recognize the position of the target T, as shown in FIG. 13, the laser is scanned in the X and Y directions, and the change in the reflection intensity of the laser is measured. The intersection (coordinate) of the center line of the region where the reflection intensity in the X direction and the Y direction exceeds the threshold is the reference point RP. The recognition of the target T is performed twice for each chip area CA. Note that it may be performed twice for each shot. A shot refers to one transfer area when transferring each pattern constituting a semiconductor element.
[0072]
Next, the position (coordinates) of the fuse F determined to be cut by the P inspection is irradiated with laser light to cut the fuse F (FIG. 9).
[0073]
Thereafter, as shown in FIG. 10, a bump electrode 55 made of an alloy solder of Sn (tin) and Pb (lead) is formed on the Au film 53. The bump electrode 55 is formed by, for example, a printing method or a ball transfer method. Although FIG. 10 shows the Au film 53 for easy understanding, the Au film 53 is absorbed in the solder after the solder is mounted.
[0074]
Thereafter, the semiconductor wafer W is diced along the scribe area SA to divide it into a plurality of chips (CA). Next, for example, after the individual chips (CA) are face-down bonded onto the mounting substrate 60 and the bump electrodes 55 are heated and reflowed, the underfill resin 62 is filled in the gap between the chip (CA) and the mounting substrate 60. Completes the CSP (FIG. 11).
[0075]
As described above, according to the present embodiment, since the target T is formed of the same layer as the rewiring 49, for example, corrosion of the target by the etchant for the seed layer 45 or the pretreatment liquid at the time of forming the Au film 53 is prevented. Thus, the position of the target T can be accurately recognized.
[0076]
Therefore, the fuse can be cut accurately. As a result, the product yield is improved by the redundancy relief of the memory cells. Further, erroneous cutting of the fuse can be prevented, and the product yield can be improved. Further, the influence on the adjacent fuse can be reduced, and the product performance can be improved.
[0077]
For example, as shown in FIG. 14, when the target T is formed of the same layer as the third-layer wiring M3, the Al alloy film M3b (the target T and the third-layer wiring M3) is interposed via an inorganic film such as the passivation film 41. Laser reflected light cannot be confirmed. That is, such an inorganic film can be said to be a film that attenuates the reflected light intensity of the Al alloy film M3b. Therefore, it is necessary to remove the passivation film 41 above the target T and form the opening OA. Further, similarly to the first pad portion PAD1, when the TiN film M3c exposed from the opening OA is removed and the Al alloy film M3b is exposed, the Al alloy film M3b is formed by the steps shown in FIGS. Is exposed to the etching solution at the time of removing the seed layer 45, and the Al alloy film M3b is corroded.
[0078]
As shown in FIGS. 19 and 20, the Al alloy film M3b is corroded on the surface of the second pad portion PAD2 by the pretreatment liquid before the Au film 53 is formed.
[0079]
FIG. 21 is a partially enlarged view of the vicinity of the target T of FIG. 14, and FIG. 22 is a plan view of a main part of the vicinity of the target T.
[0080]
As a result, the position of the target T cannot be recognized, and the fuse F cannot be cut accurately. FIGS. 15 to 20 are cross-sectional views or plan views of a main part of a substrate showing a manufacturing process of a semiconductor integrated circuit device for describing the effect of the present embodiment (FIG. 23 to FIG. 28 also). the same).
[0081]
23 to 25, the probe needle P is brought into contact with the first pad portion PAD1 to perform a P test (FIG. 23), and the position of the target T is recognized by the laser beam RB (FIG. 23). 24), the fuse F can be cut (FIG. 25) before the seed layer 45 is removed or the pre-processing step for forming the Au film 53 is performed. In this case, the rewiring 49 and the polyimide resin are used after the P inspection. There is a process for forming the film 51, the Au film 53, and the like. Damage due to a thermal load (for example, post-baking of the polyimide resin film 51) during these forming processes is not reflected in the P inspection, and the redundancy repair is incomplete. Become. As a result, the yield decreases. In the case of a DRAM memory, the damage due to the thermal load includes, for example, a decrease in a refresh margin.
[0082]
26 to 28, for example, the target T is covered with the passivation film 41 (FIG. 26), and after the removal of the seed layer 45 and the pre-processing step at the time of forming the Au film 53 (FIG. 27). Before the fuse F is cut, a method of removing the passivation film 41 on the target T and forming the opening OA (FIG. 28) can be considered, but in this case, the number of steps of removing the passivation film 41 increases.
[0083]
On the other hand, in the present embodiment, the above effects can be obtained while avoiding these problems.
[0084]
(Embodiment 2)
In the first embodiment, the target T is formed on the passivation film 41 in the scribe region SA. However, after the passivation film 41 in the scribe region SA and the insulating film thereunder are etched to form a groove, the inside of the groove is formed. The target T may be formed by embedding a conductive film in the substrate.
[0085]
The steps up to the step of forming the third-layer wiring M3 are the same as those in the first embodiment described with reference to FIGS. 4 and 5, and a description thereof will be omitted.
[0086]
As shown in FIG. 29, a passivation film 41 is formed on the third-layer wiring M3 in the same manner as in the first embodiment, and then the passivation film 41 on the third-layer wiring M3 is removed by dry etching. The first pad part PAD1 on the three-layer wiring M3 is exposed.
[0087]
At this time, the passivation film 41 on the fuse F and the insulating film (such as 33) thereunder are removed, a groove 42 is formed, and a groove 63 is formed on the scribe area SA. The pattern of the groove 63 is substantially L-shaped, and its width is about 10 μm (see FIG. 34).
[0088]
Next, as in the first embodiment, a polyimide resin film 43 having an opening on the scribe area SA, the first pad portion PAD1, and the groove 42 is formed, and a seed layer 45 is formed thereon.
[0089]
Next, as in the first embodiment, a resist film R having a long groove 47 and a substantially L-shaped groove 47t is formed (FIG. 30), and a Cu film 49a and a Ni film 49b are formed therein by electrolytic plating. Then, after removing the resist film R, the seed layer 45 is removed using the Cu film 49a and the like as a mask. As a result, a redistribution wiring 49 including the Cu film 49a, the Ni film 49b, and the seed layer 45 and the target T are formed (FIG. 31). This target T is formed in the groove 63. FIG. 33 shows a partially enlarged view of the target T portion in FIG. FIG. 34 is a plan view of a main part of the target T portion.
[0090]
Next, as shown in FIG. 32, as in the first embodiment, a polyimide resin film 51 having openings in the second pad portion PAD2 and the scribe area SA on the rewiring 49 is formed, and is exposed from the second pad portion PAD2. After performing a surface treatment (ashing treatment, alkali degreasing treatment, acid cleaning, etc.) on the Ni film 49b thus formed, an Au film 53 is formed on the surface thereof. At this time, the Au film 53 is also formed on the target T.
[0091]
Thereafter, as in the first embodiment, a P test is performed using the Au film 53 on the second pad portion PAD2, and further, after the target T is recognized by the laser rescue machine, the fuse F is cut.
[0092]
Next, a bump electrode 55 is formed on the Au film 53 in the same manner as in the first embodiment, and further mounted on the mounting substrate 60 or the like.
[0093]
As described above, according to the present embodiment, since the target T is formed of the same layer as the rewiring and is formed inside the trench, for example, a pretreatment at the time of forming the seed layer etchant or the Au film is performed. Corrosion of the target by the liquid can be prevented, and the position of the target T can be accurately recognized.
[0094]
(Embodiment 3)
By reducing the pattern width of the groove 63 without growing the plating film in the groove 63 of the second embodiment, the seed layer 45 may be left inside the groove 63 and such a film may be used as a target.
[0095]
That is, as described in the second embodiment with reference to FIG. 29, the groove 63 is formed in the scribe area SA. However, the pattern of the groove 63 is substantially L-shaped, and its width is about 1 to 5 μm (see FIG. 38).
[0096]
Next, similarly to the second embodiment, a polyimide resin film 43 and a seed layer 45 are formed, and a resist film R having a long groove 47 is formed. At this time, as shown in FIG. Cover with R, and do not form a plating film (Cu film 49a and Ni film 49b).
[0097]
Next, as in the second embodiment, after forming a plating film in the groove 47, the resist film R is removed, the seed layer 45 is removed using the Cu film 49a or the like as a mask, and a rewiring 49 is formed (FIG. 36).
[0098]
At this time, since the width of the pattern of the groove 63 is small, the seed layer 45 is thickly deposited on the bottom thereof, and the etching is difficult to proceed. Therefore, as shown in FIG. The layer 45 (target T) remains. FIG. 37 is a partially enlarged view of the target T portion in FIG. FIG. 36 is a plan view of a main part of the target T portion.
[0099]
Next, as in Embodiment 2, a polyimide resin film 51 is formed, a surface treatment of the Ni film 49b is performed, and then an Au film 53 is formed on the surface.
[0100]
Thereafter, as in the second embodiment, a P test is performed using the Au film 53 on the second pad portion PAD2, and further, after the target T is recognized by the laser rescue machine, the fuse F is cut.
[0101]
Next, a bump electrode 55 is formed on the Au film 53 in the same manner as in the second embodiment, and further mounted on the mounting substrate 60 or the like.
[0102]
As described above, according to the present embodiment, since the target T is formed of the seed layer 45, corrosion of the target can be prevented, and the position of the target T can be accurately recognized.
[0103]
Further, in the present embodiment, as shown in FIG. 37, the surface of the target T can be made lower than the surface height of the passivation film 41, and the passivation film 41 can be formed irrespective of the positional accuracy of an exposure machine used for forming a resist film. Is obtained.
[0104]
(Embodiment 4)
In the present embodiment, a polyimide resin film 51 is left over the target of the second embodiment.
[0105]
As shown in FIG. 39, the rewiring 49 and the target T are formed as in the second embodiment.
[0106]
Next, as shown in FIG. 40, similarly to the first embodiment, a polyimide resin film 51 having an opening in the second pad portion PAD2 and the like on the rewiring 49 is formed. The resin film 51 is left. FIG. 42 is a partially enlarged view of the target T portion in FIG. FIG. 43 is a plan view of a main part of the target T portion.
[0107]
Thereafter, a surface treatment is performed on the Ni film 49b exposed from the second pad portion PAD2, and an Au film 53 is formed on the surface (FIG. 41).
[0108]
Thereafter, as in the first embodiment, a P test is performed using the Au film 53 on the second pad portion PAD2, and further, after the target T is recognized by the laser rescue machine, the fuse F is cut. At this time, since the organic film such as the polyimide resin film 51 transmits the reflected light of the target T, the target T under the organic film can be recognized.
[0109]
As described above, according to the present embodiment, similarly to the second embodiment and the like, the corrosion of the target can be prevented, and the position of the target T can be accurately recognized.
[0110]
(Embodiment 5)
In the present embodiment, the target T is formed of the same layer as the third layer wiring M3, and the polyimide resin film 43 is left on the target.
[0111]
The steps up to the formation of the second-layer wiring M2 and the plug P3 are the same as those in the first embodiment described with reference to FIG.
[0112]
As shown in FIG. 44, for example, a TiN film M3a, an Al alloy film M3b, and a TiN film M3c are sequentially deposited on the silicon oxide film 33 and the plug P3, and are patterned into a desired shape to form a third-layer wiring M3. I do. At this time, the target T is formed in the scribe area SA with a film of the same layer as the film constituting the third-layer wiring M3. That is, the target T includes the TiN film M3a, the Al alloy film M3b, and the TiN film M3c. The pattern of the target T is substantially L-shaped, and its width is about 10 μm (see FIG. 48).
[0113]
Next, as in the first embodiment, a passivation film 41 is formed, and then the passivation film 41 on the third-layer wiring M3 is removed by dry etching to expose the first pad portion PAD1. At this time, the passivation film 41 covering the target T is also removed, and an opening OA is formed. Next, the TiN film M3c exposed from the first pad portion PAD1 and the opening OA is removed. Note that it is not necessary to remove all the passivation films 41 and the like on the target T. For example, as shown in FIG. 48, the pattern of the opening OA may be an inverted L-shape.
[0114]
Then, as shown in FIG. 45, similarly to the first embodiment, a polyimide resin film 43 having an opening on the first pad portion PAD1 and the groove 42 is formed. At this time, the polyimide resin film 43 is left so as to cover the target T. FIG. 47 is a partially enlarged view of the target T portion in FIG. FIG. 48 is a plan view of a main part of the target T portion.
[0115]
Next, as shown in FIG. 46, a resist film R having a groove 47 is formed in the same manner as in the first embodiment. Is used as a mask to remove the seed layer 45 to form a rewiring 49.
[0116]
Next, as in the first embodiment, a polyimide resin film 51 is formed, a surface treatment of the Ni film 49b is performed, and then an Au film 53 is formed on the surface.
[0117]
Thereafter, as in the first embodiment, a P test is performed using the Au film 53 on the second pad portion PAD2, and after the target T is recognized by the laser rescue machine, the fuse F is cut. At this time, since the polyimide resin film 43 transmits the reflected light of the target T, the lower target T can be recognized.
[0118]
As described above, according to the present embodiment, since the polyimide film is left on the target T made of an Al alloy film or the like, for example, the target is etched by the seed layer etchant or the pretreatment liquid at the time of forming the Au film. Corrosion can be prevented, and the position of the target T can be accurately recognized.
[0119]
(Embodiment 6)
In the present embodiment, the target T is formed of the same layer as the third-layer wiring M3, and the uppermost TiN film M3c is left.
[0120]
In the fifth embodiment, as described with reference to FIG. 44, the passivation film 41 is formed, and then the first pad portion PAD1 on the third-layer wiring M3 is exposed to cover the target T. After removing 41 and forming the opening OA, the exposed TiN film M3c is further removed. In the present embodiment, as shown in FIG. 49, the TiN film M3c remains. This TiN film has a high resistance to the etchant for the seed layer 45 and the pretreatment liquid for forming the Au film 53.
[0121]
FIG. 49 is a partially enlarged view of the target T portion, and FIG. 50 is a plan view of a main portion of the target T portion.
[0122]
As described above, in the present embodiment, since the TiN film M3c on the target T is left, for example, an Al alloy film constituting the target T by an etchant for the seed layer or a pretreatment liquid for forming the Au film. Corrosion of M3b can be prevented, and the position of the target T can be accurately recognized.
[0123]
The manufacturing process of the semiconductor device of the present embodiment is the same as that of the fifth embodiment except that the TiN film M3c on the target T is left and the polyimide resin film 43 on the target T is not formed. Therefore, the detailed description is omitted.
[0124]
Of course, as shown in FIGS. 51 and 52, the polyimide resin film 43 may be left on the target T where the TiN film M3c is left, as described in the fifth embodiment. FIG. 51 is a partially enlarged view of the target T portion, and FIG. 52 is a plan view of a main portion of the target T portion.
[0125]
(Embodiment 7)
In the fifth and sixth embodiments, the target T is formed of the same layer as the third-layer wiring M3, and the TiN film M3c and the polyimide resin film 43 thereon are left. The wiring M3 may be formed using a copper film.
[0126]
The steps up to the formation of the second-layer wiring M2 and the plug P3 are the same as those in the first embodiment described with reference to FIG.
[0127]
As shown in FIG. 53, for example, after a silicon nitride film 35a and a silicon oxide film 35b are sequentially deposited on the silicon oxide film 33 and the plug P3, the insulating film on the plug P3 is removed to form a wiring groove 37a. At this time, the target groove 37b is also formed on the scribe area SA. The groove pattern is substantially L-shaped and has a width of about 10 μm (see FIG. 59).
[0128]
Next, as shown in FIG. 54, a copper film 39 is deposited on the silicon oxide film 35b including the insides of the grooves 37a and 37b by using, for example, a plating method, a CVD method, or a sputtering method.
[0129]
Next, as shown in FIG. 55, the copper film 39 outside the trenches 37a and 37b is removed by, for example, a CMP (Chemical Mechanical Polishing) method to form a target T and a third layer wiring M3.
[0130]
Next, as in the first embodiment, a passivation film 41 is formed on the third layer wiring M3 and the like, and the first pad portion PAD1 and the like on the third layer wiring M3 are exposed. A polyimide resin film 43 having an opening on one pad portion PAD1 and the groove 42 is formed (FIG. 56). At this time, the passivation film 41 remains on the target T. FIG. 58 is a partially enlarged view of the target T portion, and FIG. 59 is a plan view of a main portion of the target T portion.
[0131]
Further, similarly to the first embodiment, after forming the Cu film 49a and the Ni film 49b, the seed layer 45 is etched using these films as a mask to form the rewiring 49. Next, a polyimide resin film 51 having openings in the second pad portion PAD2 and the scribe area SA on the rewiring 49 is formed, and the surface treatment (ashing, alkali degreasing, Acid cleaning etc.) to form an Au film 53 on the surface (FIG. 57).
[0132]
Thereafter, as in the first embodiment, a P test is performed using the Au film 53 on the second pad portion PAD2, and further, after the target T is recognized by the laser rescue machine, the fuse F is cut. At this time, the reflected light of the copper film constituting the target T can be detected even through the passivation film 41. Therefore, the position of the target T can be recognized.
[0133]
Next, a bump electrode 55 is formed on the Au film 53 in the same manner as in the first embodiment, and further mounted on the mounting substrate 60 or the like.
[0134]
As described above, according to the present embodiment, since the target T is formed of the copper wiring and the passivation film 41 is left on the target T, for example, the pretreatment at the time of forming the seed layer etchant or the Au film is performed. Corrosion of the target by the liquid can be prevented, and the position of the target T can be accurately recognized.
[0135]
(Embodiment 8)
In the first embodiment and the like, the target T is substantially L-shaped, but the pattern shape of the target is not limited to such a shape. For example, as shown in FIG. It may be a shape (rectangular) pattern.
[0136]
Also in this case, the reference point RP can be determined by scanning the laser in the X and Y directions and measuring a change in the reflection intensity of the laser.
[0137]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0138]
In particular, in Embodiment 1 and the like, a DRAM memory cell has been described as an example of a memory cell. However, the present invention can be widely applied to a semiconductor integrated circuit device that performs redundancy repair of a memory cell, such as an SRAM or a nonvolatile memory. is there. The fuse is not limited to a fuse for redundancy repair of a memory cell.
[0139]
In the first embodiment, the fuse F is made of the same film as the gate electrode G. However, the fuse may be made of the same layer as the wiring and the plug.
[0140]
In Embodiment 1 and the like, the target is formed in the scribe area SA, but the target may be formed in the chip area CA. However, from the viewpoint of high integration of the element, it is desirable to form the scribe area SA.
[0141]
Further, a wiring or a rewiring formed in the chip area CA may be used as a target.
[0142]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0143]
The target and its vicinity are devised, such as forming a target (alignment mark) with a film of the same layer as the rewiring extending from the first pad region to the second pad region, and the fuse is cut based on the position. Therefore, the recognition accuracy of the target can be improved, and the cutting accuracy of the fuse can be improved.
[0144]
Further, the yield of the semiconductor integrated circuit device can be improved, and its characteristics can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor wafer on which a semiconductor integrated circuit device according to a first embodiment of the present invention is formed.
FIG. 2 is a cross-sectional view of a main part of a substrate showing a memory cell part of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 3 is an enlarged view of the vicinity of a chip region in FIG. 1;
FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 1 of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 11 is a fragmentary cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 12 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 1 of the present invention;
FIG. 13 is a main part plan view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 14 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 15 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device, for illustrating the effect of the first embodiment of the present invention;
FIG. 16 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device for showing the effect of the first embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device for showing the effect of the first embodiment of the present invention;
FIG. 18 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device for showing the effect of the first embodiment of the present invention;
FIG. 19 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 20 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device, for illustrating the effect of the first embodiment of the present invention;
FIG. 21 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 22 is a plan view of a principal part of the substrate showing a manufacturing step of the semiconductor integrated circuit device for showing the effect of the first embodiment of the present invention.
FIG. 23 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 24 is a main-portion cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 25 is a main-portion cross-sectional view of the substrate in a manufacturing step of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 26 is a main-portion cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device, for illustrating the effect of the first embodiment of the present invention;
FIG. 27 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device, for illustrating the effect of the first embodiment of the present invention;
FIG. 28 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device for illustrating the effect of the first embodiment of the present invention;
FIG. 29 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 30 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 31 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 32 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 33 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 2 of the present invention;
FIG. 34 is a main part plan view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;
FIG. 35 is an essential part cross sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device of Embodiment 3 of the present invention;
FIG. 36 is a main-portion cross-sectional view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 3 of the present invention;
FIG. 37 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 3 of the present invention;
FIG. 38 is a plan view of main parts of a substrate, showing a manufacturing step of the semiconductor integrated circuit device according to the third embodiment of the present invention;
FIG. 39 is an essential part cross sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device which is Embodiment 4 of the present invention;
FIG. 40 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 4 of the present invention;
FIG. 41 is an essential part cross sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device of Embodiment 4 of the present invention;
FIG. 42 is an essential part cross sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device of Embodiment 4 of the present invention;
FIG. 43 is a fragmentary plan view of the substrate, illustrating a manufacturing step of the semiconductor integrated circuit device according to Embodiment 4 of the present invention;
FIG. 44 is an essential part cross sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device of Embodiment 5 of the present invention;
FIG. 45 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 5 of the present invention;
FIG. 46 is a main-portion cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 5 of the present invention;
FIG. 47 is a fragmentary cross-sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 5 of the present invention;
FIG. 48 is an essential part plan view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device which is Embodiment 5 of the present invention;
FIG. 49 is an essential part cross sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 6 of the present invention;
FIG. 50 is an essential part plan view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device which is Embodiment 6 of the present invention;
FIG. 51 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of another semiconductor integrated circuit device according to Embodiment 6 of the present invention;
FIG. 52 is a main part plan view of the substrate, illustrating a manufacturing step of another semiconductor integrated circuit device according to Embodiment 6 of the present invention;
FIG. 53 is an essential part cross sectional view of the substrate, showing a manufacturing step of the semiconductor integrated circuit device which is Embodiment 7 of the present invention;
FIG. 54 is a fragmentary cross-sectional view of the substrate showing a manufacturing step of the semiconductor integrated circuit device of Embodiment 7 of the present invention;
FIG. 55 is an essential part cross sectional view of the substrate showing the manufacturing process of the semiconductor integrated circuit device of Embodiment 7 of the present invention;
FIG. 56 is an essential part cross sectional view of the substrate for showing a manufacturing step of the semiconductor integrated circuit device which is Embodiment 7 of the present invention;
FIG. 57 is an essential part cross sectional view of the substrate for showing a manufacturing step of the semiconductor integrated circuit device of Embodiment 7 of the present invention;
FIG. 58 is a cross-sectional view of a principal part of a substrate, showing a manufacturing step of the semiconductor integrated circuit device according to the seventh embodiment of the present invention;
FIG. 59 is a plan view of relevant parts of a substrate, showing a manufacturing step of the semiconductor integrated circuit device according to Embodiment 7 of the present invention;
FIG. 60 is a main part plan view of a substrate showing a target portion of a semiconductor integrated circuit device according to an eighth embodiment of the present invention;
[Explanation of symbols]
1 semiconductor substrate (substrate)
3 element separation
5 p-type well
7 Gate insulating film
9, 11 source and drain regions
13a Polycrystalline silicon film
13b WN film
13c W film
15 Silicon nitride film
17 Silicon nitride film
21 Upper electrode
23 Capacitive insulating film
25 Lower electrode
27a-27e Silicon oxide film
31 Silicon oxide film
32 silicon oxide film
33 silicon oxide film
35a Silicon nitride film
35b silicon oxide film
37a, 37b groove
39 Copper film
41 Passivation film
41a Silicon nitride film
41b silicon oxide film
42 grooves
43 Polyimide resin film
45 Seed layer
47, 47t groove
49 Rewiring
49a Cu film
49b Ni film
51 Polyimide resin film
53 Au film
55 Bump electrode
60 Mounting board
62 Underfill resin
63 grooves
BL bit line
C Capacitance element for information storage
CA chip area
F fuse
FA fuse area
G gate electrode
M1 First layer wiring
M2 Second layer wiring
M3 Third layer wiring
M3a TiN film
M3b Al alloy film
M3c TiN film
MA memory area
OA opening
P probe needle
P1 plug
P1a plug
P1b plug
P2 plug
P2a plug
P2b plug
P3 plug
PA peripheral circuit area
PAD1 1st pad part
PAD2 2nd pad part
MISFET for Qt information transfer
R resist film
RB laser light
RA redundant memory area
RP reference point
SA scribe area
T target
W semiconductor wafer

Claims (5)

(A) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region;
(B) forming a second conductive film in the chip area;
(C) forming a first insulating film on the second conductive film;
(D) exposing a first pad region by removing the first insulating film on the second conductive film;
(E) forming a third conductive film extending from the first pad region to the second pad region on the second conductive film,
Forming a fourth conductive film in the same layer as the third conductive film on the scribe region;
(F) forming a second insulating film on the third conductive film and the fourth conductive film;
(G) removing a second insulating film on the second pad region of the third conductive film;
(H) after the step (g), a step of cutting the first conductive film based on a position of the fourth conductive film;
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region;
(B) forming a second conductive film in the chip region, and forming a third conductive film in the same layer as the second conductive film on the scribe region;
(C) forming a first insulating film on the second and third conductive films;
(D) removing at least a part of the third conductive film by removing the first insulating film on the second and third conductive films, and removing a first pad region of the second conductive film; Exposing,
(E) forming a second insulating film on the second and third conductive films;
(F) exposing the first pad region by removing the second insulating film on the second conductive film, wherein the first pad region is exposed to cover the exposed region of the third conductive film. (2) leaving an insulating film;
(G) forming a fourth conductive film extending from the first pad region to the second pad region on the second conductive film;
(H) after the step (g), confirming the position of the exposed region of the third conductive film via the second insulating film, and cutting the first conductive film based on the position. When,
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region;
(B) forming a first wiring having a second conductive film and a third conductive film above the second conductive film in the chip region, and forming the second conductive film and a third conductive film above the second conductive film in the scribe region; Forming a pattern having:
(C) forming a first insulating film on the first wiring and the pattern;
(D) removing the first insulating film on the first wiring and the pattern to expose the first pad region of the third conductive film forming the first wiring, and forming the first pad forming the pattern; (3) exposing at least a part of the conductive film;
(E) forming a second wiring extending from a first pad region to a second pad region on the first wiring;
(F) after the step (e), cutting the first conductive film on the basis of the position of the exposed region of the pattern;
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a first conductive film in a chip region of a semiconductor wafer having a chip region and a scribe region;
(B) forming a groove in the chip area and the scribe area;
(C) forming a second conductive film in the groove;
(D) forming a first insulating film on the second conductive film;
(E) exposing the first pad region on the second conductive film by removing the first insulating film on the second conductive film in the chip region;
(F) forming a third conductive film extending from the first pad region to the second pad region on the second conductive film;
(G) after the step (f), confirming the position of the second conductive film in the scribe region via the first insulating film, and cutting the first conductive film based on the position When,
A method for manufacturing a semiconductor integrated circuit device, comprising: (A) a first conductive film formed in a chip region of a semiconductor substrate;
(B) a second conductive film formed in the chip area;
(C) a first insulating film formed on the second conductive film and exposing a first pad region of the second conductive film;
(D) a third conductive film extending from the first pad region to the second pad region on the second conductive film;
(E) a fourth conductive film formed on the outer peripheral portion of the chip region and having the same configuration as the third conductive film;
(F) a bump electrode formed on the second pad region of the third conductive film;
A semiconductor integrated circuit device comprising:

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