JP2009272605A - Method of manufacturing non-volatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a screening method that is carried out in short time and at low cost, and to provide a method of manufacturing a non-volatile semiconductor memory using such a screening method. <P>SOLUTION: The method is provided for manufacturing a non-volatile semiconductor memory which has a plurality of memory elements having a control gate and a floating gate. After a plurality of memory elements are formed, an erase voltage stress is applied to a plurality of the memory elements formed on the wafer of the volatile semiconductor memory of a finished final wiring process, then, the inside of the floating gate becomes electrically neutral by irradiating an electromagnetic wave on all the surface of the wafer. Afterward, a protective film without the penetration to an electromagnetic wave is formed on the upper surface, and whether it is good is determined by a wafer test. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having a plurality of memory elements each having a control gate and a floating gate.

  FIG. 7 is a plan view showing a general structure of a nonvolatile semiconductor memory device 1 having a plurality of memory elements each having a control gate and a floating gate, which is a subject of the present invention, and a plurality of control gates extending in the X direction ( A word line) 20 and a wiring layer (bit line) 60 extending a plurality of times in the Y direction. Further, the wiring layer 60 and a drain not shown in FIG. 7 are electrically connected by a drain contact 40. In FIG. 7, a state in which the conductive foreign material 22 is formed between some of the drain contacts 40 and the word lines 20 is illustrated. The conductive foreign matter 22 will be described later. In FIG. 7, in order to display the conductive foreign material 22, a part of the bit lines 60 is shown through for convenience.

  8 is a cross-sectional view taken along the line ab in FIG. As shown in FIG. 8, a P well 5, a source / drain 26, a gate oxide film 6, a floating gate 10, an ONO film 17, a control gate 20, sidewall insulating films 25 and 27, a drain contact 40, on a semiconductor substrate 4. An interlayer insulating film 41 and a wiring layer 60 are provided. A stacked film of the gate oxide film 6, the floating gate 10, the ONO film 17, and the control gate 20 is formed on the active region (P well 5) sandwiched between the source / drain 26, and via the drain contact 40. The drain 26 and the wiring layer 60 are electrically connected.

  FIG. 9 is an equivalent circuit diagram of the nonvolatile semiconductor memory device 1 shown in FIG. A plurality of memory elements are arranged in a matrix, and the control gates of the memory elements existing in the same row are electrically connected to form the word line 20. Further, the drains of the memory elements existing in the same column are electrically connected to form the bit line 60. Note that the source of each memory element is also electrically connected to form a source line 70. The bit line 60 is connected to the column decoder 71, and the word line 20 is connected to the row decoder 72.

  With the progress of miniaturization technology in recent years, the distance between the gate (control gate 20, floating gate 10) and the drain contact 40 is shortened, and there is a possibility that a short circuit occurs between them. Further, in some cases, conductive foreign matters may be mixed in the apparatus during the manufacturing process, and there is a possibility that a short circuit occurs through the foreign matters.

  FIG. 10 is a cross-sectional view taken along the line a-c in FIG. 7 and shows a case where the conductive foreign matter is inherent. When the drain contact 40 and the control gate 20 are short-circuited due to the presence of the conductive foreign material 22, the potential of the control gate 20 cannot be controlled, and a defective state is caused in the memory element.

  FIG. 11 shows a case where the drain contact 40 and the control gate 20 are short-circuited due to the presence of the conductive foreign material 22 in one region in the equivalent circuit diagram of the nonvolatile semiconductor memory device 1 shown in FIG. is there.

  As shown in FIG. 11, when the drain contact 40 and the control gate 20 are short-circuited by the conductive foreign material 22, the predetermined bit line 60 and the word line 20 are short-circuited through the conductive foreign material 22. As a result, all memory devices existing on the same word line 20, that is, all memory devices located in the same row, become defective.

  Further, since the side wall insulating films 25 and 27 exist, even if the conductive foreign material 22 exists as shown in FIG. 10, the drain contact 40 and the control gate 20 are not completely short-circuited. As a result, a defective state cannot be recognized at the time of shipping selection, and the short circuit may occur while the final product user is using the product, and a problem may first manifest itself.

  Further, as described above, since the distance between the drain contact 40 and the control gate 20 has become very close with the miniaturization of the design other than the conductive foreign matter, the contact diameter, the drain contact 40 and the control gate are also reduced. The margin of 20 misalignment is reduced. As a result, due to variations in the process, the distance between the drain contact 40 and the control gate 20 is likely to be on the verge of short-circuiting. Even in such a case, it is possible that the defective state cannot be recognized at the time of shipping selection, and a short circuit may occur for the first time during the use of the product by the user of the final product, thereby causing a problem.

  Conventionally, screening based on the flowchart shown in FIG. 12 has been performed in order to prevent the product having such a defect from flowing into the market.

  First, after forming a plurality of memory elements on the wafer, the final wiring process is completed (step # 90). Next, a protective film made of a material that does not transmit ultraviolet light is formed on the surface, the terminal portion is opened (step # 91), and then a wafer test is performed (step # 92). A defective product is marked by wafer test, or electronic non-defective product map information is obtained.

  Next, the wafer is divided into chips, and package assembly is performed only for the chips that are determined to be non-defective by the wafer test (step # 93). Thereafter, in order to sort out defects during the package assembly process, a pre-test is performed to remove defective chips (step # 94).

  Next, burn-in accelerated at a high temperature and a high electric field is performed in order to sort out the deterioration mode failure (step # 95).

  After the burn-in is performed, a test voltage is sequentially applied to all the memory blocks using the burn-in apparatus (step # 96). At this time, the test voltage is applied by applying a negative voltage Vcg to the word line 20 and a positive voltage Vwell to the well 5. At this time, when the drain 26 of the memory element is opened, the PN junction constituted by the well 5 and the drain 26 is in the forward direction, so that the drain 26 has a built-in potential (diffusion potential) of the PN junction rather than the well voltage Vwell. Therefore, a potential of about 0.3 to 0.6 V / min is applied, so that the PN junction built-in potential between the drain 26 and the well 5 is subtracted between the word line 20 and the drain contact 40 from the potential difference between Vwell and Vcg. Voltage stress is applied. At this time, if there is an extremely thin insulating film between the control gate 20 and the drain 26, dielectric breakdown occurs due to this stress. As a result, since a defective state becomes apparent in the subsequent shipping test (step # 97), it is recognized that the product is defective before it flows out to the market, and it is possible to prevent the outflow of defective products to the market. . Only products that are determined to be non-defective products in the shipping test are shipped to the market (step # 98).

  In general, a flash memory is configured such that an erase voltage can be applied to a plurality of memory cells at once. For this reason, in order to shorten the test voltage application time, it is usual to apply an erase voltage as the test voltage. At this time, by applying the erase voltage, electrons in the floating gate 10 are extracted to the well 5 side, and the threshold value of the memory element is lowered (erased state).

  Here, in the case of a flash memory as shown in FIG. 9 as an equivalent circuit, if an erase voltage is excessively applied and the threshold value of the memory element becomes too low, conduction between the drain and the source is made. When a write voltage is applied to perform writing in such a state, no voltage is applied between the drain and the source, so that writing becomes impossible and the entire bit line 60 becomes defective. Therefore, when applying an erasing voltage stress, it is necessary to always manage so that an excessive erasing state is not caused by increasing the threshold value of the memory element by performing a writing process again after applying it with a short erasing voltage stress time that does not cause over-erasing. . That is, in step # 96, it is necessary to repeatedly apply the erase voltage stress and the write operation.

  When writing to the flash memory, the source is set to 0 V (ground potential), and a high voltage is applied to the drain to generate hot electrons near the drain, and at the same time, a positive voltage is applied to the control gate 20. Thus, the generated hot electrons are injected into the floating gate 10. At this time, since a necessary current value increases, it is difficult to write in many memory elements at a time. Therefore, since the number of memory elements that can be simultaneously written is limited, the method of performing writing for preventing excessive erasure after applying an erasing voltage stress requires a huge amount of time for screening.

  In order to shorten the screening time, a chip burn-in device capable of simultaneously burning in a plurality of chips has been conventionally used in order to efficiently apply stress. However, in order to use the chip burn-in apparatus, it is necessary to complete the package assembly process. For this reason, the chip determined to be defective as a result of the pass / fail determination by screening is a chip that has already completed the package assembly process, and the test cost and the package assembly cost that have been taken so far are wasted. As a result, the manufacturing cost loss increases.

  Further, as a method of recovering from the overerased state, there is a method of irradiating with ultraviolet light. However, when an ultraviolet light non-transmissive film such as a polyimide film or a silicon nitride film is used as a protective film, the ultraviolet light is a memory element. Since the floating gate 20 is not reached, it is impossible to recover from the over-erased state even if the ultraviolet light is irradiated under such a situation. In particular, recently, a so-called multi-chip package (MCP), in which a plurality of chips are stacked in the same package and assembled so as to have almost the same size as a single chip, has been frequently used. When this packaging is performed, a polyimide film, which is an ultraviolet light non-transparent material, is usually formed on the uppermost layer as a protective film for preventing scratches by stacking to a thickness of about 1 to 2 μm. For this reason, for such a multi-chip package, a method for recovering the memory cell from the over-erased state by irradiation with ultraviolet light cannot be used.

  As another conventional example, there is a technique in which a negative bias voltage is applied to the well to increase the threshold value of the memory cell and then the overerased cell is written after the circuit is devised (see FIG. 4). See Patent Documents 1 and 2 below). However, even if this technique is used, it is impossible to write to many cells at the same time, so that the time required for screening cannot be shortened.

JP-A-8-87892 JP 9-213913 A

  As described above, in the case of the conventional test method, an error occurs in the subsequent write operation when the over-erased state occurs, so it is confirmed whether or not over-erasure is performed in a predetermined memory cell unit (block unit). It had to be done and took a lot of time. In addition, there is a method of recovering from an over-erased state in a short time by irradiating many memory cells with ultraviolet light at a time, but a protective film having no ultraviolet light permeability has already been formed. Below, there was a problem that it was not possible to recover from an excessive state by irradiation with ultraviolet light.

  In view of the above problems, an object of the present invention is to provide a screening method that can be performed in a short time and at a low cost, and to provide a method for manufacturing a nonvolatile semiconductor memory device using such a screening method.

  In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device having a plurality of memory elements each having a control gate and a floating gate, and the plurality of memory elements. After the first wiring is formed, a first step of applying a predetermined test voltage to the plurality of memory elements formed on the wafer of the nonvolatile semiconductor memory device in which the final wiring step is completed, and the first step is completed Thereafter, an electromagnetic wave is applied to the entire surface of the wafer to make the floating gate electrically neutral. After the second process is completed, the upper surface of the wafer has transparency to the electromagnetic wave. A first feature is that it includes a third step of forming a protective film that is not to be formed and a fourth step of determining pass / fail by a wafer test after the completion of the third step.

  According to the first feature of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the test voltage application process has already been completed before the wafer test. For this reason, it is possible to confirm a defective state that becomes apparent when a test voltage is applied before the wafer test is performed. That is, in the wafer test stage, it is possible to perform pass / fail determination due to the application of the test voltage.

  For this reason, only the wafer determined to be non-defective in the wafer test stage is divided for each chip and package assembly is performed, so that the number of defective chips determined to be defective after the package assembly is completed can be reduced. That is, the number of chips whose defective state becomes obvious after the assembly of the package is reduced, and the waste of the package assembly cost can be prevented.

  In addition, since the electromagnetic wave is irradiated before the protective film is formed, the floating gate of each memory element on the wafer to which the test voltage is applied can be electrically neutralized at a time. it can. For this reason, especially when an erase voltage is used as the test voltage, the recovery process from the over-erased state can be performed in a short time, so that the entire processing time can be shortened.

  In addition to the first feature, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention may be configured such that the test voltage is applied to all the memory elements or a plurality of the memory elements in the first step. A second feature is that the voltage is for applying an erase voltage to the memory elements in one or a plurality of memory blocks configured as follows.

  According to the second feature of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, when there are a plurality of memory elements that are overerased by application of an erasing voltage when irradiated with electromagnetic waves. The over-erased state can be eliminated by making a transition to the neutral state collectively. For this reason, it is not necessary to apply the erase voltage while individually managing the overerased state, and the entire processing time can be shortened.

  In addition to the first or second feature, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention has a step in which the voltage applied to the gate oxide film under the floating gate increases with time in the first step. It is a third feature that the voltage value of the test voltage is increased stepwise so as to increase.

  According to the third feature of the nonvolatile semiconductor memory device according to the present invention, the test voltage can be applied while preventing a rapid increase in the electric field applied to the gate oxide film. As a result, the deterioration of the gate oxide film can be prevented, and the defective state of the non-volatile semiconductor memory device can be made obvious while shortening the time required for the test voltage application step.

  In addition to the third feature, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention is characterized in that the test voltage in the first step is that the electric field applied to the gate insulating film is determined by the dielectric strength of the gate insulating film. The fourth feature is that the voltage value is increased stepwise with time within a range not exceeding.

  According to the fourth feature of the nonvolatile semiconductor memory device according to the present invention, the defective state of the nonvolatile semiconductor memory device can be made apparent while maintaining the reliability of the nonvolatile semiconductor memory device.

  In addition to the first feature, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention may be configured such that the test voltage is a first write voltage indicating a predetermined first write pattern, and in the first step, The first write voltage is applied to a plurality of memory elements, and the fourth step applies a second write voltage indicating a second write pattern different from the first write pattern to the plurality of memory elements. The fifth feature is to include a test to be performed.

  According to the fifth feature of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the floating gates of the plurality of memory elements are temporarily electrically neutralized by electromagnetic wave irradiation after applying the first write voltage. Thereafter, a second write voltage different from the first write voltage is applied. That is, the write state of all the memory elements can be erased at a time after the first write voltage is applied. Therefore, a test of a defective state that becomes apparent depending on the first write pattern defined by the first write voltage and a failure state that becomes apparent depending on the second write pattern defined by the second write voltage Can be performed in a short time.

  In addition to any one of the first to fifth features, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes the first step and the fourth step in which a needle is placed on the upper surface of the wafer. A sixth feature is that a voltage is applied through the needle by contact.

  The manufacturing method of the nonvolatile semiconductor memory device according to the present invention has a seventh feature that, in addition to any one of the first to sixth features, the electromagnetic wave is ultraviolet light.

  According to the present invention, since the test voltage application process has already been completed at the stage before the wafer test is performed, it is possible to confirm the defective state that is manifested by the test voltage application at the stage before the wafer test is performed. For this reason, only the wafer determined to be non-defective in the wafer test stage is divided for each chip and package assembly is performed, so that the number of defective chips determined to be defective after the package assembly is completed can be reduced. That is, the number of chips whose defective state becomes obvious after the assembly of the package is reduced, and the waste of the package assembly cost can be prevented.

  In addition, because it is configured to irradiate an electromagnetic wave before forming a protective film, the floating gate of each memory element on the wafer to which the test voltage is applied is brought into an electrically neutral state at a time. Can do. For this reason, especially when an erase voltage is used as the test voltage, the recovery process from the over-erased state can be performed in a short time, so that the entire processing time can be shortened.

  Hereinafter, embodiments of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention (hereinafter referred to as “the method of the present invention” as appropriate) will be described with reference to the drawings. The method according to the present invention is used to determine whether or not the semiconductor memory device having a plurality of memory elements each including a control gate and a floating gate is acceptable after the final wiring process is completed and before it is shipped to the market. The test method has a feature. That is, the plan view and the cross-sectional view of the target nonvolatile semiconductor memory device are the same as those in FIGS. 7 and 8 described above, and the same components will be described with the same reference numerals.

[First Embodiment]
A first embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described. FIG. 1 is a flowchart showing the procedure of the method of the present invention according to this embodiment. First, after forming a plurality of memory elements on the wafer, the final wiring process is completed (step # 1). Thereafter, a test voltage is applied under the state before forming the protective film (step # 2). Specifically, the erase voltage is applied as a test voltage. The chip can be applied only by inputting from a small number of terminals such as a grounding terminal, a voltage application terminal to the control gate 20, a voltage application terminal to the well 5, an application voltage mode setting terminal, etc. By providing a mode in which an erasing voltage stress can be applied to all of the memory blocks, stress can be efficiently applied to a plurality of chips even in a wafer state. In addition, the application of the erase voltage can reveal a short-circuit state between the control gate 20 and the drain contact 40.

  Note that the test voltage (erase voltage) stress is applied in step # 2 by applying a negative voltage to the word line 20 and a positive voltage to the well 5 or the drain 26 (drain contact 40). Can do. The method of applying a positive voltage to the well 5 is preferable from the viewpoint of easy circuit design for applying stress to the entire chip, but the method of the present invention is limited to the stress application method according to step # 2. Is not to be done.

  The voltage stress application according to step # 2 is performed before the formation of a protective film according to step # 4, which will be described later.

  After applying a test voltage (erase voltage) stress, ultraviolet light irradiation is performed in a wafer state (step # 3). Although there is a possibility that an overerased state is induced in the memory element due to the application of the erasing voltage, the inside of the floating gates 10 of all the memory cells is electrically centered by irradiating ultraviolet light in the wafer state. It is possible to return to a neutral state (initial state), and the overerased state can be eliminated. Note that this step # 3 may be an irradiation process other than ultraviolet light as long as it is an electromagnetic wave that can electrically neutralize the floating gate 10 by irradiation.

  Then, after forming a protective film having no ultraviolet light transparency such as a polyimide film, the connection terminal portion is opened using a known method such as photoresist coating, exposure, development, dry etching, wet etching (step #). 4).

  Thereafter, a wafer test is performed to select non-defective products (step # 5). At this time, it is also determined whether or not a short circuit has occurred between the control gate 20 and the drain contact 40 due to the application of the test voltage according to Step # 2, and the pass / fail selection is performed. The wafer test according to Step # 5 is performed, for example, in a state where the needle is in contact with the upper surface of the pad after the protective film is formed. In this case, voltage application is performed with the needle in contact with the upper surface of the pad before and after the formation of the protective film.

  Next, the wafer is divided into chips, and package assembly is performed only on the wafer chips determined to be non-defective in the wafer test according to Step # 5 (Step # 6).

  Next, in order to select defects in the package assembly process, a pretest is performed before burn-in to remove defective chips (step # 7). Thereafter, burn-in accelerated at a high temperature and a high electric field is performed in order to select a failure in the deterioration mode (step # 8). After the burn-in, a shipping test is performed to determine pass / fail (step # 9), and only non-defective products are shipped (step # 10).

  In this embodiment, since the selection of the short-circuit mode failure between the control gate 20 and the drain contact 40 has already been completed at the stage of the wafer test related to Step # 5, the number of defective chips in the shipping test related to Step # 9 is Decrease. That is, the package assembly according to step # 6 is a configuration in which the package assembly is performed only for the chip in which the short-circuit mode failure does not occur in step # 5. It is possible to reduce the number of chips whose state becomes obvious and prevent waste of package assembly costs.

  In addition, since the method of this embodiment is configured to irradiate the ultraviolet light before forming the protective film, the memory cells of the entire wafer can be temporarily recovered from the over-erased state. For this reason, the processing time can be greatly shortened as compared with the method of confirming that the memory cell is not over-erased while performing the write operation for each predetermined memory cell unit or block unit.

[Second Embodiment]
A second embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described. This embodiment is characterized by the test voltage application method (step # 2) in the first embodiment, and the other steps (steps # 3 to # 10) are the same as those in the first embodiment. It is. Below, only a different part from 1st Embodiment is demonstrated.

  The test voltage (erase voltage) application step (step # 2) is intended to make the short-circuit state between the control gate 20 and the drain contact 40 particularly obvious. However, depending on the application method, excessive stress may be applied to the gate oxide film 6 to deteriorate the gate oxide film 6. Since the deterioration of the gate oxide film 6 causes a decrease in the reliability of the memory cell (flash cell), it is desirable to apply a test voltage under conditions that do not deteriorate the gate oxide film 6.

  On the other hand, when the voltage value of the test voltage is lowered in order to avoid the deterioration of the gate oxide film 6, a long application time is required to achieve the purpose of Step # 2 in which the short-circuit state becomes apparent. As a result, after step # 1, the time required to finish up to step # 10 becomes longer. This will be described with reference to FIG.

  FIG. 2 is a graph showing the relationship between the test voltage application time [sec] and the threshold voltage Vt [mV] of the flash memory cell. The test voltage is applied by applying a negative voltage to the word line (control gate) 20 and a positive voltage to the well 5. As a result, a potential difference is generated between the floating gate 10 and the well 4, and electrons are extracted from the floating gate 10 to the well 4 through the gate oxide film 6.

  Here, FIG. 2 shows the relationship between the test voltage application time and the threshold voltage Vt of the flash memory cell for each potential difference Vcg_sub between the control gate 20 and the well 5. According to this, it can be seen that under a certain Vcg_sub, the threshold voltage Vt decreases as the application time increases. Further, when Vcg_sub is increased, the threshold voltage Vt is decreased under the same application time, which indicates that the erase speed is high. If Vcg_sub is increased, the potential difference between the control gate 20 and the drain contact 40 increases. At this time, if a defective state exists between the control gate 20 and the drain contact 40, it is easy to cause a dielectric breakdown, whereby the defective state can be made apparent, and the screening effect is improved.

  However, when Vcg_sub is increased, the electric field Eox applied to the gate oxide film 6 increases. This will be described with reference to FIG.

  FIG. 3 is a graph showing the relationship between the threshold voltage and the electric field Eox for each potential difference Vcg_sub between the control gate 20 and the well 5. According to FIG. 3, when 16.5 V is applied as Vcg_sub in the state of Vt = 3000 [mV], the electric field Eox applied to the gate oxide film 6 exceeds about 12 MV / cm indicating the dielectric strength of the gate oxide film. . When the electric field Eox is high, a charge trap level is generated in the tunnel oxide film or at the interface due to the electrical stress, and electrons are likely to leak from the floating gate via the charge trap level, so that the charge retention characteristics are likely to deteriorate. This reduces the reliability of the flash cell.

  Conversely, if Vcg_sub is reduced, the electric field Eox applied to the gate oxide film 6 can be lowered, but the potential difference between the control gate 20 and the drain contact 40 of the cell is also reduced, so that it takes a long time to cause dielectric breakdown. Take it.

  The present embodiment is characterized in that, in step # 2, the test voltage is applied while increasing the voltage value stepwise. As an example, first, a test voltage of 13.5 V is applied for 20 seconds between the control gate 20 and the well 5 as a first stage, and then a test voltage of 14.5 V is applied for 20 seconds as a second stage. Thereafter, a test voltage of 15.5 V is applied for 20 seconds as a third stage, and then a test voltage of 15.5 V is applied for 20 seconds as a fourth stage. FIG. 4 shows the relationship between the application time and the threshold voltage when the test voltage is applied by such a method, and FIG. 5 shows the relationship between the threshold voltage and the electric field Eox.

  When the test voltage is applied in this way, the threshold voltage Vt decreases as shown by the arrow in FIG. At this time, the electric field Eox applied to the gate oxide film 6 changes along the arrow in FIG.

  Referring to FIGS. 4 and 5, the threshold voltage Vt can be lowered to a negative voltage range while ensuring the electric field Eox applied to the gate oxide film 6 at 10.2 MV / cm or less. That is, in step # 2, initially, the voltage applied between the control gate 20 and the well 5 is set to a low voltage, and the voltage value is increased step by step, whereby the electric field Eox applied to the gate oxide film 6 is rapidly increased. Test voltage can be applied while preventing. As a result, the failure state between the control gate 20 and the drain contact 40 can be made obvious while preventing the gate oxide film 6 from being deteriorated and shortening the time required for the test voltage application step.

  In addition, since each step after step # 3 is common to the first embodiment, the description thereof is omitted.

[Third Embodiment]
A third embodiment of the method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described. FIG. 6 is a flowchart showing the procedure of the method of the present invention according to this embodiment. In the process of performing the same process as in FIG. 1, the same step number is assigned and a detailed description is omitted.

  In the present embodiment, it is assumed that a defect that occurs depending on the writing pattern becomes obvious and only non-defective products are selected.

  In the present embodiment, after the final wiring process is completed (step # 1), a write voltage indicating a predetermined first write pattern is applied (step # 11). For example, “10101010” is adopted as the first writing pattern. By this step # 11, a defect that occurs when the pattern “10101010” is written becomes obvious. Specifically, for example, by applying a positive voltage for writing to the bit line 60 every other line, writing “0” to every other memory cell on the same word line 20, Writing of the first write pattern is performed. By performing the same writing every other line with respect to the word line 20, "10101010" is written every other line. At this time, if there is a defect depending on the pattern “10101010”, the defect becomes obvious.

  Next, the entire wafer is irradiated with ultraviolet light (step # 12). The written information (“10101010” in the above example) is erased by this ultraviolet light irradiation. Thereafter, after forming a protective film (step # 4), a wafer test is performed to select non-defective products (step # 5). In this wafer test, a test for applying a write voltage indicating a second write pattern different from the first write pattern is also performed (step # 13). For example, “01010101” is adopted as the second write pattern. Specifically, a voltage is applied so that writing is performed on the memory cell that has not been written in step # 11. In step # 13, a defect generated by writing the pattern “10101010” becomes obvious. Therefore, in the wafer test according to step # 5, a defective product that has become apparent in the first and second write patterns is detected, and a good product is detected. Only can be sorted out. That is, in steps # 11 and # 13, defects such as a short circuit between the bit lines 60 adjacent to the word line 20, a short circuit between the adjacent word lines 20, and a short circuit between the adjacent bit lines 60 become obvious. As a result of being determined as a defective product in step # 5, the product in which is made apparent is not supplied to the market.

  Thereafter, as in the first embodiment, the package assembly (step # 6), pre-test (step # 7), burn-in (step # 8), and shipping test (step # 9) are performed through the shipment (step # 9). # 10).

  When performing a writing test for a plurality of different writing patterns, it is necessary to perform erasing processing after writing one writing pattern and writing another different writing pattern. In this embodiment, since the first write pattern is written and then the second write pattern is written after the erase process is performed on all the memory cells at once by irradiation with ultraviolet light, the time required for the erase process is shortened. And the overall test time can be shortened. In the method of the present invention according to this embodiment, it is obvious that the first and second write patterns themselves are not affected.

  In addition, it is good also as a structure which performs step # 11-# 13 after each process of step # 1-# 3 in 1st Embodiment. As a result, it is possible to select a short-circuit mode failure between the control gate 20 and the drain contact 40 and to select a write failure depending on the first and second write patterns.

1 is a flowchart showing a procedure according to a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. Graph showing the relationship between test voltage application time and threshold voltage Graph showing relationship between threshold voltage and electric field applied to gate oxide film The graph which shows the relationship between the application time of a test voltage when a test voltage is applied using the method of 2nd Embodiment, and a threshold voltage The graph which shows the relationship between the threshold voltage when using the method of 2nd Embodiment, and the relationship of the electric field concerning a gate oxide film 9 is a flowchart showing a procedure according to a third embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. The top view which shows the general structure of the non-volatile semiconductor memory device which has multiple memory elements provided with a control gate and a floating gate Sectional drawing of the non-volatile semiconductor memory device which has multiple memory elements provided with a control gate and a floating gate Equivalent circuit diagram of a nonvolatile semiconductor memory device having a plurality of memory elements each having a control gate and a floating gate Sectional drawing when a conductive foreign substance exists in a nonvolatile semiconductor memory device having a plurality of memory elements each having a control gate and a floating gate Equivalent circuit diagram when conductive foreign matter exists in a nonvolatile semiconductor memory device having a plurality of memory elements each having a control gate and a floating gate Flow chart showing conventional screening method

Explanation of symbols

1: Nonvolatile semiconductor memory device 5: P well 6: Gate oxide film 10: Floating gate 17: ONO film 20: Control gate (word line)
22: Conductive foreign matter 25: Side wall insulating film 26: Source / drain 27: Side wall insulating film 40: Drain contact 41: Interlayer insulating film 60: Wiring layer (bit line)
70: Source line 71: Column decoder 72: Row decoder

Claims (7)

A method for manufacturing a nonvolatile semiconductor memory device having a plurality of memory elements each having a control gate and a floating gate,
A first step of applying a predetermined test voltage to the plurality of memory elements formed on the wafer of the nonvolatile semiconductor memory device after the final wiring process is completed after the plurality of memory elements are formed;
After the first step, a second step of bringing the inside of the floating gate into an electrically neutral state by irradiating the entire surface of the wafer with electromagnetic waves;
A third step of forming a protective film having no transparency to the electromagnetic wave on the upper surface of the wafer after the completion of the second step;
A non-volatile semiconductor memory device manufacturing method comprising: a fourth step of performing pass / fail judgment by a wafer test after the third step.   In the first step, the test voltage is erased at a time for all the memory elements or for the memory elements in one or a plurality of memory blocks constituted by a plurality of memory elements. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the voltage is for applying a voltage.   3. The voltage value of the test voltage is increased stepwise so that the voltage applied to the gate oxide film under the floating gate increases stepwise over time in the first step. A method for manufacturing the nonvolatile semiconductor memory device according to claim 1.   The test voltage in the first step is a stepwise increase in voltage value over time within a range in which an electric field applied to the gate insulating film does not exceed a dielectric strength of the gate insulating film. 4. A method for manufacturing a nonvolatile semiconductor memory device according to 3. The test voltage is a first write voltage indicating a predetermined first write pattern, and the first write voltage is applied to the plurality of memory elements in the first step;
2. The nonvolatile memory according to claim 1, wherein the fourth step includes a test in which a second write voltage indicating a second write pattern different from the first write pattern is applied to the plurality of memory elements. For manufacturing a conductive semiconductor memory device.   6. The method according to claim 1, wherein in each of the first step and the fourth step, a voltage is applied through the needle by bringing the needle into contact with the upper surface of the wafer. The manufacturing method of the non-volatile semiconductor memory device of description.   The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the electromagnetic wave is ultraviolet light.

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