JPH11354601A - Test and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid even recoverable nonvolatile memories from being classified as faulty in a screening test, because of charge traps generated by damages received in a memory manufacturing step. SOLUTION: In an EPROM, damages received in a wafer manufacturing step sometimes causes generation of charge traps in an oxide film of a gate. The trapped charges are divided into cases of defective charges and recoverable charges. When an annealing step P3 is carried out at 300 deg.C for 20 hours, the recoverable trapped charges are released and are recovered. Since the defective trapped charges are unrecoverable, they remain left. Thereafter, when a screening step P6 is carried out, a failure caused by the defective charge trap is determined surely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor device for finding defective charge retention failures occurring in a nonvolatile semiconductor memory device during a manufacturing process, and a wafer for such a nonvolatile semiconductor memory device. The present invention relates to a method for manufacturing a semiconductor device in a manufacturing process.

[0002]

As a nonvolatile semiconductor memory device, for example, an EPR erasable by ultraviolet rays is used.
There is an OM or an electrically rewritable EEPROM. In this case, for example, the charge injected due to the occurrence of a defective charge trap in the floating gate due to the damage received during the manufacturing process. May disappear earlier than in a normal state.

A screening test is performed on such defective charge retention failures in a nonvolatile semiconductor memory device in order to remove them in advance. First, as shown in FIG. 15, prior to the screening test, after the wafer manufacturing step S1 is completed, the ultraviolet irradiation step S2 is performed on the wafer on which the elements are formed.
UV irradiation is performed to erase all the data in the memory cells of each element, and then, a non-defective item (D / S; die sort) step S3 is performed to confirm the operation of each element.

Next, in a "0" data writing step S4, a charge is injected into a floating gate of a memory cell into a memory cell array of an element determined as a non-defective item in a non-defective item selecting step S3. Write processing is performed as "0". In this state, the screening step S5 is performed by leaving the substrate in a high-temperature atmosphere of, for example, about 300 ° C. for a predetermined screening time (for example, 20 hours). Thereafter, as a data reading step S6, it is determined whether or not the charge of the floating gate remains, that is, whether or not the state in which the data "0" is stored is maintained, and the data "0" is stored. An element that has not been used is determined to be defective (S7).

At this time, in order to determine whether or not data "0" is stored, the threshold voltage Vpp of the element memory cell array having the lowest value is measured and Vppmax is measured. If the value of Vppmax is lower than a certain value, the element can be determined to be defective.

By the way, in the screening test performed by the conventional method as described above, if a memory cell of an element is subjected to some kind of process damage during a wafer manufacturing process and a charge trap or the like is generated, as shown in FIG. In addition, Vppmax fluctuation may occur significantly in the damaged memory cell.

[0007] When such charge trapping occurs, the charge accumulated in the floating gate electrode during the screening test is discharged through the charge trap, causing a phenomenon that the data "0" is not generated. The storage state is lost, and it looks as if it is a defective charge retention defect. Due to these causes, there is a problem that a screening process for reliably removing defective defective charge retention defective products cannot be performed in a screening test.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electric charge generated due to process damage received during a wafer manufacturing process when performing a screening test of a nonvolatile semiconductor memory device. It is an object of the present invention to provide a method for testing a semiconductor device, which can reliably remove a recoverable one by a trap and reliably screen only a defective charge retention failure.

[0009]

SUMMARY OF THE INVENTION The present invention is directed to a method of testing a semiconductor device for finding defective charge retention defects occurring in a nonvolatile semiconductor memory device during a manufacturing process. Prior to performing a charge retention characteristic test step for finding a charge retention defect, an annealing step for releasing a recoverable non-defective charge trap that behaves similarly to the charge retention defect is performed. However, it has a feature (the invention of claim 1).

According to the above-described method for testing a semiconductor device, an annealing step is performed prior to the charge retention characteristic test step, and a non-recoverable charge retention defect generated in the manufacturing process of the nonvolatile semiconductor memory device is determined. As a result, it is possible to reliably determine only a defective charge retention failure by performing the charge retention characteristic test step.

In the above-described method for testing a semiconductor device, the charge retention characteristic test step may be performed, after the annealing step, in a state where data “0” is written in a memory cell of the nonvolatile semiconductor memory device at a predetermined temperature. (Invention of claim 2), or at a predetermined temperature in a state where charges are injected into the floating gate of the memory cell of the nonvolatile semiconductor memory device (invention of claim 3).

Further, in the above case, it is preferable that the charge retention characteristic test step is performed after the memory cell of the nonvolatile semiconductor memory device is subjected to an ultraviolet irradiation step of erasing data in the memory cell by ultraviolet irradiation. (Invention of claim 4).

[0013] In this case, the annealing step can be performed prior to the execution of the ultraviolet irradiation step (claim 5). Further, the annealing step can be performed after the ultraviolet irradiation step is performed (the invention of claim 6).

In the above-described method for testing a semiconductor device, it is preferable that the annealing step is performed under a temperature condition equal to or higher than the high-temperature leaving condition in the charge retention characteristic testing step (claim 7). Further, in the above case, the annealing step is performed by setting the nonvolatile semiconductor memory device to 300.
It is preferable that the heat treatment is performed for 10 hours or more at a temperature of ° C. (the invention of claim 8).

Further, in the invention according to the ninth aspect, regardless of whether or not the semiconductor device has been tested as described above, in the final step of the wafer manufacturing process, a recoverable non-defect that behaves similarly to a charge retention failure. Since the annealing step for releasing the charge trap is performed, only the chip having the non-recoverable defective charge trap causes the charge retention failure, and the recoverable chip can be obtained as a good product.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to screening for defective charge retention failure of an EPROM will be described below with reference to FIGS. FIG. 1 shows the contents of the flow of a test process in this embodiment, and is a process performed after a wafer manufacturing process P1 which is a process of manufacturing an EPROM 1 (see FIG. 2) as a target nonvolatile semiconductor memory device. Including an annealing step P3 which is a step which is a feature of the present invention,
Steps P2 to P8 are shown separately, and the test is performed as described later.

FIG. 2 shows a schematic cross section of one memory cell of an EPROM 1 formed on a silicon substrate in a wafer manufacturing process P1, for example, a p-type channel well 2 is formed on a silicon substrate. An n-type source region 3 and a drain region 4 are formed in the channel well 2 and formed so that a tunnel current can flow on a surface of a portion serving as a channel region between the source region 3 and the drain region 4. A floating gate electrode 6 made of polysilicon is formed via the oxide film 5 thus formed.

A polysilicon control gate electrode 8 is formed above the floating gate electrode 6 with an oxide film 7 between polysilicon layers interposed therebetween, and an aluminum oxide film 9 is formed so as to cover these. The gate terminal G is led out to the outside by a film or the like. Further, each of the source region 3 and the drain region 4 is
A source terminal S and a drain terminal D are led out to the outside by an aluminum film or the like.

The EPROM 1 thus formed
Indicates that the floating gate electrode 6 has a higher voltage (for example, V
g = 10.5 V), and electrons are injected as hot electrons through the oxide film 5.
In this state, the threshold value Vpp is increased, so that data "0" can be stored.

The floating gate electrode 6
Since it is formed in a state of being electrically insulated by both oxide films 5 and 7, when the above-mentioned data "0" is written, that is, when the electrons are injected, the injected electrons flow out anywhere. Since the stored state cannot be maintained, data "0" is stored.

On the other hand, when no electrons are injected into the floating gate electrode 6, no channel is formed between the source region 3 and the drain region 4, so that
It becomes an off state and can be held as a state in which data "1" is stored. In addition, data “0”
The electrons in the floating gate electrode 6 of the memory cell in which is written can be discharged by irradiating ultraviolet rays to erase data.

In the EPROM 1 operating as described above, it is important that the electric charge accumulated in the floating gate electrode 6 be held in a normal state. However, if any defect occurs in the oxide film 5 or the oxide film 7 used for charge injection due to damage received during the wafer manufacturing process P1, the defect becomes a charge trap and discharges through it. As a result, the ability to retain charges may be reduced.

In order to find a memory cell in which such a defect has occurred, the following screening test is performed as a charge retention characteristic test step. That is, as shown in FIG. 1, after completion of the wafer manufacturing process P1, first, each element of the wafer is irradiated with ultraviolet rays in an ultraviolet irradiation step P2, so that the electric charge of the floating gate electrode 6 of each memory cell is ensured. To erase the data.

Next, as an annealing step P3, a heat treatment is performed, for example, at a temperature of 300 ° C. and an annealing time of 20 hours. This annealing step P3 includes a wafer manufacturing step P1 in the oxide film 5 or oxide film 7 as described later.
In order to remove the recoverable charge traps and the like formed due to the damage received in the above,
According to the results of the experiment by the inventors, as described later, 30
It has been found that such recoverable charge traps can be removed by performing the process at a temperature of 0 ° C. for about 10 hours, and an annealing time of 20 hours is set for the purpose of ensuring practical use during this time. It is set as.

Next, a non-defective item selection (D / S) process P4 is performed to confirm the operation of the memory cell of each element,
In the data writing step P5, electric charges are injected into the floating gate electrode 6 to write data "0" into each memory cell, and the electric charges are held. In this state, a screening test is performed under predetermined conditions in a screening step P6. In this case, for example, the temperature is 300 ° C.
The accelerating test of the discharge of the stored charges is performed by leaving the substrate for about 20 hours in the approximately atmosphere for a screening time.

Thus, for example, when a defective charge trap is formed in the oxide films 5 and 7, the charge held in the floating gate electrode 6 by the acceleration test is transferred via the charge trap. Discharge occurs to the source region 3, the drain region 4, or the control gate electrode 8, and the storage state of data "0" cannot be maintained. Subsequently, in a data reading step P7, it is checked whether data "0" is stored and held, and a defective product determination P8 is performed.

FIG. 3 shows the process up to the defective product determination P8 when the screening process P6 is performed.
After the ultraviolet erasing step P2, the charge in the floating gate electrode 6 is completely discharged to erase data (see FIG. 3A). In this state, the frequency (bit number) distribution of the value of the threshold voltage Vpp of the memory cell array of the element becomes a distribution state as shown on the right side of FIG.

Next, in the "0" data write step P5, a high voltage is applied to the control gate electrode 8 to generate hot electrons, and charges are injected into the floating gate electrode 6 via the oxide film 5 ( FIG. As a result, the threshold voltage Vpp is increased, and the frequency (bit number) distribution of the value of Vpp is, as shown on the right side of FIG. Is shifted to the higher side as a whole.

Subsequently, in the screening step P6, if the device is left in a high temperature state (see FIG. 3C), the maintenance of the charge holding state is accelerated as compared with the normal temperature state. The conditions are the same as those when left for a long time. Therefore, the screening time (2
0 hours) (see (d) in the figure)
The charge stored in the floating gate electrode 6 is smaller than the charge amount in the initial state, and FIG.
, The threshold voltage Vpp also shifts slightly lower.

At this time, in the memory cell in which the defective charge retention failure has occurred, the threshold voltage Vpp
Is out of the distribution and becomes a low value. Therefore, in the diagram of the distribution state, data may be obtained as if a tail is drawn as shown in the figure. And the measured threshold voltage V
If the lowest value Vppmax of pp is equal to or higher than a predetermined level, it is determined that the memory cell is a normal memory cell, and if it is out of distribution and lower than the predetermined level, it is determined to be defective.

FIG. 4 illustrates a discharge phenomenon in a screening step in a memory cell in which a defective charge retention defect has occurred. For example, as shown in FIG. The case where a defect is caused in P1 by damage to each of the oxide films 5 and 7 at the position indicated by the mark “x” in the figure is shown.

The damaged portions in the oxide films 5 and 7 are trapped by electric charges (indicated by "+" in the figure), as shown in FIG. Flows easily. That is, when the screening step P6 is performed from the state where charges are injected into the floating gate electrode 6 in the “0” data writing step P5 (see FIG. 3C), the floating gate electrode 6
The electric charge accumulated therein escapes to the drain region 4 or the control gate electrode 8 through the electric charge trap, and is easily discharged. Therefore, the screening process P
At the end of step 6, the charge remaining in the floating gate electrode 6 is smaller than that of the normal memory cell (see FIG. 4D). This is defective charge retention failure.

On the other hand, FIG. 5 shows a recovering state in the case where a recoverable charge trap is provided. Now, for example, as shown in FIG. 1A, each of the oxide films 5 and 7 of a certain memory cell is damaged (indicated by a “◆” in the figure) in the wafer manufacturing process P1 to be damaged. Consider a case where a charge trap (indicated by a “+” mark in the figure) occurs as shown in FIG. Such charge trapping is not defective but irrecoverable, but temporary.

In this case, after erasing the data through the ultraviolet irradiation step P2, in the annealing step P3, 3
By performing the heat treatment at 00 ° C. for 20 hours, the electric charge trapped in the damaged portion is discharged, and the electric charge trap is removed (see FIG. 3C). As a result, in the non-defective item selection process P4 and subsequent steps P4 to P8, the memory cell can remain as a non-defective item, and only the memory cell in which defective charge traps are generated is determined as a defective item. It comes to be.

FIGS. 6 and 7 show an annealing step P3 (3
(00 ° C., 20 hours), a non-defective sample (indicated by “x” in FIG. 6) that does not include a defective charge trap and a defective sample that includes a defective charge trap (in FIG. 6) (Indicated by "△")) shows the result of screening in a high temperature state. FIG. 6 shows a change in the value of the threshold voltage Vppmax that changes with the passage of the screening time.
(A) and (b) respectively show the screening step P6
9 shows the frequency distribution of the threshold voltage Vpp of the non-defective sample and the defective sample obtained in the data reading step P7 after the completion of the above.

As can be seen from the results, in the non-defective sample, the value of the threshold voltage Vpp slightly decreases with the passage of the screening time, but the value obtained for each memory cell is within a slight variation range. The distribution is almost complete. On the other hand, in the defective sample, there is a memory cell in which the value of the threshold voltage Vpp is extremely reduced, and this value gradually decreases as the screening time elapses, and when the screening time of 20 hours elapses. In this case, as shown in the figure, Vppmax is in a state largely deviating from the entire distribution.

Next, the setting of the annealing time conditions in the annealing step P3 will be described together with the results of experiments conducted by the inventors. FIGS. 8 to 13 show transition states of the threshold voltage Vppmax that changes with the lapse of the screening time when the annealing time is 0 hour, 1 hour, 2 hours, 3 hours, 5 hours, and 10 hours, respectively. Is shown.

In this case, in the samples shown in FIG. 8 to FIG. 12 which were measured, the samples were determined to be non-defective when the non-defective product selection step P4 was performed after the annealing step P3 was completed. The samples that have become defective due to the execution of the process P6 are shown.
In this case, the trapping of charges is eliminated by performing the annealing step P3 for a period of time or longer, and the threshold voltage Vppmax is restored.

FIG. 13 shows that the recovery of charge traps disappeared by setting the annealing time at 10 hours, so that the threshold voltage Vppmax did not decrease even after the screening step P6. Is shown. Note that a defective product including a trap of defective charges is not shown here because it is not recovered by performing the annealing step P3.

From this result, in the case where the annealing time is from 0 hours to 5 hours (see FIG. 12), the phenomenon of the threshold voltage Vppmax still decreases, but when the annealing time is 10 hours. It can be seen from FIG. 13 that the decrease in the threshold voltage Vppmax is almost eliminated. Although not shown, it has been found that if the annealing time is longer than 10 hours, this does not cause another new defective product, so that the actual annealing time should be assured. 20 hours.

As a result, even if a trap of recoverable charges is included, the trapped charges can be released and restored as a good product by performing the annealing step P3. Therefore, when the screening process P6 is performed, only defective products caused by trapping of defective charges can be reliably determined as defective products.

The reason why the annealing temperature is set to 300 ° C. is that the temperature condition of the screening test is set for the convenience of the test process. To 300 ° C
In this case, if the annealing temperature is changed, it is expected that the annealing time will be different.

According to the present embodiment, prior to performing the screening step P6 as a charge retention characteristic test step, an annealing step P3 is provided to eliminate recoverable charge traps. At the time of performing the screening process P6, it is possible to perform the process while leaving only traps of irrecoverable defective charges.

FIG. 14 shows a second embodiment of the present invention. The difference from the first embodiment is that an ultraviolet irradiation step P is performed.
2 is omitted and the charge retention characteristic test step is performed. Then, the ultraviolet irradiation step P
2 can eliminate the trap of recoverable charges by performing the annealing step P3, and at the time of performing the screening step P6, the non-recoverable defective charges can be removed. This can be performed with only the trap left.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. As a step of injecting charges into the floating gate electrode 6, a write step P5 of data "0" is performed, but a case is adopted in which injecting charges into the floating gate electrode 6 does not result in a write state of data "0". In this case, data corresponding to the charge injection may be written.

The annealing step P3 includes an ultraviolet irradiation step P2.
May be performed before the execution. The annealing temperature in the annealing step P3 may be lower than 300 ° C. or higher. The annealing time is 20
The time is not limited to 10 hours and may be 10 hours or more.

In the above-described embodiment, a case has been described in which the present invention is applied to an EPROM. However, the present invention is not limited to this, and the present invention can also be applied to a nonvolatile semiconductor memory device such as an EEPROM or a flash EEPROM.

Further, in the above embodiment, the annealing step is performed as one of the charge retention failure test steps. However, regardless of such a test step, the annealing step is performed as one of the wafer manufacturing steps. It can also be positioned. That is, regardless of whether the charge retention failure test is performed or not, by performing the above-described annealing process at the final step of the wafer manufacturing process, a non-defective charge that can be recovered in a manufactured wafer state can be obtained. It is intended to eliminate traps.

As a result, a defective chip including a defective charge trap is identified by conducting a conventional test without performing the above-mentioned annealing step for the test step. Even if a test is not performed, a defective chip including a defective charge trap can be removed through a normal selection process and the like, and a recoverable one can be selected without being counted as a defect. Will be able to

[0050]

As described above, according to the method of testing a semiconductor device of the present invention, prior to performing a charge retention characteristic test step for finding a charge retention defect, a recovery behavior similar to the charge retention defect is performed. Since the annealing step for releasing possible non-defective charge traps is performed, the annealing step is performed prior to the charge retention characteristic test step, and the charge generated in the manufacturing process in the nonvolatile semiconductor memory device is performed. It is possible to recover a recoverable one of the retention failures. As a result, by performing the charge retention characteristic test process, it is possible to reliably determine only the defective charge retention failure as a failure. It has excellent effects.

Further, according to the method of manufacturing a semiconductor device of the present invention, in the final step of the wafer manufacturing step, an annealing step for releasing recoverable non-defective charge traps which behave similarly to charge retention failures is provided. As a result, the chips that are finally obtained as products are excluded from those containing recoverable non-defective charge traps, so that they can be counted as good products. In addition, even when such a chip is used in the charge retention characteristic test step, there is an excellent effect that a normal test step can be performed without separately performing an annealing step.

[Brief description of the drawings]

FIG. 1 is a process explanatory view showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a target storage element.

FIG. 3 is a diagram illustrating the principle of a screening test.

FIG. 4 is an explanatory view of charge retention failure due to defective charge traps.

FIG. 5 is an explanatory diagram of an operation when a non-defect charge trap is removed through an annealing step;

FIG. 6 is a diagram showing a transition of Vpp with respect to a screening time in a case where an annealing process is performed for a non-defective product and a defective product.

FIG. 7 is a diagram showing the distribution of Vppmax of each cell after the screening step in the case of performing an annealing step for a non-defective product and a defective product.

FIG. 8 is a diagram showing a result of a screening test when the annealing time is varied as a parameter (when the annealing time is 0 hour);

FIG. 9 is a diagram corresponding to FIG. 8 (when the annealing time is 1 hour)

FIG. 10 is a diagram corresponding to FIG. 8 (when the annealing time is 2 hours)

FIG. 11 is a diagram corresponding to FIG. 8 (when the annealing time is 3 hours);

FIG. 12 is a diagram corresponding to FIG. 8 (when the annealing time is 5 hours)

FIG. 13 is a diagram corresponding to FIG. 8 (when the annealing time is 10 hours);

FIG. 14 is a view corresponding to FIG. 1, showing a second embodiment of the present invention.

FIG. 15 is a diagram corresponding to FIG. 1 showing a conventional example.

FIG. 16 is a diagram showing the transition of Vppmax with respect to the screening time for defective products.

[Explanation of symbols]

1 is an EPROM (nonvolatile semiconductor memory device), 2 is a channel well, 3 is a source region, 4 is a drain region, 5
Is an oxide film, 6 is a floating gate electrode, 7 is an oxide film, 8 is a control gate electrode, 9 is an oxide film, P3 is an annealing step, and P5 to P7 are screening tests (charge retention characteristic test steps).

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 H01L 29/78 371 29/29/788 29/792

Claims (9)

[Claims] 1. A method for testing a semiconductor device for detecting defective charge retention defects occurring in a manufacturing process of a nonvolatile semiconductor memory device, comprising: a charge retention characteristic test step for detecting the charge retention defects. A method for testing a semiconductor device, comprising: performing an annealing step for releasing a trap of recoverable non-defective charges that behaves in the same manner as the charge retention failure before performing the step. 2. The test method for a semiconductor device according to claim 1, wherein in the charge holding characteristic test step, data “0” is written to a memory cell of the nonvolatile semiconductor memory device after the end of the annealing step. A test method for a semiconductor device, wherein the test is performed at a predetermined temperature in a state. 3. The method for testing a semiconductor device according to claim 1, wherein in the charge retention characteristic test step, after the annealing step, charges are injected into a floating gate of a memory cell of the nonvolatile semiconductor memory device. A test method for a semiconductor device, wherein the test is performed at a predetermined temperature in a state. 4. The method for testing a semiconductor device according to claim 2, wherein the charge retention characteristic test step erases data in the memory cell of the nonvolatile semiconductor memory device by irradiating the memory cell with ultraviolet light. A method for testing a semiconductor device, which is performed after performing an ultraviolet irradiation step. 5. The method for testing a semiconductor device according to claim 4, wherein the annealing step is performed prior to performing the ultraviolet irradiation step. 6. The method for testing a semiconductor device according to claim 4, wherein the annealing step is performed after performing the ultraviolet irradiation step. 7. The method for testing a semiconductor device according to claim 1, wherein the annealing step is performed under a temperature condition equal to or higher than a high-temperature storage condition in the charge retention characteristic test step. Semiconductor device testing method. 8. The method for testing a semiconductor device according to claim 7, wherein in the annealing, the non-volatile semiconductor storage device
A test method for a semiconductor device, characterized in that a heat treatment is performed at a temperature of 00 ° C. for 10 hours or more. 9. A method of manufacturing a semiconductor device for manufacturing a wafer of a nonvolatile semiconductor memory device having a floating gate, wherein a recoverable non-defective charge which behaves similarly to a charge retention failure is provided in a final step of the wafer manufacture. A method of manufacturing a semiconductor device, wherein an annealing step for releasing traps is performed.