JP2012094593A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve inspection properties of a semiconductor device.SOLUTION: A method of manufacturing a semiconductor device of the present invention comprises the steps of: (a) forming a conductive film (an aluminum film 10b) containing aluminum above a substrate; (b) forming wiring by patterning the conductive film; (c) forming a first insulating film (a first protective film) on the wiring; (d) exposing a pad region (Pd) of the wiring by etching the first insulating film; (e) performing a plasma treatment using a nitrogen plasma gas to the pad region (Pd); and (f) energizing the pad region (Pd) by contacting a probe needle to the pad region (Pd) after the step (e). Since an aluminum nitride layer (15) is formed on the pad region (Pd) through the step (e), the contact resistance between the pad region (Pd) and the probe needle (N) can be reduced.

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a configuration effective for a semiconductor device having a pad and a technique effective when applied to a method for manufacturing a semiconductor device having a pad.

  The semiconductor device has a semiconductor element such as a MISFET formed on a semiconductor substrate and a multilayer wiring formed above the semiconductor element. The uppermost layer wiring is covered with a protective film, and the opening of this protective film serves as a bonding pad. This bonding pad is an area for measuring electrical connection with an external terminal.

  By using the bonding pad, it is possible to check the electrical characteristics of the semiconductor device by energizing through the needle (probe needle). Such an inspection is called a probe test.

  For example, in the following Patent Document 1 (Japanese Patent Laid-Open No. 2002-75996), a step of forming a passivation film on the surface of a semiconductor substrate on which a desired element region and wiring layer are formed and a pad region to be externally connected are exposed. In order to prevent this, an etching process for etching the passivation film is disclosed. Further, after the etching processing step, the contact failure of the pad is reduced by the step of etching the wiring layer surface using an ammonium fluoride-containing liquid and the processing step of performing oxygen plasma treatment or ashing treatment on the wiring layer surface after the etching step. A technique for preventing and providing a highly reliable semiconductor device is disclosed.

  Japanese Patent Application Laid-Open No. 10-163280 discloses an inspection method for inspecting an electrical characteristic of an object to be inspected by bringing a contactor into contact with an electrode of the object to be inspected. Specifically, after plasma processing is performed on the object to be inspected in the plasma processing chamber to remove the oxide film on the electrode surface, the object to be inspected is transferred to the inspection room, There has been disclosed a technique for preventing the aluminum oxide shavings from adhering to the needle tip by inspecting the electrical characteristics of the object to be inspected by bringing the contact into contact therewith.

  Further, in the following Patent Document 3 (Japanese Patent Laid-Open No. 4-186838), after forming a wiring made of Al or an Al alloy, a removal process is performed to remove a contaminated layer on at least the upper surface of the wiring, and then exposed to the atmosphere. A technique for modifying the surface of a wiring without disclosing it is disclosed.

  Further, in Patent Document 4 (Japanese Patent Laid-Open No. 2-140923) described below, an aluminum alloy film is etched by plasma treatment using a gas mainly composed of ammonia without exposing the aluminum alloy film pattern to the atmosphere. A technology for efficiently removing chlorine and chloride adhering to the substrate surface later and preventing corrosion of the wiring is disclosed.

JP 2002-75996 A Japanese Patent Laid-Open No. 10-163280 Japanese Patent Laid-Open No. 4-186838 JP-A-2-140923

  According to the study of the present inventor, the contact resistance between the pad and the probe is increased efficiently as described in detail later in the probe test in the manufacturing process of the semiconductor device having the pad as described above. There was a situation where the inspection could not be performed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the inspection characteristics of the semiconductor device.

  Another object of the present invention is to provide a configuration of a semiconductor device capable of improving the inspection characteristics of the semiconductor device.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in this application, a method of manufacturing a semiconductor device shown in a typical embodiment includes (a) a step of forming a conductive film containing aluminum above a substrate, and (b) the conductive Forming a wiring by patterning the conductive film, and (c) forming a first insulating film on the wiring. And (d) a step of exposing the pad region of the wiring by etching the first insulating film; and (e) a step of performing a plasma treatment using a nitrogen-based plasma gas on the pad region. And (f) after the step (e), a step of bringing a probe needle into contact with the pad region and energizing the pad region.

  Among the inventions disclosed in the present application, a semiconductor device shown in a representative embodiment includes (a) a wiring containing aluminum formed above a semiconductor substrate, and (b) formed on the wiring. An antireflection film containing a nitrogen compound; and (c) a first insulating film formed on the antireflection film. And (d) an opening provided in the antireflection film and the first insulating film, the opening exposing the pad region of the wiring, and (e) formed in the pad region of the wiring. (F) The aluminum nitride film is thicker than the natural aluminum nitride film formed between the antireflection film and the first insulating film.

  Among the inventions disclosed in the present application, according to the method for manufacturing a semiconductor device shown in the following representative embodiment, the inspection characteristics of the semiconductor device can be improved.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the inspection characteristics of the semiconductor device can be improved, and the characteristics of the semiconductor device can be improved. it can.

7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of First Embodiment; 7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of First Embodiment; FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 2; FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 3; FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 4; FIG. 6 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 5; FIG. 7 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 6; FIG. 8 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 7; FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 8; FIG. 10 is a diagram for explaining the effect of the semiconductor device of the first embodiment, and is a cross-sectional view of a main part showing a contact state of the probe needle with respect to the pad region of the semiconductor device of the first embodiment. FIG. 10 is a diagram for explaining the effect of the semiconductor device of the first embodiment, and is a cross-sectional view of a principal part showing a contact state of a probe needle with respect to a pad region of a semiconductor device of a comparative example. A diagram for explaining an effect of the semiconductor device of the first embodiment, showing the resistance value of the pad region having been subjected to the NH ₃ plasma process of the first embodiment, the resistance of the pad region in Comparative Example It is a graph. FIG. 10 is a diagram for explaining the effect of the semiconductor device of the first embodiment, and is a graph showing the resistance value of the pad region in the first embodiment and the resistance value of the pad region in the comparative example. FIG. 6 is a plan view showing a manufacturing process (mounting process) of the semiconductor device of First Embodiment, and is a plan view showing an example of a semiconductor chip after dicing. FIG. 6 is a main-portion cross-sectional view showing the manufacturing process (mounting process) of the semiconductor device of First Embodiment; FIG. 6 is a main-portion cross-sectional view showing the manufacturing process (mounting process) of the semiconductor device of First Embodiment; FIG. 16 is a main-portion cross-sectional view illustrating the manufacturing process (mounting process) of the semiconductor device according to the first embodiment, and illustrating the process subsequent to FIG. 15; A diagram for explaining the effect of the semiconductor device of Embodiment 2 (Application Example 1) shows the resistance of the pad region subjected to N ₂ plasma treatment, the resistance of the pad region in Comparative Example It is a graph. A diagram for explaining the effect of the semiconductor device of Embodiment 2 (Application Example 2), the resistance value of the pad region subjected to N 2 _O plasma treatment, the resistance of the pad region in Comparative Example It is a graph to show. A diagram for explaining the effect of the semiconductor device of Embodiment 2 (Application Example 3) is a graph showing the resistance of the pad region subjected to mixed plasma treatment of N ₂ and O _2. FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 3; FIG. 22 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 21; FIG. 23 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 22; FIG. 24 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 23; FIG. 25 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 24. FIG. 26 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 25; FIG. 27 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 26; FIG. 28 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 27;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
Hereinafter, the configuration and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. 1 to 9 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. 10 to 13 are diagrams for explaining the effects of the semiconductor device according to the present embodiment. 14 to 17 are plan views or cross-sectional views showing the manufacturing process (mounting process) of the semiconductor device of the present embodiment.

[Description of structure]
First, with reference to FIG. 1 which is one of main cross-sectional views showing a manufacturing process of the semiconductor device of the present embodiment and FIG. 16 which is a partially enlarged view thereof, a characteristic of the semiconductor device of the present embodiment. The configuration will be described.

  As shown in FIG. 1, the semiconductor device of the present embodiment includes, for example, a p-channel MISFET Qp and an n-channel MISFET Qn as semiconductor elements formed on a semiconductor substrate (substrate) 1. In addition to the MISFET, other elements such as a resistance element and a memory cell may be included.

  On these MISFETs (Metal Insulator Semiconductor Field Effect Transistors), an interlayer insulating film TH1 (TH1a, TH1b) is formed. A first layer wiring M1 is formed on the source / drain regions (3n, 3p) of the MISFET via a plug P1. Further, a plurality of wiring layers (second layer wiring M2 to fourth layer wiring M4) are formed on the first layer wiring M1. The wiring layers are electrically connected by plugs P2 to P4, and the other regions are electrically insulated by interlayer insulating films TH2 to TH4.

  The first layer wiring M1 to the fourth layer wiring M4 are damascene wirings made of a metal such as so-called copper (Cu). The fifth layer wiring M5 which is the uppermost layer wiring is a wiring made of aluminum (a conductive film containing aluminum). The fifth layer wiring M5 and the fourth layer wiring M4 are electrically connected by a plug P5, and the other regions are electrically insulated by an interlayer insulating film TH5.

  The first layer wiring M1 to the fourth layer wiring M4 may be aluminum (Al) wiring. However, since the pad region Pd is provided in the uppermost layer wiring (here, the fifth layer wiring M5), it is preferable to use an aluminum wiring having high corrosion resistance.

  A first protective film (12, 13) and a second protective film (photosensitive polyimide film 16) are formed on the fifth layer wiring M5, and a fifth layer wiring (aluminum film 10b) is formed from the opening OA of these films. ) M5 is exposed. This exposed portion becomes the pad region Pd.

  Here, as a characteristic configuration of the semiconductor device of the present embodiment, as shown in FIG. 1, an aluminum nitride layer 15 which is a film formed by plasma nitriding is disposed on the surface of the pad region Pd.

  As will be described in detail later, a probe test is performed using the pad region Pd. Therefore, probe marks (not shown in FIG. 1, refer to FIG. 10) are generated in the pad region Pd.

  A wire W for electrical connection with a wiring board (WB) to be described later is disposed on the pad region Pd. The aluminum nitride layer 15 is a film having low conductivity. However, as will be described in detail later, the aluminum nitride layer 15 is easy to break, and the wire W and the fifth layer wiring (aluminum film 10b) are formed through a crack (not shown). Electrical connection with M5 can be achieved.

[Production method explanation]
Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to FIGS. 1 to 17 and the configuration of the semiconductor device will be clarified.

  First, a semiconductor substrate 1 is prepared in which a plurality of wirings (M1 to M4) are formed above semiconductor elements (n-channel MISFET Qn and p-channel MISFET Qp) as shown in FIG.

  There are no limitations on the method for forming the semiconductor elements (n-channel type MISFETQn and p-channel type MISFETQp) and the plurality of wirings (M1 to M4). For example, these can be formed by the following steps.

[Qn, Qp formation process]
For example, a trench is formed by etching a semiconductor substrate 1 made of p-type single crystal silicon, and an element isolation region 2 is formed by embedding, for example, a silicon oxide film as an insulating film in the trench. The element isolation region 2 defines an active region where the n-channel MISFET Qn is formed and an active region where the p-channel MISFET Qp is formed.

  Next, after ion-implanting p-type impurities into the active region of the semiconductor substrate 1 where the n-channel MISFET Qn is to be formed, the impurities are diffused by heat treatment to form a p-type well. In addition, an n-type well is formed by ion-implanting an n-type impurity into the active region of the semiconductor substrate 1 where the p-channel MISFET Qp is formed, and then diffusing the impurity by heat treatment. Next, for example, the surface of the semiconductor substrate 1 (p-type well and n-type well) is thermally oxidized to form a gate insulating film.

  Next, a polycrystalline silicon film doped with impurities is deposited on the gate insulating film, for example, as a conductive film, and a silicon nitride film, for example, is deposited thereon as an insulating film. Next, after etching the silicon nitride film, the polycrystalline silicon film is etched using the silicon nitride film as a mask to form the gate electrode G.

Next, n ⁻ type semiconductor regions are formed by ion-implanting n-type impurities into the p-type wells on both sides of the gate electrode G, and p-type impurities are ion-implanted into the n-type wells on both sides of the gate electrode G. ^- -type semiconductor regions.

  Next, after depositing, for example, a silicon nitride film as an insulating film on the entire surface of the semiconductor substrate 1, side wall spacers are formed on the side walls of the gate electrode G by anisotropic etching.

Next, an n ⁺ -type semiconductor region having an impurity concentration higher than that of the n ⁻ -type semiconductor region is formed by ion-implanting n-type impurities into the p-type well using the gate electrode G and the side wall spacer as a mask. A p ⁺ type semiconductor region having an impurity concentration higher than that of the p ⁻ type semiconductor region is formed by ion implantation of p type impurities into the n type well using the wall spacer as a mask.

Through the above steps, the source of the LDD (Lightly Doped Drain) structure composed of the n ⁻ type semiconductor region and the n ⁺ type semiconductor region, the n channel MISFET Qn having the drain region 3n, and the p ⁻ type semiconductor region and the p ⁺ type semiconductor A p-channel MISFET Qp having a source / drain region 3p having an LDD structure composed of regions is formed.

[M1-M3 formation process]
Next, a multilayer wiring is formed above the n-channel MISFET Qn and the p-channel MISFET Qp. Hereinafter, the formation process of the first layer wiring M1 to the third layer wiring M3 in the multilayer wiring will be described.

  First, as shown in FIG. 1, for example, a silicon oxide film is deposited as an insulating film on the n-channel MISFET Qn and the p-channel MISFET Qp by a CVD (Chemical Vapor deposition) method. Thereafter, if necessary, the surface of the silicon oxide film is polished by a chemical mechanical polishing (CMP) method to planarize the surface, thereby forming an interlayer insulating film TH1a.

  Next, by etching the interlayer insulating film TH1a, contact holes (connection holes) are formed on the source and drain regions 3n and 3p, respectively. Next, a tungsten (W) film, for example, is deposited as a conductive film on the interlayer insulating film TH1a including the inside of the contact hole by the CVD method, and this tungsten film is polished by the CMP method until the interlayer insulating film TH1a is exposed. Thus, a conductive film is embedded in the contact hole. By this step, a plug (contact plug) P1 is formed. Note that a barrier film made of a single-layer film such as a titanium nitride (TiN) film or a titanium (Ti) film or a laminated film thereof may be provided below the tungsten film.

  Next, on the interlayer insulating film TH1a and the plug P1, for example, a silicon nitride film and a silicon oxide film are sequentially deposited as an insulating film by a CVD method to form a wiring trench insulating film TH1b composed of these laminated films. Note that the silicon nitride film serves as an etching stopper film. The interlayer insulating film TH1a and the wiring trench insulating film TH1b may be collectively referred to as an interlayer insulating film TH1.

  Next, the wiring groove is formed by etching the wiring groove insulating film TH1b. Next, a barrier film (not shown) made of, for example, titanium nitride is deposited by sputtering on the wiring groove insulating film TH1b including the inside of the wiring groove, and further, a seed film for electroplating (see FIG. For example, a copper thin film is formed by sputtering or CVD. Next, on the seed film, for example, a copper film is formed as a conductive film by an electrolytic plating method.

  Next, after heat-treating the copper film, the first-layer wiring M1 is formed by removing the copper film and the barrier film other than the wiring trench by the CMP method. Thus, a method of embedding a conductive film in the wiring trench is called a damascene method, and a method of forming the plug and the wiring in separate processes is called a single damascene method. Further, a method of forming plugs and wirings at a time by simultaneously embedding a conductive film in the contact holes and wiring trenches as in second layer wiring M2 to fourth layer wiring M4 described later is a dual damascene method. To tell.

  Next, the second layer wiring M2 and the third layer wiring M3 are formed using a dual damascene method. First, an interlayer insulating film TH2 is formed on the first layer wiring M1 and the wiring trench insulating film TH1b by sequentially depositing, for example, a silicon nitride film, a silicon oxide film, a silicon nitride film, and a silicon oxide film as insulating films by the CVD method. Form. Of these films, the lower silicon nitride film has a function of preventing diffusion of copper constituting the first layer wiring M1. The lower silicon nitride film is used as an etching stopper when forming a contact hole described later, and the upper silicon nitride film is used as an etching stopper when forming a wiring groove described later.

  Next, in the interlayer insulating film TH2, a silicon oxide film and a silicon nitride film, which are the two insulating films from the top, are etched to form a wiring groove. Next, a first photoresist film (not shown) is deposited on the interlayer insulating film TH2 including the inside of the wiring trench, and the wiring trench is filled with the first photoresist film by etching back. Further, a second photoresist film (not shown) having an opening for forming a plug P2 to be described later is formed on the first photoresist film, and the first photoresist film and the lower layer are formed using the second photoresist film as a mask. The two-layer silicon oxide film and silicon nitride film are etched to form contact holes.

  Here, the contact hole is formed after the wiring groove is formed. However, after the contact hole is formed by etching the interlayer insulating film TH2 (four-layer film) in the formation region of the plug P2, the contact hole is formed from the top. The wiring trench may be formed by etching the silicon oxide film and the silicon nitride film which are the insulating films of the layers.

  Next, a barrier film (not shown) made of, for example, titanium nitride is deposited by sputtering on the interlayer insulating film TH2 including the inside of the contact hole and the wiring trench, and further, a seed film for electroplating is formed on the barrier film. For example, a copper thin film is formed by sputtering or CVD (not shown). Next, on the seed film, for example, a copper film is formed as a conductive film by an electrolytic plating method.

  Next, after heat-treating the copper film, the plug P2 and the second-layer wiring M2 are formed by removing the copper film and the barrier film other than the wiring trench by the CMP method.

  Next, similarly to the interlayer insulating film TH2, the plug P2, and the second layer wiring M2, the interlayer insulating film TH3, the plug P3, and the third layer wiring M3 are formed. Note that a silicon carbonitride film (SiCN film) may be used instead of the silicon nitride film in the interlayer insulating films TH1 to TH3 (the same applies to TH4 described later). The silicon carbonitride film is suitable because it has a high copper (Cu) diffusion barrier property.

[M4, M5, Pd formation process]
Next, after forming the fourth layer wiring M4, a fifth layer wiring (aluminum wiring) M5 which is the uppermost layer wiring is formed above the fourth layer wiring M4, and a protective film (12, 13, 16) is formed on the upper portion thereof. Then, a part thereof is exposed to form a pad region (Al pad, pad, bonding pad, opening) Pd. The process will be described in detail with reference to FIGS. In addition, the cross-sectional part of FIGS. 2-9 respond | corresponds to the AA part of FIG. 1, for example.

  The fourth layer wiring M4 is formed as follows, for example. First, as shown in FIG. 2, a SiCN film TH4a, for example, is formed as an insulating film on the third layer wiring (M3) and the interlayer insulating film (TH3), and then, for example, TEOS (Tetra Ethyl Ortho Silicate) is used as the insulating film. The film TH4b is formed by a plasma CVD method. Next, for example, a SiCN film TH4c is formed as an insulating film on the TEOS film TH4b by a CVD method. Further, for example, a TEOS film TH4d is formed as an insulating film on the SiCN film TH4c by a plasma CVD method. Next, for example, a SiCN film TH4e is formed as an insulating film on the TEOS film TH4d by a CVD method. Thereby, an interlayer insulating film TH4 including five insulating films (TH4a to TH4e) is formed. Of these films, the lower SiCN film TH4a has a function of preventing diffusion of copper constituting the third-layer wiring M3. The SiCN films TH4a and TH4c are used as etching stoppers when forming contact holes and wiring grooves, which will be described later.

  Next, in the interlayer insulating film TH4, the SiCN film TH4e and the TEOS film TH4d, which are the two insulating films from the top, are etched to form a wiring trench. Next, a first photoresist film (not shown) is deposited on the interlayer insulating film TH4 including the inside of the wiring trench, and the wiring trench is filled with the first photoresist film by etching back. Further, a second photoresist film (not shown) having an opening for forming a plug P4 to be described later is formed on the first photoresist film, and the first photoresist film and the lower layer are formed using the second photoresist film as a mask. The contact holes are formed by etching the three layers of TEOS film TH4b and SiCN films TH4a and TH4c.

  In FIG. 2, the connection between one fourth layer wiring M4 and the third layer wiring (M3, not shown in FIG. 2) is connected by two plugs P4. You may connect with the plug P4. However, connection failure can be reduced by providing a plurality of plugs in the contact region.

  Further, here, the contact hole is formed after the wiring groove is formed. However, after the contact hole is formed by etching the interlayer insulating film TH4 (four-layer films TH4a to TH4e) in the formation region of the plug P4, The wiring trench may be formed by etching the two layers of SiCN film TH4e and TEOS film TH4d from above.

  Next, a barrier film (not shown) made of, for example, titanium nitride is deposited by sputtering on the interlayer insulating film TH4 including the inside of the contact hole and the wiring groove, and further, a seed film for electroplating is formed on the barrier film. For example, a copper thin film is formed by sputtering or CVD (not shown). Next, a copper film, for example, is formed as a conductive film on the seed film by an electrolytic plating method or the like.

  Next, after heat-treating the copper film, the plug P4 and the fourth-layer wiring M4 are formed by removing the copper film and the barrier film other than the wiring trench by the CMP method.

  The interlayer insulating film TH4 may have the same configuration as the interlayer insulating film TH2, and the fourth layer wiring M4 may be formed in the same manner as the second layer wiring M2. Further, the interlayer insulating film TH2 may have the same configuration as the interlayer insulating film TH4, and the second layer wiring M2 may be formed in the same manner as the fourth layer wiring M4. Further, the interlayer insulating film TH3 may have the same configuration as the interlayer insulating film TH4, and the third layer wiring M3 may be formed in the same manner as the fourth layer wiring M4.

  Next, an interlayer insulating film TH5 is formed on the fourth layer wiring M4 by sequentially depositing, for example, a SiCN (silicon carbonitride) film TH5a and a silicon oxide film TH5b as an insulating film by a CVD method. This SiCN film TH5a has excellent barrier properties and insulation against copper diffusion, and is suitable for use on the fourth layer wiring (Cu damascene wiring) M4.

  Next, the interlayer insulating film TH5 is etched to form a contact hole on the fourth layer wiring M4. Next, for example, a titanium nitride (TiN) film is formed as the barrier film 10a on the interlayer insulating film TH5 including the inside of the contact hole by a sputtering method.

  Next, an aluminum film 10b is formed on the barrier film 10a by a sputtering method. Next, a titanium nitride (TiN) film 10c is formed as an antireflection film on the aluminum film 10b by a sputtering method. For example, the aluminum film (10b) and the titanium nitride film (10c) can be continuously formed while changing the target in the same sputtering apparatus. Thus, by performing continuous film formation, it is possible to form good laminated films (10b and 10c) with few foreign substances and oxides at the film interface. The aluminum film 10b referred to here may contain other metals. For example, an alloy containing about several percent of Cu may be used.

  Next, a photoresist film (not shown) is applied on top of the laminated film of the barrier film 10a, the aluminum film 10b, and the titanium nitride film (antireflection film) 10c, and is exposed and developed (photolithography) to form the fifth layer wiring M5. The photoresist film is left in the formation region. Thus, by forming the antireflection film (titanium nitride film 10c) on the aluminum film 10b, the pattern accuracy can be improved. That is, in the photoresist film, irradiation light is reflected from the aluminum film 10b at the time of exposure, and resolution failure due to interference between the irradiation light and the reflected light can be prevented.

  Next, the multilayer film is etched (patterned) using the photoresist film as a mask to form a fifth layer wiring (aluminum wiring) M5 and a plug P5. The plug P5 is made of a barrier film 10a and an aluminum film 10b embedded in the contact hole, and the fifth layer wiring M5 is made of a barrier film 10a and an aluminum film 10b on the interlayer insulating film TH5. A titanium nitride film (antireflection film) 10c is disposed on the fifth layer wiring M5. Since the titanium nitride film 10c has conductivity, it may be handled as a part of the fifth layer wiring (aluminum wiring) M5.

  Next, as illustrated in FIG. 3, for example, a stacked film of a silicon oxide film 12 and a silicon nitride film 13 is formed as a first protective film (first insulating film) on the fifth layer wiring M <b> 5. Each of these films can be formed by a plasma CVD method.

  Next, as shown in FIG. 4, a photoresist film R is applied on the silicon nitride film 13. Next, as shown in FIG. 5, the photoresist film R in the opening OA is removed by exposing and developing the photoresist film R. The opening OA corresponds to a pad area Pd described later. By this step, the surface of the first protective film (the surface of the silicon nitride film 13) is exposed.

  Next, as shown in FIG. 6, the first protective film (laminated film of the silicon oxide film 12 and the silicon nitride film 13) is etched using the photoresist film R as a mask, so that an opening (OA) is formed in the first protective film. Form. Further, subsequently, the titanium nitride film (antireflection film) 10c is etched. As a result, the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) is exposed from the opening OA. This exposed area becomes the pad area Pd.

  Here, although only one pad region Pd is shown in FIG. 6, a plurality of pad regions Pd are formed inside the semiconductor device (semiconductor chip) (see FIG. 14), and the plurality of pad regions Pd. Form at once.

  Therefore, over-etching is preferably performed in order to prevent non-opening of the pad region Pd. That is, even after the titanium nitride film (antireflection film) 10c is etched and the surface of the aluminum film 10b is exposed, the etching is continued and the surface of the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) in the pad region Pd. Retreat. In other words, a recess corresponding to the pad region Pd is formed in the aluminum film 10b (fifth layer wiring (aluminum wiring) M5). Here, the over-etching amount (retraction amount, recess depth) is D.

  Thus, by performing over-etching, non-opening of the pad region Pd, in other words, non-exposure of the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) in the pad region Pd can be prevented.

  In particular, when the first protective film (laminated film of the silicon oxide film 12 and the silicon nitride film 13) having a relatively large thickness and the titanium nitride film (antireflection film) 10c are simultaneously etched, the overetching is performed. This facilitates the controllability of etching, which is preferable.

  Next, a cleaning process is performed on the entire semiconductor substrate (1) to remove the remaining particles and the like, and the pad region Pd is cleaned. As this cleaning liquid, for example, a cleaning liquid made of ammonium fluoride, formaldehyde and water is used.

  Next, as shown in FIG. 7, the photoresist film R is removed by ashing (ashing treatment) or the like. The ashing processing time is about 70 seconds, for example. This ashing process also serves to improve the corrosion resistance of the aluminum film 10b (pad region Pd).

Next, a plasma treatment using a nitrogen-based plasma gas is performed on the pad region Pd. That is, the pad region Pd is exposed to an atmosphere in which nitrogen or a nitrogen compound gas (nitriding gas) is turned into plasma. As the nitriding plasma gas, a NH ₃ (ammonia) plasma gas is used. By exposing the pad region Pd to the NH ₃ plasma gas (NH ₃ plasma treatment), the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) exposed from the pad region Pd is nitrided, and the aluminum nitride layer (surface Treatment layer, plasma treatment layer, hard layer) 15 is formed.

  The aluminum nitride layer 15 is a layer (film) formed by plasma treatment using a nitrogen-based plasma gas, and is a layer (film) thicker than an unintentionally formed natural aluminum nitride layer.

  For example, when a nitrogen compound film (for example, an antireflection film containing a nitrogen compound such as the titanium nitride film 10c or the SiON film 11 described in Embodiment 2) is formed on the aluminum film 10b. Aluminum and the nitrogen compound react to form aluminum nitride. A layer (film) formed unintentionally in this way is referred to herein as a natural aluminum nitride layer (film). This natural aluminum nitride layer can be formed at the boundary between the aluminum film 10b and the antireflection film (titanium nitride film 10c) in the above process. The aforementioned aluminum nitride layer 15 is formed thicker than this natural aluminum nitride layer.

  Further, the film thickness (average film thickness) of the aluminum nitride layer 15 described above can protect the pad region Pd, and can be broken and electrically connected by the stress of the probe needle described later and the pressure during wire bonding. A film thickness of the order is preferable, and a preferable film thickness range is 10 nm or more and 30 nm or less.

[Engraving and probe test process]
Thereafter, the semiconductor substrate (wafer) 1 is numbered (engraved) as necessary. The semiconductor element (MISFET), the wiring, the pad region Pd, and the like formed in the above process are formed in a plurality of chip regions partitioned in a rectangular shape on a substantially circular wafer. Further, in the semiconductor device manufacturing process, a plurality of wafers are often processed continuously. Therefore, wafer information such as a lot number and a wafer number is written in a predetermined area of the wafer for each wafer. For example, a plurality of dot-shaped recesses in the form of numbers (symbols) are formed at the edge of the wafer (area not used as a chip) by laser or the like (laser naming).

  This numbering process may be performed at any stage in the manufacturing process of the semiconductor device. However, if it is formed in a lower layer region, a number of films are stacked thereon, and the number ( (Symbol) becomes difficult to recognize. Further, the subsequent film forming process is only a second protective film (16) to be described later, and, as will be described later, the second protective film (16) on the number simultaneously with the removing process of the second protective film (16) in the pad region Pd. The protective film (16) can also be removed. Therefore, it is preferable to perform numbering at this stage.

  Next, the entire semiconductor substrate (1) is subjected to a cleaning process to remove particles generated by laser naming, photoresist film residues, and the like. As this cleaning liquid, for example, a cleaning liquid made of ammonium fluoride, formaldehyde and water is used. Next, particles remaining after the cleaning treatment are removed by a scrub jet using pure.

  Next, ashing (ashing treatment) is performed on the pad region Pd to improve the corrosion resistance of the aluminum film 10b (pad region Pd) and improve the wettability of the second protective film (16) described later. Thereby, the adhesion between the aluminum film 10b (pad region Pd) and the second protective film (16) is improved, and the resolution is good in the exposure / development process of the second protective film (photosensitive polyimide film 16). Become. The ashing processing time is about 120 seconds, for example.

  Next, the presence or absence of a residue of the titanium nitride film (antireflection film) 10c on the pad region Pd (aluminum film 10b) is examined by reflection inspection.

  Next, as shown in FIG. 8, for example, a photosensitive polyimide film (PIQ film: Polyimide-isoindoloquinazolinedion film) 16 is formed as a second protective film on the first protective film (on the silicon nitride film 13) including the pad region Pd. Apply. Next, as shown in FIG. 9, the photosensitive polyimide film 16 in the opening OA is removed by exposing and developing the photosensitive polyimide film 16. By this step, the aluminum film 10b (pad region Pd) is exposed again from the opening OA. As the developer for the photosensitive polyimide film 16, for example, a developer composed of dimethyl sulfoxide, gamma-butyrolactone and water is used. In FIG. 9, the opening OA of the first protective film (silicon oxide film 12, silicon nitride film 13) and the opening OA of the second protective film (photosensitive polyimide film 16) have the same size. The opening of the second protective film may be larger than the opening OA of the first protective film.

  Next, the photosensitive polyimide film (second protective film) 16 is cured by performing heat treatment (curing treatment). Next, ashing (ashing treatment) is performed on the photosensitive polyimide film 16 to remove polyimide residues on the pad region Pd, foreign matters on the surface of the photosensitive polyimide film, and the like.

  Next, an operation test of the semiconductor device is performed using the pad region Pd. In this way, determining whether the semiconductor device (integrated circuit) is good or bad in the pre-process (before dicing, wafer state) of the manufacturing process of the semiconductor device is called “wafer test”.

  As this wafer test, for example, there is a “probe test” performed using a probe card provided with probe needles (N) corresponding to a plurality of pad regions Pd (see FIG. 14). By applying an electrical signal to the pad region Pd through the probe needle (N) and detecting a signal obtained from the pad region Pd, the electrical characteristics of the semiconductor device can be confirmed. From this test result, the quality of the semiconductor device (integrated circuit) can be determined.

  There are no restrictions on the test content, but examples of the test type include a DC test, an AC test, and a function test. By the DC test, for example, confirmation of the presence or absence of a disconnection or a short circuit, confirmation of the output voltage (current), and the like can be performed. Further, for example, the waveform of the output signal can be confirmed by the AC test. In addition, it is possible to check whether data can be written and the data holding time by a function test.

  Here, in the present embodiment, the pad region Pd is subjected to plasma treatment using a nitrogen-based plasma gas, and an aluminum nitride layer (surface treatment layer, plasma treatment layer, hard layer) 15 is formed on the surface thereof. Therefore, the contact resistance between the pad region Pd and the probe needle (N) can be reduced. As a result, probe test characteristics (inspection characteristics) can be improved.

  That is, the formation of the aluminum nitride layer 15 which is a processing film firmly bonded to the pad region Pd by plasma prevents the natural oxide film from being formed in the pad region Pd during the process up to the probe test. can do.

  Further, as shown in FIG. 10, when the probe needle N abuts, the aluminum nitride layer 15 on the pad region Pd is cracked, and the pad region Pd (the aluminum film 10b, the fifth layer wiring (aluminum) is cut through the crack. Wiring) M5) and probe needle (N) can be brought into contact with low resistance. FIG. 10 is a diagram for explaining the effect of the semiconductor device according to the present embodiment, and is a cross-sectional view of the main part showing the contact state of the probe needle with the pad region of the semiconductor device according to the present embodiment. FIG. 11 is a cross-sectional view of the main part showing the contact state of the probe needle with respect to the pad region of the semiconductor device of the comparative example, for explaining the effect of the semiconductor device of the present embodiment.

  On the other hand, as shown in FIG. 11, in the case of the comparative example in which the plasma treatment using the nitrogen-based plasma gas is not performed, a natural oxide film 25 is formed on the surface of the pad region Pd. The natural oxide film 25 is soft and not strongly bonded. Furthermore, since the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) also has a relatively soft property, the lower aluminum film 10b is also recessed following the natural oxide film 25. As a result, the aluminum film 10b and the probe needle N come into contact via the natural oxide film 25, and the contact resistance increases. It has been found by the present inventors that such a phenomenon is difficult to improve even if the probe pressure (the amount of overdrive described later) is increased.

  Therefore, in the case of the comparative example shown in FIG. 11, a desired electrical signal cannot be applied to the pad region Pd, and a signal obtained from the pad region Pd cannot be accurately detected. Therefore, it cannot be determined whether the semiconductor device (integrated circuit) is defective or whether the pad region Pd and the probe needle N have a high resistance, and an accurate test (inspection) cannot be performed. .

FIG. 12 shows the resistance value between the pad region Pd and the probe needle subjected to the NH ₃ plasma treatment of the present embodiment, and the resistance value between the pad region Pd and the probe needle in the comparative example. The horizontal axis of the graph represents the number of contacts (times), and the vertical axis represents the resistance value (PAD resistance value: Ω (ohm)).

  As shown in FIG. 12, in the case of the present embodiment, the resistance value (PAD resistance value) between the pad region Pd and the probe needle is lower than in the comparative example (Ref). Here, the probe needle is overdriven so that, for example, the amount of pushing from the surface of the pad region Pd (the amount of biting of the needle tip, the amount of overdrive) is about 65 μm.

  FIG. 13 is a graph showing the resistance value of the pad region Pd in the present embodiment and the resistance value of the pad region Pd in the comparative example. Here, the resistance value (Ω (ohm)) is plotted on the horizontal axis. The vertical axis represents the percentage (%) of the number of contacts, that is, the ratio of the number of contacts to be measured to the total number of contacts. The number of contacts to be measured indicates the number of contacts, that is, the cumulative number of contact of the probe needle.

  In FIG. 13, graphs (a) and (b) show the case of the comparative example (reference, Ref), and graphs (c) and (d) show the case of the present embodiment. The reference for the processing of the graph (c) is the graph (a), and the reference for the processing of the graph (d) is the graph (b). As shown in FIG. 13, both the graphs (c) and (d) have lower resistance values than the reference ((a) (b)).

  As described above, in this embodiment, it was confirmed that the contact resistance between the pad region Pd and the probe needle (N) can be reduced. As a result, it is possible to improve the inspection accuracy of the probe test. In addition, the inspection time can be shortened. Therefore, it is possible to improve the manufacturing yield of the semiconductor device and the throughput of manufacturing the semiconductor device. In addition, the reliability of the semiconductor device can be increased.

In place of the nitrogen plasma treatment, an oxidation (oxygen) plasma treatment may be performed. For example, even if an aluminum oxide layer, which is a treatment film firmly bonded to the pad region Pd by plasma, is formed by oxygen (O ₂ ) plasma treatment, a similar effect is assumed.

  However, various etching processes (including a development process) and cleaning processes may occur between the plasma processing process and the probe test process. In these steps, a chemical that dissolves the oxide film is often used. In addition, since many particles, film residues, and the like are often oxidized films, a chemical that dissolves the oxide film (oxide film removing agent) is often used preferably.

  For example, also in the above manufacturing process, between the plasma processing process and the probe test process, <1> a cleaning process for removing particles and the like generated by laser naming, and <2> development of the photosensitive polyimide film 16 There are processes. Therefore, through these steps, the pad region Pd is exposed to a cleaning solution or a developing solution. As described above, the cleaning solution contains, for example, ammonium fluoride and formaldehyde, and the developer contains, for example, dimethyl sulfoxide and gamma-butyrolactone. These agents can dissolve the aluminum oxide film.

  Therefore, when the aluminum oxide layer is formed in the pad region Pd by the oxidation plasma treatment, the aluminum oxide layer is dissolved by the etching solution (including the developing solution) and the cleaning solution. As a result, a natural oxide film is formed before the probe test process, resulting in a configuration similar to the state shown in FIG.

  On the other hand, if the aluminum nitride layer 15 is formed as in the present embodiment, it is not melted in the etching process (including the developing process) and the cleaning process, and the formation of a natural oxide film is prevented. It also becomes a protective film.

  Further, in the probe test process, as described above, by making use of the hardness of the aluminum nitride layer 15 and inserting a probe needle, it is easy to make contact with the lower aluminum film 10b (pad region Pd). Can be planned.

[Mounting process]
After the probe test process, the semiconductor substrate (wafer) 1 is cut (diced) and separated into a plurality of semiconductor chips CHP (divided into individual pieces). Note that the semiconductor substrate 1 may be thinned by performing back surface grinding of the semiconductor substrate (wafer) 1 before dicing. FIG. 14 shows an example of the semiconductor chip after dicing. As shown in the drawing, in the semiconductor chip CHP cut into a substantially rectangular shape, a plurality of pad regions Pd are arranged around the element formation region EA.

  Next, as shown in FIG. 15, the semiconductor chip CHP is mounted (adhered) on the wiring board WB (die bonding). Terminals (external terminals) TE are formed on the chip mounting surface side of the wiring board WB. Next, the pad region Pd formed on the semiconductor chip CHP and the terminal TE formed on the wiring board WB are connected by a wire (conductive member) W made of a gold wire or the like (wire bonding). Specifically, as shown in FIG. 16, the wire W is connected to the pad region Pd exposed from the opening (OA) of the first protective film (12, 13) and the second protective film (16). . At this time, since the aluminum nitride layer 15 on the surface of the pad region Pd is a thin film, the aluminum nitride layer 15 is easily crushed (breaks), which hinders electrical conduction between the lower aluminum film 10b (fifth layer wiring (aluminum wiring) M5) and the wire W. There is no. In other words, the pad region Pd (the aluminum film 10b, the fifth layer wiring (aluminum wiring) M5) and the wire W can be electrically connected to each other through a plurality of cracks (not shown) in the aluminum nitride layer 15.

  Thereafter, as shown in FIG. 17, the semiconductor chip CHP and the wires W are sealed with a resin MR so as to cover them. This resin MR is provided in order to protect the semiconductor chip CHP from external impact and impurity intrusion. Subsequently, solder balls SB serving as external connection terminals are formed on the back surface (surface opposite to the chip mounting surface) of the wiring board WB.

  Through the above steps, a semiconductor device can be manufactured. In the present embodiment, wire bonding has been described as an example, but face-down bonding may be performed.

  For example, after performing the probe test, a bump electrode may be formed on the pad region Pd, mounted on the wiring board with the bump electrode formation side (face side) facing down, and sealed with resin.

  In the above process, the first to fourth layer wirings are damascene wirings. However, the present invention is not limited to this. For example, each wiring may be formed by patterning a conductive film (metal film).

  In the above process, the MISFET is exemplified as the semiconductor element. However, the present invention is not limited to this, and other elements such as a resistance element and a memory can be formed.

(Embodiment 2)
In the first embodiment, the NH ₃ plasma gas is used when the pad region Pd is subjected to the plasma treatment using the nitrogen-based plasma gas. However, other nitrogen-based plasma gases may be used. Good. 18 to 20 are diagrams for explaining the effect of the semiconductor device of the present embodiment.

(Application 1)
As application example 1, a plasma gas of N ₂ (nitrogen) may be used. Note that, except for the plasma gas type, since it is the same as that of the first embodiment, description of the configuration and manufacturing process of the semiconductor device is omitted.

FIG. 18 shows the resistance value between the pad region Pd subjected to N ₂ plasma treatment and the probe needle, which is an application example 1 of the present embodiment, and the pad region Pd and the probe needle in the comparative example (Ref). Indicates the resistance value. The horizontal axis of the graph represents the number of contacts (times), and the vertical axis represents the resistance value (PAD resistance value: Ω (ohm)).

  As shown in FIG. 18, also in this application example 1, the PAD resistance value is lower than that in the comparative example. Further, the probe needle (N) is overdriven so that, for example, the pushing amount from the surface of the pad region Pd is about 65 μm.

Thus, even when the N ₂ plasma treatment was performed, it was confirmed that the contact resistance between the pad region Pd and the probe needle (N) was lowered.

(Application example 2)
As application example 2, a plasma gas of N ₂ O (nitrous oxide) may be used. Note that, except for the plasma gas type, since it is the same as that of the first embodiment, description of the configuration and manufacturing process of the semiconductor device is omitted.

FIG. 19 shows a resistance value between the pad region Pd subjected to the N ₂ O plasma treatment and the probe needle, which is an application example 2 of the present embodiment, and the pad region Pd and the probe needle in the comparative example (Ref). The resistance value is shown. The horizontal axis of the graph represents the number of contacts (times), and the vertical axis represents the resistance value (PAD resistance value: Ω (ohm)).

  As shown in FIG. 19, also in this application example 2, the PAD resistance value is lower than that in the comparative example. Further, the probe needle (N) is overdriven so that, for example, the pushing amount from the surface of the pad region Pd is about 65 μm.

Thus, even when the N ₂ O plasma treatment was performed, it was confirmed that the contact resistance between the pad region Pd and the probe needle (N) was lowered.

(Application 3)
As Application Example 3, a gas obtained by converting a mixed gas of N ₂ (nitrogen) and O ₂ (oxygen) into plasma may be used. Note that, except for the plasma gas type, since it is the same as that of the first embodiment, description of the configuration and manufacturing process of the semiconductor device is omitted.

FIG. 20 is a graph showing the resistance value of the pad region Pd subjected to the mixed plasma treatment of N ₂ and O ₂ as Application Example 3 of the present embodiment. The horizontal axis represents the resistance value (Ω (ohm)), and the vertical axis represents the percentage (%) of the number of contacts. The content of O ₂ is, for example, about 50 Vol%.

A graph (e) is a graph of a mixed plasma treatment of N ₂ and O ₂ , and a graph (f) is a graph of the N ₂ plasma treatment described in Application Example 1.

  As shown in FIG. 20, also in this application example 3, the PAD resistance value is lowered. Note that the probe needle (N) is overdriven so that, for example, the push-in amount from the surface of the pad region Pd is about 65 μm.

Thus, it was confirmed that the contact resistance between the pad region Pd and the probe needle (N) can be reduced even when the mixed plasma treatment of N ₂ and O ₂ is performed.

As described in detail above, as a plasma treatment using a nitrogen-based plasma gas, a gas obtained by converting any one of N ₂ and N ₂ O into plasma in addition to NH ₃ can be used. N ₂ may contain O ₂ .

  In the first embodiment and the second embodiment (application examples 1 to 3), the overdrive amount is set to 65 μm, but the present invention is not limited to this value. However, in order to reduce the contact resistance, it is preferable to perform overdrive, and it is preferable to set the thickness corresponding to the suitable thickness of the aluminum nitride layer described above. The range of the overdrive amount is preferably 50 μm or more, more preferably 60 μm or more and 70 μm or less. By this overdrive, a probe trace (a trace in contact with the probe needle) is formed in the pad region Pd.

(Embodiment 3)
In the first embodiment, the titanium nitride film 10c is used as the antireflection film. However, in the present embodiment, the SiON (silicon oxynitride) film 11 is used as the antireflection film. The titanium nitride film 10c is a conductive film, while the SiON film 11 is an insulating film. 21 to 28 are main-portion cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment.

  Since the configuration other than the antireflection film (11) is the same as that of the first embodiment, a detailed description of the configuration of the semiconductor device is omitted (see FIGS. 1, 16 and the like).

  The process up to the formation of the third layer wiring M3 is the same as that of the first embodiment, and thus detailed description thereof is omitted (see FIG. 1 and the column of [M1 to M3 formation process]).

  With reference to FIGS. 21 to 28, processes after the formation process of the fourth layer wiring M <b> 4 will be described.

  As shown in FIG. 21, the fourth layer wiring M4 and the plug P4 are formed in the interlayer insulating film TH4 in the same manner as in the first embodiment. The interlayer insulating film TH4 includes five insulating films in which a SiCN film TH4a, a TEOS film TH4b, a SiCN film TH4c, a TEOS film TH4d, and a SiCN film TH4e are sequentially stacked from below. In FIG. 21, the connection between one fourth layer wiring M4 and the third layer wiring (M3, not shown in FIG. 21) is connected by two plugs P4. You may connect with the plug P4. However, connection failure can be reduced by providing a plurality of plugs in the contact region.

  Next, an interlayer insulating film TH5 is formed on the fourth layer wiring M4 by sequentially depositing, for example, a SiCN (silicon carbonitride) film TH5a and a silicon oxide film TH5b as an insulating film by a CVD method. This SiCN film TH5a has excellent barrier properties and insulation against copper diffusion, and is suitable for use on the fourth layer wiring (Cu damascene wiring) M4.

  Next, the interlayer insulating film TH5 is etched to form a contact hole on the fourth layer wiring M4. Next, for example, a titanium nitride (TiN) film is formed as the barrier film 10a on the interlayer insulating film TH5 including the inside of the contact hole by a sputtering method.

  Next, an aluminum film 10b is formed on the barrier film 10a by a sputtering method. Next, a SiON (silicon oxynitride) film 11 is formed as an antireflection film on the aluminum film 10b by a CVD method. In addition, the aluminum film said here may contain another metal. For example, you may contain about several percent of Cu.

  Next, a photoresist film (not shown) is applied on top of the laminated film of the barrier film 10a, the aluminum film 10b, and the SiON film (antireflection film) 11, and is exposed and developed (photolithography) to form the fifth layer wiring M5. The photoresist film is left in the region. Thus, by forming the antireflection film (SiON film 11) on the aluminum film 10b, the pattern accuracy can be improved. That is, in the photoresist film, irradiation light is reflected from the aluminum film 10b at the time of exposure, and resolution failure due to interference between the irradiation light and the reflected light can be prevented.

  Next, the multilayer film is etched (patterned) using the photoresist film as a mask to form a fifth layer wiring (aluminum wiring) M5 and a plug P5. The plug P5 is made of a barrier film 10a and an aluminum film 10b embedded in the contact hole, and the fifth layer wiring M5 is made of a barrier film 10a and an aluminum film 10b on the interlayer insulating film TH5. An SiON film (antireflection film) 11 is disposed on the fifth layer wiring M5.

  Next, as illustrated in FIG. 22, for example, a stacked film of a silicon oxide film 12 and a silicon nitride film 13 is formed as a first protective film (first insulating film) on the fifth layer wiring M <b> 5. Each of these films can be formed by a plasma CVD method. The film thickness of the silicon oxide film 12 is about 50 nm, for example, and the film thickness of the silicon nitride film 13 is about 600 nm, for example.

  Next, as shown in FIG. 23, a photoresist film R is applied on the silicon nitride film 13. Next, as shown in FIG. 24, the photoresist film R in the opening OA is removed by exposing and developing the photoresist film R. The opening OA corresponds to a pad area Pd described later. By this step, the surface of the first protective film (the surface of the silicon oxide film 12) is exposed.

  Next, as shown in FIG. 25, by etching the first protective film (laminated film of the silicon oxide film 12 and the silicon nitride film 13) using the photoresist film R as a mask, an opening (OA) is formed in the first protective film. Form. Further, subsequently, the SiON film (antireflection film) 11 is etched. As a result, the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) is exposed from the opening OA. This exposed area becomes the pad area Pd.

  Here, although only one pad region Pd is shown in FIG. 25, a plurality of pad regions Pd are formed inside the semiconductor device (semiconductor chip) (see FIG. 14), and the plurality of pad regions Pd. Form at once.

  Therefore, over-etching is preferably performed in order to prevent non-opening of the pad region Pd. That is, even after the SiON film (antireflection film) 11 is etched and the surface of the aluminum film 10b is exposed, the etching is continued and the surface of the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) in the pad region Pd is exposed. Retreat. In other words, a recess corresponding to the pad region Pd is formed in the aluminum film 10b (fifth layer wiring (aluminum wiring) M5). Here, the over-etching amount (retraction amount, recess depth) is D.

  Thus, by performing over-etching, non-opening of the pad region Pd, in other words, non-exposure of the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) in the pad region Pd can be prevented. Unlike the first embodiment, since the etching selectivity between the SiON film (insulating film) 11 and the aluminum film 10b is larger than the etching selectivity between the titanium nitride film 10c and the aluminum film 10b, the overetching amount D is reduced. can do.

  Next, a cleaning process is performed on the entire semiconductor substrate (1) to remove the remaining particles and the like, and the pad region Pd is cleaned. As this cleaning liquid, for example, a cleaning liquid made of ammonium fluoride, formaldehyde and water is used.

  Next, as shown in FIG. 26, the photoresist film R is removed by ashing (ashing treatment) or the like. This ashing process also serves to improve the corrosion resistance of the aluminum film 10b (pad region Pd).

Next, a plasma treatment using a nitrogen-based plasma gas is performed on the pad region Pd. That is, the pad region Pd is exposed to an atmosphere in which nitrogen or a nitrogen compound gas (nitriding gas) is turned into plasma. As the nitriding plasma gas, an NH ₃ plasma gas is used. By exposing the pad region Pd to the NH ₃ plasma gas (NH ₃ plasma treatment), the aluminum film 10b (fifth layer wiring (aluminum wiring) M5) exposed from the pad region Pd is nitrided, and the aluminum nitride layer (surface Treatment layer, plasma treatment layer, hard layer) 15 is formed.

  The aluminum nitride layer 15 is a layer (film) formed by plasma treatment using a nitrogen-based plasma gas, and is a layer (film) thicker than an unintentionally formed natural aluminum nitride layer.

  For example, when a nitrogen compound film (for example, the SiON film 11) is formed on the aluminum film 10b, aluminum and a nitrogen compound react to form aluminum nitride. In particular, when the SiON film 11 is formed by plasma CVD, the reaction between nitrogen and aluminum tends to occur. A layer (film) formed unintentionally in this way is referred to herein as a natural aluminum nitride layer (film). This natural aluminum nitride layer can be formed at the boundary between the aluminum film 10b and the antireflection film (SiON film 11) in the above process. The aforementioned aluminum nitride layer 15 is formed thicker than this natural aluminum nitride layer.

  Further, the film thickness (average film thickness) of the aluminum nitride layer 15 described above can protect the pad region Pd, and can be broken and electrically connected by the stress of the probe needle described later and the pressure during wire bonding. A film thickness of the order is preferable, and a preferable film thickness range is 10 nm or more and 30 nm or less.

[Engraving and probe test process]
Thereafter, the semiconductor substrate (wafer) 1 is numbered (engraved) as necessary. The semiconductor element (MISFET), the wiring, the pad region Pd, and the like formed in the above process are formed in a plurality of chip regions partitioned in a rectangular shape on a substantially circular wafer. Further, in the semiconductor device manufacturing process, a plurality of wafers are often processed continuously. Therefore, wafer information such as a lot number and a wafer number is written in a predetermined area of the wafer for each wafer. For example, a plurality of dot-shaped recesses in the form of numbers (symbols) are formed at the edge of the wafer (area not used as a chip) by laser or the like (laser naming).

  This numbering process may be performed at any stage in the manufacturing process of the semiconductor device. However, if it is formed in a lower layer region, a number of films are stacked thereon, and the number ( Symbol) becomes difficult to recognize. Further, the subsequent film forming process is only a second protective film (16) to be described later, and, as will be described later, the second protective film (16) on the number simultaneously with the removing process of the second protective film (16) in the pad region Pd. The protective film (16) can also be removed. Therefore, it is preferable to perform numbering at this stage.

  Next, the entire semiconductor substrate (1) is subjected to a cleaning process to remove particles generated by laser naming, photoresist film residues, and the like. As this cleaning liquid, for example, a cleaning liquid made of ammonium fluoride, formaldehyde and water is used. Next, particles remaining after the cleaning treatment are removed by a scrub jet using pure.

  Next, ashing (ashing treatment) is performed on the pad region Pd to improve the corrosion resistance of the aluminum film 10b (pad region Pd) and improve the wettability of the second protective film (16) described later. Thereby, the adhesion between the aluminum film 10b (pad region Pd) and the second protective film (16) is improved, and the resolution is good in the exposure / development process of the second protective film (photosensitive polyimide film 16). Become.

  Next, the presence or absence of a residue of the SiON film (antireflection film) 11 on the pad region Pd (aluminum film 10b) is examined by reflection inspection. If the SiON film (antireflection film) 11 remains, etching is performed again.

  Next, as shown in FIG. 27, on the first protective film including the pad region Pd (on the silicon nitride film 13), for example, a photosensitive polyimide film (PIQ film: Polyimide-isoindoloquinazolinedion film) 16 is used as the second protective film. Apply. Next, as shown in FIG. 28, the photosensitive polyimide film 16 in the opening OA is removed by exposing and developing the photosensitive polyimide film 16. By this step, the aluminum film 10b (pad region Pd) is exposed again from the opening OA. As the developer for the photosensitive polyimide film 16, for example, a developer composed of dimethyl sulfoxide, gamma-butyrolactone and water is used. In FIG. 28, the opening OA of the first protective film (silicon oxide film 12, silicon nitride film 13) and the opening OA of the second protective film (photosensitive polyimide film 16) have the same size. The opening of the second protective film may be larger than the opening OA of the first protective film.

  Next, the photosensitive polyimide film (second protective film) 16 is cured by performing heat treatment (curing treatment). Next, ashing (ashing treatment) is performed on the photosensitive polyimide film 16 to remove polyimide residues on the pad region Pd, foreign matters on the surface of the photosensitive polyimide film, and the like.

  Next, an operation test of the semiconductor device is performed using the pad region Pd. In this way, determining whether the semiconductor device (integrated circuit) is good or bad in the pre-process (before dicing, wafer state) of the manufacturing process of the semiconductor device is called “wafer test”.

  As this wafer test, for example, there is a “probe test” performed using a probe card provided with probe needles (N) corresponding to a plurality of pad regions Pd (see FIG. 14). By applying an electrical signal to the pad region Pd through the probe needle (N) and detecting a signal obtained from the pad region Pd, the electrical characteristics of the semiconductor device can be confirmed. From this test result, the quality of the semiconductor device (integrated circuit) can be determined.

  There are no restrictions on the test content, but examples of the test type include a DC test, an AC test, and a function test. By the DC test, for example, confirmation of the presence or absence of a disconnection or a short circuit, confirmation of the output voltage (current), and the like can be performed. Further, for example, the waveform of the output signal can be confirmed by the AC test. In addition, it is possible to check whether data can be written and the data holding time by a function test.

  Here, in the present embodiment, the pad region Pd is subjected to plasma treatment using a nitrogen-based plasma gas, and an aluminum nitride layer (surface treatment layer, plasma treatment layer, hard layer) 15 is formed on the surface thereof. Therefore, the contact resistance between the pad region Pd and the probe needle (N) can be reduced. As a result, probe test characteristics (inspection characteristics) can be improved.

  That is, the formation of the aluminum nitride layer 15 which is a processing film firmly bonded to the pad region Pd by plasma prevents the natural oxide film from being formed in the pad region Pd during the process up to the probe test. can do.

In addition, although it demonstrated also in Embodiment 1, it can also consider performing oxidation type | system | group (oxygen type | system | group) plasma processing instead of the said nitrogen type plasma processing. For example, even if an aluminum oxide layer, which is a treatment film firmly bonded to the pad region Pd by plasma, is formed by oxygen (O ₂ ) plasma treatment, a similar effect is assumed.

  However, various etching processes (including a development process) and cleaning processes may occur between the plasma processing process and the probe test process. In these steps, a chemical that dissolves the oxide film is often used. In addition, since many particles, film residues, and the like are often oxidized films, a chemical that dissolves the oxide film (oxide film removing agent) is often used preferably.

  For example, also in the above manufacturing process, between the plasma processing process and the probe test process, <1> a cleaning process for removing particles and the like generated by laser naming, and <2> development of the photosensitive polyimide film 16 There are processes. Therefore, through these steps, the pad region Pd is exposed to a cleaning solution or a developing solution. As described above, the cleaning solution contains, for example, ammonium fluoride and formaldehyde, and the developer contains, for example, dimethyl sulfoxide and gamma-butyrolactone. These agents can dissolve the aluminum oxide film.

  Therefore, when the aluminum oxide layer is formed in the pad region Pd by the oxidation plasma treatment, the aluminum oxide layer is dissolved by the etching solution (including the developing solution) and the cleaning solution. As a result, a natural oxide film is formed before the probe test process, resulting in an increase in contact resistance with the probe needle (see FIG. 11).

  On the other hand, if the aluminum nitride layer 15 is formed as in the present embodiment, it is not melted in the etching process (including the developing process) and the cleaning process, and the formation of a natural oxide film is prevented. It also becomes a protective film.

  Further, in the probe test step, as described above, by making use of the hardness of the aluminum nitride layer 15 and inserting a probe needle, it is easily brought into contact with the underlying aluminum film (pad region Pd). be able to.

  After the probe test, as in the first embodiment, the semiconductor substrate (wafer) 1 is cut (diced) and separated into individual semiconductor chips CHP, and then the semiconductor chips are formed on the wiring board WB. CHP is mounted (bonded) (die bonding). Furthermore, after this, the pad region Pd and the terminal TE formed on the wiring board WB are connected by a wire W made of a gold wire or the like (wire bonding), and then the semiconductor chip CHP and the wire W are covered. Sealing with resin MR (see FIGS. 14 to 17). Subsequently, solder balls SB serving as external connection terminals are formed on the back surface (surface opposite to the chip mounting surface) of the wiring board WB.

  Through the above steps, a semiconductor device can be manufactured. In the present embodiment, wire bonding has been described as an example, but face-down bonding may be performed.

  For example, after performing the probe test, a bump electrode may be formed on the pad region Pd, mounted on the wiring board with the bump electrode forming side (face side) facing down, and sealed with resin.

  Also in this embodiment, the first to fourth layer wirings (damascene wirings) may be formed by patterning a conductive film (metal film).

  Also in this embodiment, various elements such as other elements such as a resistance element and a memory may be formed as the semiconductor element in addition to the MISFET.

  As mentioned above, although the invention made by the present inventor has been specifically described based on the first to third embodiments, the present invention is not limited to the first to third embodiments and does not depart from the gist thereof. Needless to say, various changes can be made.

  The present invention is suitable for application to a semiconductor device and a method for manufacturing a semiconductor device, in particular, a configuration of a semiconductor device having a pad and a method for manufacturing a semiconductor device having a pad.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3n Source, drain region 3p Source, drain region 10a Barrier film 10b Aluminum film 10c Titanium nitride film 11 SiON film 12 Silicon oxide film 13 Silicon nitride film 15 Aluminum nitride layer 16 Photosensitive polyimide film 25 Natural oxidation Film CHP Semiconductor chip D Overetching amount EA Element formation region G Gate electrode M1 First layer wiring M2 Second layer wiring M3 Third layer wiring M4 Fourth layer wiring M5 Fifth layer wiring MR Resin N Probe needle OA Opening portion P1 Plug P2 plug P3 plug P4 plug P5 plug Pd pad area Qn n-channel MISFET
Qp p-channel MISFET
R photoresist film SB solder ball TE terminal TH1 interlayer insulating film TH1a interlayer insulating film TH1b wiring groove insulating film TH2 interlayer insulating film TH3 interlayer insulating film TH4 interlayer insulating film TH4a SiCN film TH4b TEOS film TH4c SiCN film TH4d TEOS film TH4e SiCN film TH5 interlayer insulating film TH5a SiCN film TH5b silicon oxide film W wire WB wiring board

Claims (25)

(A) forming a conductive film containing aluminum above the substrate;
(B) forming a wiring by patterning the conductive film;
(C) forming a first insulating film on the wiring;
(D) exposing the pad region of the wiring by etching the first insulating film;
(E) performing a plasma treatment using a nitrogen-based plasma gas on the pad region;
(F) After the step (e), a step of bringing a probe needle into contact with the pad region and energizing the pad region;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein an aluminum nitride film is formed in the pad region by the step (e).   The step (f) is a step in which the aluminum nitride film is divided by the probe needle, the probe needle is brought into contact with the wiring in the pad region through a crack in the aluminum nitride film, and energized. A method of manufacturing a semiconductor device according to claim 2. Between the step (a) and the step (b),
(G) having a step of forming an antireflection film on the conductive film;
3. The method of manufacturing a semiconductor device according to claim 2, wherein the step (c) is a step of patterning the conductive film and the antireflection film.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the antireflection film is a titanium nitride film.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the antireflection film is a silicon oxynitride film. In the step (g), a natural aluminum nitride film is formed at the boundary between the conductive film and the antireflection film,
7. The method of manufacturing a semiconductor device according to claim 5, wherein the film thickness of the aluminum nitride film is larger than the film thickness of the natural aluminum nitride film.   The method of manufacturing a semiconductor device according to claim 2, wherein the aluminum nitride film has a thickness of 10 nm to 30 nm.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen-based plasma gas is a plasma of a gas containing nitrogen or a nitrogen compound. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen-based plasma gas includes a gas obtained by converting any one of N ₂ , ammonia (NH ₃ ), and N ₂ O into plasma. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen-based plasma gas includes a gas obtained by converting a mixed gas of N ₂ and O ₂ into plasma. Between the step (e) and the step (f),
3. The method of manufacturing a semiconductor device according to claim 2, further comprising a cleaning step using a cleaning liquid containing an oxide film removing agent.   13. The method for manufacturing a semiconductor device according to claim 12, wherein the cleaning liquid contains ammonium fluoride and formamide. Between the step (e) and the step (f),
3. The semiconductor according to claim 2, further comprising: (i) forming a second insulating film on the first insulating film and the pad region, and removing the second insulating film on the pad region. Device manufacturing method.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the second insulating film is a photosensitive polyimide film, and the removal of the second insulating film is performed by an exposure process and a development process.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the developing step is performed using a developer containing dimethyl sulfoxide and gamma-butyrolactone.   The step (d) is a step of etching the first insulating film and then over-etching the wiring to form a recess in the wiring, and using the recess as a previous pad region. A method for manufacturing a semiconductor device according to claim 1. Between the step (a) and the step (b),
(J) having a step of forming an antireflection film on the conductive film;
The step (b) is a step of patterning the conductive film and the antireflection film,
In the step (d), the first insulating film and the antireflection film are etched, and then the conductive film is over-etched to form a recess in the conductive film. The method of manufacturing a semiconductor device according to claim 1, wherein After the step (f),
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of connecting the pad region and the external terminal via a conductive member. (A) a wiring containing aluminum formed above the semiconductor substrate;
(B) an antireflection film containing a nitrogen compound formed on the wiring;
(C) a first insulating film formed on the antireflection film;
(D) an opening provided in the antireflection film and the first insulating film, the opening exposing the pad region of the wiring;
(E) an aluminum nitride film formed in the pad region of the wiring,
(F) The semiconductor device, wherein the aluminum nitride film is thicker than a natural aluminum nitride film formed between the antireflection film and the first insulating film.   21. The semiconductor device according to claim 20, wherein the thickness of the aluminum nitride film is not less than 10 nm and not more than 30 nm.   21. The semiconductor device according to claim 20, wherein the antireflection film is a titanium nitride film or a silicon oxynitride film.   21. The semiconductor device according to claim 20, further comprising a photosensitive polyimide film formed on the first insulating film and opening the pad region.   21. The semiconductor device according to claim 20, wherein a surface of the wiring recedes in the pad region.   21. The semiconductor device according to claim 20, further comprising a probe needle contact mark in the pad region.