WO2011074155A1 - Semiconductor device and manufacturing method for same - Google Patents

Semiconductor device and manufacturing method for same Download PDF

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Publication number
WO2011074155A1
WO2011074155A1 PCT/JP2010/004730 JP2010004730W WO2011074155A1 WO 2011074155 A1 WO2011074155 A1 WO 2011074155A1 JP 2010004730 W JP2010004730 W JP 2010004730W WO 2011074155 A1 WO2011074155 A1 WO 2011074155A1
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Prior art keywords
region
protective film
semiconductor device
scribe region
semiconductor
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PCT/JP2010/004730
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French (fr)
Japanese (ja)
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平野博茂
伊藤史人
太田行俊
小池功二
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パナソニック株式会社
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Publication of WO2011074155A1 publication Critical patent/WO2011074155A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Definitions

  • the present invention relates to a semiconductor device formed by dividing a semiconductor wafer on which a plurality of semiconductor elements are formed into chips, and a manufacturing method thereof, and more particularly, to a semiconductor device in which a back surface of a semiconductor wafer is ground and a manufacturing method thereof.
  • the semiconductor device is manufactured by forming a plurality of element formation regions, each of which is a semiconductor chip including semiconductor elements, on a semiconductor wafer. As shown in FIG. 12A and FIG. 12B, a center for cutting the semiconductor wafer 101 into individual semiconductor chips between the adjacent element formation regions 101A in the semiconductor wafer 101 is provided. A scribe line 103 having a line 103a is formed. Here, a protective film 102 for protecting the element formation region 101A is formed on each element formation region 101A.
  • the thickness of the semiconductor wafer 101 is set to about 500 ⁇ m to 1000 ⁇ m in order to maintain its strength.
  • the thickness of the semiconductor chip needs to be about 50 ⁇ m to 400 ⁇ m. For this reason, after the semiconductor wafer 101 is thinned to a desired thickness, the semiconductor wafer 101 is cut vertically and horizontally along the scribe line 103.
  • the surface (back surface) of the semiconductor wafer 101 opposite to the element formation region 101A is ground. That is, in the back grinding process, an adhesive protective sheet 104 is attached on the semiconductor wafer 101 so as to cover the entire surface. Thereafter, the semiconductor wafer 101 is held on the stage 105 via the protective sheet 104. The back surface of the semiconductor wafer 101 is ground by the cutting unit 106 of the grinding device. At this time, there is no problem if the protective sheet 104 and the surface of the semiconductor wafer 101 are in close contact with each other. For example, when the surface of the scribe line 103 is low, grinding scraps during back surface grinding are removed from the lowered portion. Contaminated water containing can enter.
  • Reference numeral 10 shown in FIG. 14 is a mask for exposure of a protective film made of a resin material.
  • a scribe pattern 13 is formed between a plurality of chip patterns 12, and an area corresponding to a peripheral portion of a semiconductor wafer is The mask pattern 11 is shown as being masked.
  • the conventional method for manufacturing a semiconductor device cannot cope with the case where a protective film, an element structure, or a manufacturing process in which the thickness of the peripheral portion of the semiconductor wafer cannot be reduced, and is cut from a scribe line during back surface grinding. There exists a problem that there exists a possibility that refuse etc. may permeate.
  • An object of the present invention is to solve the above-described problems and to prevent intrusion of cutting wastes and the like from a scribe region when the back surface of a semiconductor wafer is ground.
  • a semiconductor device is provided with a protective film on the scribe region.
  • a semiconductor device includes an element formation region in which a semiconductor element is formed on a semiconductor substrate, a scribe region formed around the element formation region in the semiconductor substrate, an upper portion of the element formation region, and a scribe region. And a protective film for protecting the element formation region and the scribe region.
  • the protective film is formed on the element forming region and the scribe region, the protective film of the protective tape to be applied when grinding the back surface of the semiconductor substrate in the wafer state The adhesion is improved even on the scribe region. For this reason, since it becomes difficult to permeate the water containing grinding waste between the protective tape and the protective film, contamination of the surface of the semiconductor wafer by the grinding waste can be prevented.
  • the protective film may be made of a resin material.
  • each element formation region has a seal ring made of a conductor formed so as to surround each, and the protective film is the entire surface of the region outside the seal ring on the scribe region. It may be formed.
  • the semiconductor device of the present invention may further include an evaluation pad formed on the scribe region for evaluating the semiconductor element, and the protective film may be formed on the scribe region except for the evaluation pad.
  • the protective film may be formed with a predetermined width in the central region of the scribe region.
  • the predetermined width of the protective film may be smaller than the cutting width of the semiconductor substrate.
  • the protective film does not contact the side surface of the blade that cuts the scribe region.
  • the protective film is made of an organic material. It is possible to make it difficult to cause clogging of the blade side surface.
  • the semiconductor device of the present invention further includes an evaluation pad that is formed on the scribe region and evaluates the semiconductor element, and the protective film is formed so as to surround a part of the periphery of the evaluation pad. It may be.
  • the protective film may be formed linearly on the scribe region along the scribe region.
  • the linear protective film may be divided into at least two on the scribe region.
  • At least two linear protective films may be formed on the scribe region so as to surround each element formation region.
  • a method of manufacturing a semiconductor device includes an element formation region in which a semiconductor element is formed on a semiconductor substrate, a scribe region formed around the element formation region in the semiconductor substrate, an upper portion of the element formation region, and a scribe region.
  • a method for manufacturing a semiconductor device having a protective film for protecting an element formation region and a scribe region formed thereon, and sticking an adhesive protective tape to the entire surface of the protective film in a semiconductor substrate in a wafer state And a step of grinding a surface of the semiconductor substrate on which the protective tape is affixed to the side opposite to the protective tape, and a step of peeling the protective tape from the semiconductor substrate.
  • the protective film is formed on the element formation region and the scribe region, the protective tape is applied when the back surface of the semiconductor substrate in the wafer state is ground.
  • the adhesion with the protective film is improved also on the scribe region. For this reason, since it becomes difficult to permeate the water containing grinding waste between the protective tape and the protective film, contamination of the surface of the semiconductor wafer by the grinding waste can be prevented.
  • the method of manufacturing a semiconductor device after the protective tape is peeled off from the semiconductor substrate, the semiconductor substrate in the scribe region is cut through the protective film by the cutting means in the wafer state, thereby separating the semiconductor substrate for each element forming region. It is preferable that the method further includes a step of dividing into two.
  • the semiconductor device semiconductor chip obtained by dividing is not contaminated by grinding dust, the reliability of the semiconductor device can be improved.
  • At least one of a blade and a laser beam can be used as the cutting means.
  • the semiconductor device and the method of manufacturing the same when grinding the back surface of the semiconductor wafer, it is possible to prevent intrusion of grinding scraps and the like from the scribe region. Can be prevented.
  • FIG. 1A and 1B show a semiconductor device according to the first embodiment of the present invention
  • FIG. 1A is a plan view
  • FIG. 1B is a plan view of FIG. It is sectional drawing in the Ib-Ib line.
  • 2A and 2B are partial enlarged views of the semiconductor device according to the first embodiment of the present invention
  • FIG. 2A is a plan view
  • FIG. FIG. 3 is a sectional view taken along line IIb-IIb in FIG.
  • FIG. 3 is a schematic cross-sectional view showing a back grinding step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view showing a dicing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 5A and 5B are partially enlarged views of a semiconductor device according to a modification of the first embodiment of the present invention
  • FIG. 5A is a plan view
  • FIG. FIG. 5B is a cross-sectional view taken along the line Vb-Vb in FIG. 6A and 6B are partially enlarged views of a semiconductor device according to the second embodiment of the present invention
  • FIG. 6A is a plan view
  • FIG. FIG. 7 is a schematic cross-sectional view of a dicing process taken along line VIb-VIb in FIG.
  • FIGS. 7A and 7B are partially enlarged views of a semiconductor device according to a first modification of the second embodiment of the present invention
  • FIG. 7A is a plan view.
  • FIG. 7B is a schematic cross-sectional view of the dicing process along the line VIIb-VIIb in FIG. 8A and 8B are partially enlarged views of a semiconductor device according to a second modification of the second embodiment of the present invention
  • FIG. 8A is a plan view
  • 8 (b) is a schematic cross-sectional view of the dicing process along the line VIIIb-VIIIb in FIG. 8 (a).
  • 9A and 9B are partially enlarged plan views of a semiconductor device according to the third embodiment of the present invention.
  • FIG. 10A and FIG. 10B are partially enlarged plan views of a semiconductor device according to a first modification of the third embodiment of the present invention.
  • FIG. 11B are partially enlarged plan views of a semiconductor device according to a second modification of the third embodiment of the present invention.
  • 12A and 12B show a semiconductor device according to a conventional example
  • FIG. 12A is a plan view
  • FIG. 12B is a cross-sectional view taken along line XIIb-XIIb in FIG.
  • FIG. 13 is a schematic cross-sectional view showing a dicing process in the conventional method for manufacturing a semiconductor device.
  • FIG. 14 is a plan view showing a mask for a protective film in a method of manufacturing a semiconductor device according to another conventional example.
  • a semiconductor wafer is formed between adjacent element formation regions 1A in a semiconductor wafer 1 in which a plurality of element (device) formation regions 1A are formed in a matrix.
  • a scribe region 3 having a center line 3a for cutting 1 and dividing it into individual semiconductor chips is formed.
  • a protective film 2 for protecting the element formation region 1A is formed on each element formation region 1A.
  • 2 (a) and 2 (b) show an enlarged region where the scribe region 3 intersects.
  • an evaluation element (TEG: test element group) or the like of a semiconductor element may be formed also in the scribe region 3 in the semiconductor wafer 1.
  • desired active elements such as transistors and wirings are formed on the main surface of a semiconductor wafer (slice) cut out from a silicon ingot and processed on the front and back surfaces thereof.
  • a semiconductor wafer slice
  • a plurality of element formation regions 1A corresponding to the divided semiconductor chips are formed in the semiconductor wafer 1, and a scribe region 3 that is a cutting region is formed between the element formation regions 1A. Is provided.
  • a passivation film made of silicon nitride (SiN) or TEOS (tetra-ethyl-ortho-silicate) or the like is formed on the surface of each element formation region 1A, and the passivation film is formed on the passivation film.
  • the protective film 2 made of an organic resin material such as polybenzoxazole (PBO) or polyimide is formed.
  • the protective film 2 can be formed by a spin coating method and a lithography method if a photosensitive resin material is used as the organic resin material. Note that, in the pad portion that electrically extracts the function of the element in each element formation region 1A, the passivation film and the protective film 2 are not formed, but the pad portion is exposed.
  • the protective film 2 is also formed on the scribe region 3 between the element formation regions 1A in the semiconductor wafer 1.
  • substantially all of the outer portions of the seal ring 1a made of metal, for example, formed on the periphery of each element formation region 1A on the scribe region 3 are formed.
  • the protective film 2 is left.
  • the opposite surface (back surface) of the protective film 2 in the semiconductor wafer 1 is ground. That is, in the back grinding process, an adhesive protective sheet 4 is attached on the semiconductor wafer 1 so as to cover the entire surface of the semiconductor wafer 1. Thereafter, the semiconductor wafer 1 is held on the stage 5 via the protective sheet 4. Subsequently, the back surface of the semiconductor wafer 1 is ground by the cutting unit 6 of the grinding device so that the thickness of the semiconductor wafer is about 50 ⁇ m to 400 ⁇ m.
  • the protective sheet 4 is peeled off from the protective film 2 on the surface of the semiconductor wafer 1.
  • the semiconductor wafer 1 is cut by the cutting blade 7 along the center line 3 a of each scribe region 3 of the semiconductor wafer 1.
  • the width of the scribe region 3 is about 100 ⁇ m
  • the width of the protective film 2 is also about 100 ⁇ m.
  • the cutting means used in the dicing process is not limited to the blade 7, and a laser beam may be used instead of the blade, or the blade and the laser beam may be used in combination.
  • the area of the protective film 2 formed on the semiconductor wafer 1 having the element formation region 1A is increased by the amount formed on the scribe region 3, so that the semiconductor wafer 1, the adhesion of the protective tape 4 to the surface of the semiconductor wafer 1 is improved. For this reason, in the back grinding process, it becomes difficult for water containing grinding waste to enter the element forming region 1A. However, although a small amount of water may enter the element formation region 1A in the first row from the outside on the semiconductor wafer 1, it does not enter the effective element formation region 1A in the inner side from the second row. .
  • FIG. 5A and FIG. 5B show a modification of the first embodiment.
  • the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. The same applies to the following embodiments and modifications thereof.
  • an evaluation pad for evaluating the electrical characteristics of the element formation region 1A including the TEG on the scribe region 3 of the semiconductor wafer 1 is used. 8 is selectively provided.
  • the protective film 2 made of the resin material according to this modification is formed so as to expose each evaluation pad 8 in the scribe region 3. Therefore, also in this modification example, the protective film 2 is formed on the scribe region 3 between the element formation regions 1A in the semiconductor wafer 1 except for the respective evaluation pads 8, so that the first embodiment The same effect as the form can be obtained.
  • the protective film 2 made of a resin material formed on the scribe region 3 is placed on the center line 3a of the scribe region 3.
  • the width is about 20 ⁇ m, which is smaller than the width of the dicing blade 7.
  • the width of the blade 7 is, for example, about 30 ⁇ m to 40 ⁇ m, and the width of the protective film 2 on the scribe region 3 is set so that it can be removed by a dicing process. .
  • the side surface of the blade 7 is likely to be clogged with the resin material, and the side surface of the blade 7 needs to be polished frequently.
  • the blade 7 is not easily clogged because the side surface of the blade 7 does not contact the protective film 7.
  • the protective film 2 is also provided on the scribe region 3 in the semiconductor wafer 1 as in the first embodiment, effective element formation arranged on the inner side of the semiconductor wafer 1 during back surface grinding is performed. The contaminated water during grinding does not enter the region 1A.
  • FIG. 7A and FIG. 7B show a first modification of the second embodiment. As shown in FIGS. 7A and 7B, in the first modified example, the evaluation is performed to evaluate the electrical characteristics of the element formation region 1A including the TEG on the scribe region 3 of the semiconductor wafer 1. A pad 8 is selectively provided.
  • the protective film 2 made of the resin material according to the first modification is formed so as to surround each evaluation pad 8 in the scribe region 3. . Accordingly, also in the first modified example, since the protective film 2 is continuously formed on the scribe region 3 between the element forming regions 1A in the semiconductor wafer 1, the evaluation pad 8 is formed. In addition, the adhesion between the protective sheet 4 and the protective film 2 is not weakened.
  • the protective film 2 formed on the scribe region 3 is formed on the center line 3a of the scribe region 3 so as to be narrower than the width of the blade 7, and when the semiconductor wafer 1 is diced. Since the blade 7 is configured to cut the protective film 2 only at the periphery of the evaluation pad 8, the blade 7 is hardly clogged. Therefore, the same effect as in the second embodiment can be obtained.
  • FIG. 8A and FIG. 8B show a second modification of the second embodiment.
  • the protective film 2 formed on the scribe region 3 is not surrounded by the entire periphery of the evaluation pad 8, It is formed so as to surround only one side with respect to the center line 3a of the evaluation pad 8.
  • the protective film 2 made of a resin material formed on the scribe region 3 is formed along the center line 3 a of the scribe region 3.
  • the protective film 2A is formed as a second protective film 2B surrounding each element forming region 1A. Accordingly, in the region where the evaluation pad 8 is not formed in the scribe region 3, the first protective film 2A on the center line 3a of the scribe region 3 and the second protective film 2B surrounding each element forming region 1A.
  • the three linear protective films 2A and 2B are formed.
  • the periphery of the evaluation pad 8 is surrounded by the first protective film 2A and the second protective film 2B.
  • the width of the first protective film 2A is about 20 ⁇ m
  • the width of the second protective film 2B is about 10 ⁇ m to 20 ⁇ m.
  • FIG. 10 shows a first modification of the third embodiment.
  • the first modification only the second protective film 2 ⁇ / b> B surrounding each element formation region 1 ⁇ / b> A is formed without providing the first protective film 2 ⁇ / b> A on the scribe region 3. Yes.
  • the periphery of the evaluation pad 8 is formed so as to be surrounded by the second protective film 2A.
  • a connection portion 2a is provided on the scribe region 3 to connect the second protective films 2B extending in parallel with each other in a direction intersecting with the second protective films 2B.
  • the second protective film 2B formed on the scribe region 3 can greatly reduce the contact area with the dicing blade 7, so that the clogging of the blade 7 is greatly improved. Can do.
  • the second protective film 2B formed on the scribe region 3 is locally connected by the connecting portion 2a, so that contaminated water containing grinding scraps when grinding the back surface of the semiconductor wafer 1 is performed. Can be prevented from entering the scribe region 3.
  • FIG. 11 shows a second modification of the third embodiment.
  • a second protective film 2B formed on the scribe region 3 and surrounding each element formation region 1A is formed so as to cross in a cross pattern. Accordingly, the connecting portion 2a between the second protective films 2B is a crossed cross-shaped portion.
  • the scribe region 3 has a configuration in which the intrusion path of contaminated water during grinding is cut. Furthermore, the amount of grinding by the blade 7 in the second protective film 2B on the scribe region 3 can be reduced. As a result, water can be prevented from entering during back grinding, and clogging of the blade 7 can be significantly suppressed.
  • the semiconductor device and the manufacturing method thereof according to the present invention can prevent the intrusion of grinding debris and the like from the scribe region when grinding the back surface of the semiconductor wafer, the surface of the element forming region can be prevented from being contaminated. This is useful for a semiconductor device in which the back surface of a wafer is ground, a manufacturing method thereof, and the like.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Disclosed is a semiconductor device having an element formation region (1A) wherein an element is formed on a semiconductor wafer (1), and a scribe region (3) formed on the periphery of the element formation region (1A) on the semiconductor wafer (1). Furthermore, the semiconductor device has a protective film (2) which is formed on and protects the element formation region (1A) and the scribe region (3).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、複数の半導体素子が形成された半導体ウエハをチップ状に分割してなる半導体装置及びその製造方法に関し、特に、半導体ウエハの裏面が研削される半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device formed by dividing a semiconductor wafer on which a plurality of semiconductor elements are formed into chips, and a manufacturing method thereof, and more particularly, to a semiconductor device in which a back surface of a semiconductor wafer is ground and a manufacturing method thereof.
　半導体装置は、それぞれが半導体素子を含む半導体チップとなる複数の素子形成領域を半導体ウエハに形成して製造される。図１２（ａ）及び図１２（ｂ）に示すように、半導体ウエハ１０１における隣り合う素子形成領域１０１Ａ同士の間には、半導体ウエハ１０１を切断して個々の半導体チップに分割するための、中心線１０３ａを持つスクライブライン１０３が形成されている。ここでは、各素子形成領域１０１Ａの上に、該素子形成領域１０１Ａを保護する保護膜１０２が形成されている。 The semiconductor device is manufactured by forming a plurality of element formation regions, each of which is a semiconductor chip including semiconductor elements, on a semiconductor wafer. As shown in FIG. 12A and FIG. 12B, a center for cutting the semiconductor wafer 101 into individual semiconductor chips between the adjacent element formation regions 101A in the semiconductor wafer 101 is provided. A scribe line 103 having a line 103a is formed. Here, a protective film 102 for protecting the element formation region 101A is formed on each element formation region 101A.
　半導体ウエハ１０１の厚さは、製造工程においては、その強度を保つため、５００μｍから１０００μｍ程度とされている。各チップに分割され、それをパッケージに組み込む場合には、半導体チップの厚さは、５０μｍから４００μｍ程度にする必要がある。このため、半導体ウエハ１０１を所望の厚さにまで薄くした後、該半導体ウエハ１０１をスクライブライン１０３に沿って縦横に切断する方法が採られている。 In the manufacturing process, the thickness of the semiconductor wafer 101 is set to about 500 μm to 1000 μm in order to maintain its strength. When the chip is divided into chips and incorporated in a package, the thickness of the semiconductor chip needs to be about 50 μm to 400 μm. For this reason, after the semiconductor wafer 101 is thinned to a desired thickness, the semiconductor wafer 101 is cut vertically and horizontally along the scribe line 103.
　半導体ウエハ１０１は、図１３に示すように、素子形成領域１０１Ａと反対側の面（裏面）が研削される。すなわち、裏面研削（バックグラインド）工程において、半導体ウエハ１０１の上に、その全面を覆うように粘着性を有する保護シート１０４を貼り付ける。その後、半導体ウエハ１０１をステージ１０５の上に保護シート１０４を介して保持する。半導体ウエハ１０１の裏面は、研削装置の切削部１０６によって研削される。このとき、保護シート１０４と半導体ウエハ１０１の表面とが密着すれば問題はないが、例えば、スクライブライン１０３の表面が低くなっている場合には、低くなった部分から裏面研削時の研削屑を含む汚染された水が浸入することがある。 As shown in FIG. 13, the surface (back surface) of the semiconductor wafer 101 opposite to the element formation region 101A is ground. That is, in the back grinding process, an adhesive protective sheet 104 is attached on the semiconductor wafer 101 so as to cover the entire surface. Thereafter, the semiconductor wafer 101 is held on the stage 105 via the protective sheet 104. The back surface of the semiconductor wafer 101 is ground by the cutting unit 106 of the grinding device. At this time, there is no problem if the protective sheet 104 and the surface of the semiconductor wafer 101 are in close contact with each other. For example, when the surface of the scribe line 103 is low, grinding scraps during back surface grinding are removed from the lowered portion. Contaminated water containing can enter.
　これを防ぐために、下記の特許文献１においては、半導体ウエハに形成される樹脂材からなる保護膜の周縁部を除去して該周縁部の高さを低くし、保護シートと半導体ウエハ自体との密着性を向上させることにより、裏面研削時の汚染された水が半導体ウエハと保護シートとの間から浸入しないように工夫している。なお、図１４に示す符号１０は、樹脂材からなる保護膜の露光用のマスクであって、複数のチップパターン１２の間にスクライブパターン１３が形成され、半導体ウエハの周縁部に相当する領域は、マスクパターン１１によりマスクされる様子を示している。 In order to prevent this, in Patent Document 1 below, the peripheral portion of the protective film made of a resin material formed on the semiconductor wafer is removed to reduce the height of the peripheral portion, and the protective sheet and the semiconductor wafer itself are removed. By improving the adhesion, it is devised so that contaminated water during back surface grinding does not enter between the semiconductor wafer and the protective sheet. Reference numeral 10 shown in FIG. 14 is a mask for exposure of a protective film made of a resin material. A scribe pattern 13 is formed between a plurality of chip patterns 12, and an area corresponding to a peripheral portion of a semiconductor wafer is The mask pattern 11 is shown as being masked.
特開２００７－２１４２６８号公報JP 2007-214268 A
　しかしながら、前記従来の半導体装置の製造方法は、半導体ウエハの周縁部の厚さを小さくすることができない保護膜、素子構造又は製造工程を用いる場合には対応できず、裏面研削時にスクライブラインから切削屑等が浸入してしまうおそれがあるという問題がある。 However, the conventional method for manufacturing a semiconductor device cannot cope with the case where a protective film, an element structure, or a manufacturing process in which the thickness of the peripheral portion of the semiconductor wafer cannot be reduced, and is cut from a scribe line during back surface grinding. There exists a problem that there exists a possibility that refuse etc. may permeate.
　本発明は、前記の問題を解決し、半導体ウエハの裏面を研削する際に、スクライブ領域からの切削屑等の浸入を防止できるようにすることを目的とする。 An object of the present invention is to solve the above-described problems and to prevent intrusion of cutting wastes and the like from a scribe region when the back surface of a semiconductor wafer is ground.
　前記の目的を達成するため、本発明は、半導体装置をそのスクライブ領域の上にも保護膜を設ける構成とする。 In order to achieve the above object, according to the present invention, a semiconductor device is provided with a protective film on the scribe region.
　具体的に、本発明に係る半導体装置は、半導体基板に半導体素子が形成された素子形成領域と、半導体基板における素子形成領域の周囲に形成されたスクライブ領域と、素子形成領域の上及びスクライブ領域の上に形成され、素子形成領域及びスクライブ領域を保護する保護膜とを備えている。 Specifically, a semiconductor device according to the present invention includes an element formation region in which a semiconductor element is formed on a semiconductor substrate, a scribe region formed around the element formation region in the semiconductor substrate, an upper portion of the element formation region, and a scribe region. And a protective film for protecting the element formation region and the scribe region.
　本発明の半導体装置によると、素子形成領域の上及びスクライブ領域の上に形成された保護膜を備えているため、ウエハ状態にある半導体基板の裏面を研削する際に貼る保護テープの保護膜との密着性がスクライブ領域上においても向上する。このため、研削屑を含む水が保護テープと保護膜との間に染み込み難くなるので、研削屑による半導体ウエハの表面の汚染を防止することができる。 According to the semiconductor device of the present invention, since the protective film is formed on the element forming region and the scribe region, the protective film of the protective tape to be applied when grinding the back surface of the semiconductor substrate in the wafer state The adhesion is improved even on the scribe region. For this reason, since it becomes difficult to permeate the water containing grinding waste between the protective tape and the protective film, contamination of the surface of the semiconductor wafer by the grinding waste can be prevented.
　本発明の半導体装置において、保護膜は樹脂材により構成されていてもよい。 In the semiconductor device of the present invention, the protective film may be made of a resin material.
　本発明の半導体装置において、各素子形成領域は、それぞれを囲むように形成された、導体からなるシールリングを有しており、保護膜はスクライブ領域の上におけるシールリングよりも外側の領域の全面に形成されていてもよい。 In the semiconductor device of the present invention, each element formation region has a seal ring made of a conductor formed so as to surround each, and the protective film is the entire surface of the region outside the seal ring on the scribe region. It may be formed.
　本発明の半導体装置は、スクライブ領域の上に形成され、半導体素子を評価する評価用パッドをさらに備え、保護膜は、スクライブ領域の上における評価用パッドを除く領域に形成されていてもよい。 The semiconductor device of the present invention may further include an evaluation pad formed on the scribe region for evaluating the semiconductor element, and the protective film may be formed on the scribe region except for the evaluation pad.
　本発明の半導体装置において、保護膜はスクライブ領域のうちの中央領域に所定の幅で形成されていてもよい。 In the semiconductor device of the present invention, the protective film may be formed with a predetermined width in the central region of the scribe region.
　この場合に、保護膜における所定の幅は、半導体基板の切断幅よりも小さくてもよい。 In this case, the predetermined width of the protective film may be smaller than the cutting width of the semiconductor substrate.
　このようにすると、ウエハ状態にある半導体基板に対してブレードを用いたダイシング工程において、スクライブ領域を切断するブレードの側面に保護膜が接触しないため、例えば該保護膜が有機系材料からなる場合に、ブレード側面の目詰まりを起こし難くすることができる。 In this case, in the dicing process using the blade on the semiconductor substrate in the wafer state, the protective film does not contact the side surface of the blade that cuts the scribe region. For example, when the protective film is made of an organic material. It is possible to make it difficult to cause clogging of the blade side surface.
　またこの場合に、本発明の半導体装置は、スクライブ領域の上に形成され、半導体素子を評価する評価用パッドをさらに備え、保護膜は、評価用パッドの周囲の一部を囲むように形成されていてもよい。 In this case, the semiconductor device of the present invention further includes an evaluation pad that is formed on the scribe region and evaluates the semiconductor element, and the protective film is formed so as to surround a part of the periphery of the evaluation pad. It may be.
　本発明の半導体装置において、保護膜は、スクライブ領域の上に、該スクライブ領域に沿って線状に形成されていてもよい。 In the semiconductor device of the present invention, the protective film may be formed linearly on the scribe region along the scribe region.
　この場合に、スクライブ領域の上において、線状の保護膜は少なくとも２本に分けて形成されていてもよい。 In this case, the linear protective film may be divided into at least two on the scribe region.
　また、この場合に、スクライブ領域の上において、線状の保護膜は、各素子形成領域をそれぞれ囲むように少なくとも２本で形成されていてもよい。 Further, in this case, at least two linear protective films may be formed on the scribe region so as to surround each element formation region.
　本発明に係る半導体装置の製造方法は、半導体基板に半導体素子が形成された素子形成領域と、半導体基板における素子形成領域の周囲に形成されたスクライブ領域と、素子形成領域の上及びスクライブ領域の上に形成され、素子形成領域及びスクライブ領域を保護する保護膜とを有する半導体装置の製造方法を対象とし、ウエハ状態の半導体基板における保護膜の上の全面に、粘着性を有する保護テープを貼る工程と、保護テープが貼られた半導体基板における保護テープと反対側の面を研削する工程と、保護テープを半導体基板から剥がす工程とを備えている。 A method of manufacturing a semiconductor device according to the present invention includes an element formation region in which a semiconductor element is formed on a semiconductor substrate, a scribe region formed around the element formation region in the semiconductor substrate, an upper portion of the element formation region, and a scribe region. A method for manufacturing a semiconductor device having a protective film for protecting an element formation region and a scribe region formed thereon, and sticking an adhesive protective tape to the entire surface of the protective film in a semiconductor substrate in a wafer state And a step of grinding a surface of the semiconductor substrate on which the protective tape is affixed to the side opposite to the protective tape, and a step of peeling the protective tape from the semiconductor substrate.
　本発明の半導体装置の製造方法によると、素子形成領域の上及びスクライブ領域の上に形成された保護膜を有しているため、ウエハ状態にある半導体基板の裏面を研削する際に貼る保護テープの保護膜との密着性がスクライブ領域上においても向上する。このため、研削屑を含む水が保護テープと保護膜との間に染み込み難くなるので、研削屑による半導体ウエハの表面の汚染を防止することができる。 According to the method for manufacturing a semiconductor device of the present invention, since the protective film is formed on the element formation region and the scribe region, the protective tape is applied when the back surface of the semiconductor substrate in the wafer state is ground. The adhesion with the protective film is improved also on the scribe region. For this reason, since it becomes difficult to permeate the water containing grinding waste between the protective tape and the protective film, contamination of the surface of the semiconductor wafer by the grinding waste can be prevented.
　本発明の半導体装置の製造方法は、保護テープを半導体基板から剥がした後に、スクライブ領域において、ウエハ状態の半導体基板を切断手段により保護膜を介して切断することにより、半導体基板を素子形成領域ごとに分割する工程をさらに備えていることが好ましい。 In the method of manufacturing a semiconductor device according to the present invention, after the protective tape is peeled off from the semiconductor substrate, the semiconductor substrate in the scribe region is cut through the protective film by the cutting means in the wafer state, thereby separating the semiconductor substrate for each element forming region. It is preferable that the method further includes a step of dividing into two.
　このようにすると、分割して得られた半導体装置（半導体チップ）には、研削屑による汚染がないため、半導体装置の信頼性の向上を図ることができる。 In this way, since the semiconductor device (semiconductor chip) obtained by dividing is not contaminated by grinding dust, the reliability of the semiconductor device can be improved.
　第２の半導体装置の製造方法において、切断手段にはブレード及びレーザ光のうちの少なくとも一方を用いることができる。 In the second method for manufacturing a semiconductor device, at least one of a blade and a laser beam can be used as the cutting means.
　本発明に係る半導体装置及びその製造方法によると、半導体ウエハの裏面を研削する際に、スクライブ領域からの研削屑等の浸入を防止できるため、半導体ウエハにおける素子形成領域及びスクライブ領域の表面の汚れを防ぐことができる。 According to the semiconductor device and the method of manufacturing the same according to the present invention, when grinding the back surface of the semiconductor wafer, it is possible to prevent intrusion of grinding scraps and the like from the scribe region. Can be prevented.
図１（ａ）及び図１（ｂ）は本発明の第１の実施形態に係る半導体装置を示し、図１（ａ）は平面図であり、図１（ｂ）は図１（ａ）のＩｂ－Ｉｂ線における断面図である。1A and 1B show a semiconductor device according to the first embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a plan view of FIG. It is sectional drawing in the Ib-Ib line. 図２（ａ）及び図２（ｂ）は本発明の第１の実施形態に係る半導体装置の部分的な拡大図であり、図２（ａ）は平面図であり、図２（ｂ）は図２（ａ）のIIｂ－IIｂ線における断面図である。2A and 2B are partial enlarged views of the semiconductor device according to the first embodiment of the present invention, FIG. 2A is a plan view, and FIG. FIG. 3 is a sectional view taken along line IIb-IIb in FIG. 図３は本発明の第１の実施形態に係る半導体装置の製造方法における裏面研削工程を示す模式的な断面図である。FIG. 3 is a schematic cross-sectional view showing a back grinding step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図４は本発明の第１の実施形態に係る半導体装置の製造方法におけるダイシング工程を示す模式的な断面図である。FIG. 4 is a schematic cross-sectional view showing a dicing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図５（ａ）及び図５（ｂ）は本発明の第１の実施形態の一変形例に係る半導体装置の部分的な拡大図であり、図５（ａ）は平面図であり、図５（ｂ）は図５（ａ）のＶｂ－Ｖｂ線における断面図である。5A and 5B are partially enlarged views of a semiconductor device according to a modification of the first embodiment of the present invention, FIG. 5A is a plan view, and FIG. FIG. 5B is a cross-sectional view taken along the line Vb-Vb in FIG. 図６（ａ）及び図６（ｂ）は本発明の第２の実施形態に係る半導体装置の部分的な拡大図であり、図６（ａ）は平面図であり、図６（ｂ）は図６（ａ）のVIｂ－VIｂ線におけるダイシング工程の模式的な断面図である。6A and 6B are partially enlarged views of a semiconductor device according to the second embodiment of the present invention, FIG. 6A is a plan view, and FIG. FIG. 7 is a schematic cross-sectional view of a dicing process taken along line VIb-VIb in FIG. 図７（ａ）及び図７（ｂ）は本発明の第２の実施形態の第１変形例に係る半導体装置の部分的な拡大図であり、図７（ａ）は平面図であり、図７（ｂ）は図７（ａ）のVIIｂ－VIIｂ線におけるダイシング工程の模式的な断面図である。FIGS. 7A and 7B are partially enlarged views of a semiconductor device according to a first modification of the second embodiment of the present invention, and FIG. 7A is a plan view. FIG. 7B is a schematic cross-sectional view of the dicing process along the line VIIb-VIIb in FIG. 図８（ａ）及び図８（ｂ）は本発明の第２の実施形態の第２変形例に係る半導体装置の部分的な拡大図であり、図８（ａ）は平面図であり、図８（ｂ）は図８（ａ）のVIIIｂ－VIIIｂ線におけるダイシング工程の模式的な断面図である。8A and 8B are partially enlarged views of a semiconductor device according to a second modification of the second embodiment of the present invention, and FIG. 8A is a plan view. 8 (b) is a schematic cross-sectional view of the dicing process along the line VIIIb-VIIIb in FIG. 8 (a). 図９（ａ）及び図９（ｂ）は本発明の第３の実施形態に係る半導体装置の部分的な拡大平面図である。9A and 9B are partially enlarged plan views of a semiconductor device according to the third embodiment of the present invention. 図１０（ａ）及び図１０（ｂ）は本発明の第３の実施形態の第１変形例に係る半導体装置の部分的な拡大平面図である。FIG. 10A and FIG. 10B are partially enlarged plan views of a semiconductor device according to a first modification of the third embodiment of the present invention. 図１１（ａ）及び図１１（ｂ）は本発明の第３の実施形態の第２変形例に係る半導体装置の部分的な拡大平面図である。FIG. 11A and FIG. 11B are partially enlarged plan views of a semiconductor device according to a second modification of the third embodiment of the present invention. 図１２（ａ）及び図１２（ｂ）は従来例に係る半導体装置を示し、図１２（ａ）は平面図であり、図１２（ｂ）は図１２（ａ）のXIIｂ－XIIｂ線における断面図である。12A and 12B show a semiconductor device according to a conventional example, FIG. 12A is a plan view, and FIG. 12B is a cross-sectional view taken along line XIIb-XIIb in FIG. FIG. 図１３は従来例に係る半導体装置の製造方法におけるダイシング工程を示す模式的な断面図である。FIG. 13 is a schematic cross-sectional view showing a dicing process in the conventional method for manufacturing a semiconductor device. 図１４は他の従来例に係る半導体装置の製造方法における保護膜用のマスクを示す平面図である。FIG. 14 is a plan view showing a mask for a protective film in a method of manufacturing a semiconductor device according to another conventional example.
　（第１の実施形態）
　本発明の第１の実施形態に係る半導体装置について図１から図４を参照しながら説明する。 (First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.
　図１（ａ）及び図１（ｂ）に示すように、複数の素子（デバイス）形成領域１Ａが行列状に形成された半導体ウエハ１における隣り合う素子形成領域１Ａ同士の間には、半導体ウエハ１を切断して個々の半導体チップに分割するための、中心線３ａを持つスクライブ領域３が形成されている。さらに、各素子形成領域１Ａの上に、該素子形成領域１Ａを保護する保護膜２が形成されている。また、図２（ａ）及び図２（ｂ）に、スクライブ領域３が交差する領域を拡大して示す。図１及び図２に示すように、半導体ウエハ１におけるスクライブ領域３においても、半導体素子の評価用素子（ＴＥＧ：test element group）等が形成される場合もある。 As shown in FIGS. 1A and 1B, a semiconductor wafer is formed between adjacent element formation regions 1A in a semiconductor wafer 1 in which a plurality of element (device) formation regions 1A are formed in a matrix. A scribe region 3 having a center line 3a for cutting 1 and dividing it into individual semiconductor chips is formed. Further, a protective film 2 for protecting the element formation region 1A is formed on each element formation region 1A. 2 (a) and 2 (b) show an enlarged region where the scribe region 3 intersects. As shown in FIGS. 1 and 2, an evaluation element (TEG: test element group) or the like of a semiconductor element may be formed also in the scribe region 3 in the semiconductor wafer 1.
　以下、第１の実施形態に係る半導体装置の製造方法について説明する。 Hereinafter, a method for manufacturing the semiconductor device according to the first embodiment will be described.
　例えば、シリコンインゴットから切り出され、その表面及び裏面等が加工された半導体ウエハ（スライス）の主面上に、トランジスタ等の所望の能動素子及び配線等を形成する。このとき、上述したように、半導体ウエハ１には、分割後の各半導体チップに対応する複数の素子形成領域１Ａが形成され、各素子形成領域１Ａ同士の間には切断領域であるスクライブ領域３が設けられる。 For example, desired active elements such as transistors and wirings are formed on the main surface of a semiconductor wafer (slice) cut out from a silicon ingot and processed on the front and back surfaces thereof. At this time, as described above, a plurality of element formation regions 1A corresponding to the divided semiconductor chips are formed in the semiconductor wafer 1, and a scribe region 3 that is a cutting region is formed between the element formation regions 1A. Is provided.
　図示はしていないが、各素子形成領域１Ａの表面には、窒化シリコン（ＳｉＮ）又はＴＥＯＳ（tetra-ethyl-ortho-silicate）等からなるパッシベーション膜が形成されており、該パッシベーション膜の上に、例えばポリベンゾオキサゾール（ＰＢＯ）又はポリイミド等の有機樹脂材からなる保護膜２を形成する。具体的には、保護膜２は、有機樹脂材として感光性樹脂材を用いれば、スピン塗布法及びリソグラフィ法により形成することが可能となる。なお、各素子形成領域１Ａにおける素子の機能を電気的に外部に引き出すパッド部分においては、パッシベーション膜及び保護膜２を形成せず、パッド部分を露出するように形成する。 Although not shown, a passivation film made of silicon nitride (SiN) or TEOS (tetra-ethyl-ortho-silicate) or the like is formed on the surface of each element formation region 1A, and the passivation film is formed on the passivation film. For example, the protective film 2 made of an organic resin material such as polybenzoxazole (PBO) or polyimide is formed. Specifically, the protective film 2 can be formed by a spin coating method and a lithography method if a photosensitive resin material is used as the organic resin material. Note that, in the pad portion that electrically extracts the function of the element in each element formation region 1A, the passivation film and the protective film 2 are not formed, but the pad portion is exposed.
　第１の実施形態の特徴として、半導体ウエハ１における素子形成領域１Ａ同士の間のスクライブ領域３の上にも保護膜２を形成する。ここでは、図２（ｂ）に示すように、スクライブ領域３の上における、各素子形成領域１Ａの周縁部に形成された、例えば金属からなるシールリング１ａよりも外側部分のほぼすべての部分に保護膜２を残す構成としている。 As a feature of the first embodiment, the protective film 2 is also formed on the scribe region 3 between the element formation regions 1A in the semiconductor wafer 1. Here, as shown in FIG. 2 (b), substantially all of the outer portions of the seal ring 1a made of metal, for example, formed on the periphery of each element formation region 1A on the scribe region 3 are formed. The protective film 2 is left.
　次に、図３に示すように、半導体ウエハ１における保護膜２の反対側の面（裏面）を研削する。すなわち、裏面研削（バックグラインド）工程において、半導体ウエハ１の上に、該半導体ウエハ１の全面を覆うように粘着性を有する保護シート４を貼り付ける。その後、半導体ウエハ１をステージ５の上に保護シート４を介して保持する。続いて、半導体ウエハ１の裏面を研削装置の切削部６によって研削し、半導体ウエハの厚さを５０μｍ～４００μｍ程度の厚さとする。 Next, as shown in FIG. 3, the opposite surface (back surface) of the protective film 2 in the semiconductor wafer 1 is ground. That is, in the back grinding process, an adhesive protective sheet 4 is attached on the semiconductor wafer 1 so as to cover the entire surface of the semiconductor wafer 1. Thereafter, the semiconductor wafer 1 is held on the stage 5 via the protective sheet 4. Subsequently, the back surface of the semiconductor wafer 1 is ground by the cutting unit 6 of the grinding device so that the thickness of the semiconductor wafer is about 50 μm to 400 μm.
　次に、図４に示すように、半導体ウエハ１の表面上の保護膜２から保護シート４を剥がす。続いて、ダイシング工程において、半導体ウエハ１の各スクライブ領域３の中心線３ａに沿って、切削用のブレード７により半導体ウエハ１を切断する。ここで、ブレード７の幅（＝切断幅）は３０μｍ～４０μｍ程度で、スクライブ領域３の幅は約１００μｍで、保護膜２の幅も１００μｍ程度である。なお、ダイシング工程に用いる切削手段はブレード７に限られず、ブレードに代えてレーザ光を用いてもよく、また、ブレードとレーザ光とを併用してもよい。 Next, as shown in FIG. 4, the protective sheet 4 is peeled off from the protective film 2 on the surface of the semiconductor wafer 1. Subsequently, in the dicing process, the semiconductor wafer 1 is cut by the cutting blade 7 along the center line 3 a of each scribe region 3 of the semiconductor wafer 1. Here, the width of the blade 7 (= cut width) is about 30 μm to 40 μm, the width of the scribe region 3 is about 100 μm, and the width of the protective film 2 is also about 100 μm. The cutting means used in the dicing process is not limited to the blade 7, and a laser beam may be used instead of the blade, or the blade and the laser beam may be used in combination.
　このように、第１の実施形態によると、素子形成領域１Ａを有する半導体ウエハ１の上に形成される保護膜２の面積が、スクライブ領域３の上に形成した分だけ大きくなるため、半導体ウエハ１の裏面研削を行う際に、保護テープ４の半導体ウエハ１の表面に対する密着性が向上する。このため、裏面研削工程において、研削屑を含む水が素子形成領域１Ａに浸入し難くなる。但し、半導体ウエハ１上の外側から１列目の素子形成領域１Ａには少量の水が浸入するおそれは多少あるものの、２列目から内側の有効な素子形成領域１Ａには浸入することがない。 Thus, according to the first embodiment, the area of the protective film 2 formed on the semiconductor wafer 1 having the element formation region 1A is increased by the amount formed on the scribe region 3, so that the semiconductor wafer 1, the adhesion of the protective tape 4 to the surface of the semiconductor wafer 1 is improved. For this reason, in the back grinding process, it becomes difficult for water containing grinding waste to enter the element forming region 1A. However, although a small amount of water may enter the element formation region 1A in the first row from the outside on the semiconductor wafer 1, it does not enter the effective element formation region 1A in the inner side from the second row. .
　（第１の実施形態の一変形例）
　図５（ａ）及び図５（ｂ）に第１の実施形態の一変形例を示す。ここでは、図２に示した構成部材と同一の構成部材には同一の符号を付すことにより説明を省略する。また、以下の各実施形態及びその変形例においても同様とする。 (One modification of the first embodiment)
FIG. 5A and FIG. 5B show a modification of the first embodiment. Here, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. The same applies to the following embodiments and modifications thereof.
　図５（ａ）及び図５（ｂ）に示すように、本変形例においては、半導体ウエハ１のスクライブ領域３の上に、ＴＥＧを含む素子形成領域１Ａの電気的特性を評価する評価用パッド８が選択的に設けられている。 As shown in FIGS. 5A and 5B, in this modification, an evaluation pad for evaluating the electrical characteristics of the element formation region 1A including the TEG on the scribe region 3 of the semiconductor wafer 1 is used. 8 is selectively provided.
　このような構成を持つ半導体ウエハ１に対して、本変形例に係る樹脂材からなる保護膜２は、スクライブ領域３においては、各評価用パッド８を露出するように形成されている。従って、本変形例においても、半導体ウエハ１における素子形成領域１Ａ同士の間のスクライブ領域３の上には、各評価用パッド８を除いて保護膜２が形成されているため、第１の実施形態と同様の効果を得ることができる。 For the semiconductor wafer 1 having such a configuration, the protective film 2 made of the resin material according to this modification is formed so as to expose each evaluation pad 8 in the scribe region 3. Therefore, also in this modification example, the protective film 2 is formed on the scribe region 3 between the element formation regions 1A in the semiconductor wafer 1 except for the respective evaluation pads 8, so that the first embodiment The same effect as the form can be obtained.
　（第２の実施形態）
　以下、本発明の第２の実施形態に係る半導体装置について図６を参照しながら説明する。 (Second Embodiment)
A semiconductor device according to the second embodiment of the present invention will be described below with reference to FIG.
　図６（ａ）及び図６（ｂ）に示すように、第２の実施形態に係る半導体装置は、スクライブ領域３の上に形成する樹脂材からなる保護膜２をスクライブ領域３の中心線３ａに沿って形成し、且つその幅をダイシング用のブレード７の幅よりも小さい２０μｍ程度としている。また、図６（ｂ）に示すように、ブレード７の幅は、例えば３０μｍ～４０μｍ程度であり、スクライブ領域３の上の保護膜２の幅は、ダイシング工程により除去できるように設定している。 6A and 6B, in the semiconductor device according to the second embodiment, the protective film 2 made of a resin material formed on the scribe region 3 is placed on the center line 3a of the scribe region 3. And the width is about 20 μm, which is smaller than the width of the dicing blade 7. Further, as shown in FIG. 6B, the width of the blade 7 is, for example, about 30 μm to 40 μm, and the width of the protective film 2 on the scribe region 3 is set so that it can be removed by a dicing process. .
　一般に、樹脂材からなる保護膜２をダイシングすると、ブレード７の側面に樹脂材による目詰まりを起こしやすく、ブレード７の側面を頻繁に磨く必要がある。しかしながら、第２の実施形態においては、ブレード７の側面が保護膜７とは接触しないため、ブレード７の目詰まりが起こり難くなる。 Generally, when the protective film 2 made of a resin material is diced, the side surface of the blade 7 is likely to be clogged with the resin material, and the side surface of the blade 7 needs to be polished frequently. However, in the second embodiment, the blade 7 is not easily clogged because the side surface of the blade 7 does not contact the protective film 7.
　さらに、第１の実施形態と同様に、半導体ウエハ１におけるスクライブ領域３の上にも保護膜２を設けているため、裏面研削の際に、半導体ウエハ１の内側に配置された有効な素子形成領域１Ａには研削時の汚染された水が浸入することがない。 Further, since the protective film 2 is also provided on the scribe region 3 in the semiconductor wafer 1 as in the first embodiment, effective element formation arranged on the inner side of the semiconductor wafer 1 during back surface grinding is performed. The contaminated water during grinding does not enter the region 1A.
　（第２の実施形態の第１変形例）
　図７（ａ）及び図７（ｂ）に第２の実施形態の第１変形例を示す。図７（ａ）及び図７（ｂ）に示すように、第１変形例においては、半導体ウエハ１のスクライブ領域３の上に、ＴＥＧを含む素子形成領域１Ａの電気的特性を評価する評価用パッド８が選択的に設けられている。 (First Modification of Second Embodiment)
FIG. 7A and FIG. 7B show a first modification of the second embodiment. As shown in FIGS. 7A and 7B, in the first modified example, the evaluation is performed to evaluate the electrical characteristics of the element formation region 1A including the TEG on the scribe region 3 of the semiconductor wafer 1. A pad 8 is selectively provided.
　このような構成を持つ半導体ウエハ１に対して、第１変形例に係る樹脂材からなる保護膜２は、スクライブ領域３においては、各評価用パッド８の周囲を囲むように形成されてている。従って、第１変形例においても、半導体ウエハ１における素子形成領域１Ａ同士の間のスクライブ領域３の上には、保護膜２が連続して形成されるため、評価用パッド８が形成されていても、保護シート４と保護膜２との密着力が弱まることがない。 With respect to the semiconductor wafer 1 having such a configuration, the protective film 2 made of the resin material according to the first modification is formed so as to surround each evaluation pad 8 in the scribe region 3. . Accordingly, also in the first modified example, since the protective film 2 is continuously formed on the scribe region 3 between the element forming regions 1A in the semiconductor wafer 1, the evaluation pad 8 is formed. In addition, the adhesion between the protective sheet 4 and the protective film 2 is not weakened.
　また、スクライブ領域３の上に形成された保護膜２は、その大部分がスクライブ領域３の中心線３ａの上にブレード７の幅よりも狭く形成されており、半導体ウエハ１のダイシング時においては、ブレード７が評価用パッド８の周辺部でのみ保護膜２を切断する構成であるため、ブレード７にも目詰まりはほとんど生じることがない。従って、第２の実施形態と同様の効果を得ることができる。 Further, most of the protective film 2 formed on the scribe region 3 is formed on the center line 3a of the scribe region 3 so as to be narrower than the width of the blade 7, and when the semiconductor wafer 1 is diced. Since the blade 7 is configured to cut the protective film 2 only at the periphery of the evaluation pad 8, the blade 7 is hardly clogged. Therefore, the same effect as in the second embodiment can be obtained.
　（第２の実施形態の第２変形例）
　図８（ａ）及び図８（ｂ）に第２の実施形態の第２変形例を示す。図８（ａ）及び図８（ｂ）に示すように、第２変形例においては、スクライブ領域３の上に形成される保護膜２を、評価用パッド８の周囲を全て囲むのではなく、該評価用パッド８の中心線３ａに対して片側のみを囲むように形成している。 (Second modification of the second embodiment)
FIG. 8A and FIG. 8B show a second modification of the second embodiment. As shown in FIGS. 8A and 8B, in the second modification, the protective film 2 formed on the scribe region 3 is not surrounded by the entire periphery of the evaluation pad 8, It is formed so as to surround only one side with respect to the center line 3a of the evaluation pad 8.
　このようにすると、上記の第１変形例とほぼ同等の効果を得られる上に、スクライブ領域３の上の保護膜２が評価用パッド８の片側のみを囲む構成を採るため、スクライブ部領域３自体の幅を小さくすることができる。 In this way, an effect almost the same as that of the first modified example can be obtained, and the protective film 2 on the scribe region 3 surrounds only one side of the evaluation pad 8. The width of itself can be reduced.
　（第３の実施形態）
　以下、本発明の第３の実施形態に係る半導体装置について図９を参照しながら説明する。 (Third embodiment)
A semiconductor device according to the third embodiment of the present invention will be described below with reference to FIG.
　図９に示すように、第３の実施形態に係る半導体装置は、スクライブ領域３の上に形成する樹脂材からなる保護膜２を、スクライブ領域３の中心線３ａに沿って形成する第１の保護膜２Ａと、各素子形成領域１Ａの周囲をそれぞれ囲む第２の保護膜２Ｂとして形成している。従って、スクライブ領域３における評価用パッド８が形成されていない領域においては、該スクライブ領域３の中心線３ａ上の第１の保護膜２Ａと、各素子形成領域１Ａを囲む第２の保護膜２Ｂとの３本の線状の保護膜２Ａ、２Ｂが形成される。なお、評価用パッド８は、第１の保護膜２Ａと第２の保護膜２Ｂとによってその周囲が囲まれる。 As shown in FIG. 9, in the semiconductor device according to the third embodiment, the protective film 2 made of a resin material formed on the scribe region 3 is formed along the center line 3 a of the scribe region 3. The protective film 2A is formed as a second protective film 2B surrounding each element forming region 1A. Accordingly, in the region where the evaluation pad 8 is not formed in the scribe region 3, the first protective film 2A on the center line 3a of the scribe region 3 and the second protective film 2B surrounding each element forming region 1A. The three linear protective films 2A and 2B are formed. The periphery of the evaluation pad 8 is surrounded by the first protective film 2A and the second protective film 2B.
　このようにすると、第２の実施形態の第１変形例と比べて、スクライブ領域３における保護膜２Ａ、２Ｂの上面の面積が大きくなるため、裏面研削時における半導体ウエハ１の保護シート４と保護膜２Ａ、２Ｂとの密着性がより高くなるという効果を奏する。 In this case, since the area of the upper surface of the protective films 2A and 2B in the scribe region 3 is larger than that in the first modification of the second embodiment, the protective sheet 4 and the protective sheet 4 of the semiconductor wafer 1 are protected during back grinding. There exists an effect that adhesiveness with film | membrane 2A, 2B becomes higher.
　また、第２の実施形態と同様に、第１の保護膜２Ａの幅は２０μｍ程度であり、第２の保護膜２Ｂの幅は、１０μｍ～２０μｍ程度である。これにより、ダイシング用のブレード７が第２の保護膜２Ｂとは接触することがない。 Similarly to the second embodiment, the width of the first protective film 2A is about 20 μm, and the width of the second protective film 2B is about 10 μm to 20 μm. Thereby, the dicing blade 7 does not come into contact with the second protective film 2B.
　（第３の実施形態の第１変形例）
　図１０に第３の実施形態の第１変形例を示す。図１０に示すように、第１変形例においては、スクライブ領域３の上の第１の保護膜２Ａを設けずに、各素子形成領域１Ａを囲む第２の保護膜２Ｂのみを形成する構成としている。また、評価用パッド８の周囲は第２の保護膜２Ａによって囲むように形成している。さらに、スクライブ領域３の上において互いに平行に延びる第２の保護膜２Ｂ同士をこれらと交差する方向に接続する接続部２ａを設けている。 (First Modification of Third Embodiment)
FIG. 10 shows a first modification of the third embodiment. As shown in FIG. 10, in the first modification, only the second protective film 2 </ b> B surrounding each element formation region 1 </ b> A is formed without providing the first protective film 2 </ b> A on the scribe region 3. Yes. Further, the periphery of the evaluation pad 8 is formed so as to be surrounded by the second protective film 2A. Further, a connection portion 2a is provided on the scribe region 3 to connect the second protective films 2B extending in parallel with each other in a direction intersecting with the second protective films 2B.
　第１変形例によると、スクライブ領域３の上に形成された第２の保護膜２Ｂは、ダイシング用のブレード７との接触面積を大幅に低減できるため、ブレード７の目詰まりを大きく改善することができる。その上、スクライブ領域３の上に形成される第２の保護膜２Ｂ同士を接続部２ａによって局所的に接続することにより、半導体ウエハ１に裏面研削を行う際の研削屑を含む汚染された水がスクライブ領域３に浸入することを防止できる。 According to the first modification, the second protective film 2B formed on the scribe region 3 can greatly reduce the contact area with the dicing blade 7, so that the clogging of the blade 7 is greatly improved. Can do. In addition, the second protective film 2B formed on the scribe region 3 is locally connected by the connecting portion 2a, so that contaminated water containing grinding scraps when grinding the back surface of the semiconductor wafer 1 is performed. Can be prevented from entering the scribe region 3.
　（第３の実施形態の第２変形例）
　図１１に第３の実施形態の第２変形例を示す。図１１に示すように、第２変形例においては、スクライブ領域３の上に形成され、各素子形成領域１Ａを囲む第２の保護膜２Ｂを井桁状に交差するように形成している。従って、第２の保護膜２Ｂ同士の接続部２ａは、井桁状の交差部となる。 (Second modification of the third embodiment)
FIG. 11 shows a second modification of the third embodiment. As shown in FIG. 11, in the second modification, a second protective film 2B formed on the scribe region 3 and surrounding each element formation region 1A is formed so as to cross in a cross pattern. Accordingly, the connecting portion 2a between the second protective films 2B is a crossed cross-shaped portion.
　第２変形例においても、第１変形例と同様に、スクライブ領域３に研削時の汚染された水の浸入経路を断つ構成を有している。さらには、スクライブ領域３上において、第２の保護膜２Ｂにおけるブレード７による研削量を少なくすることができる。これにより、裏面研削時の水の浸入を防止できると共に、ブレード７の目詰まりを大幅に抑制することができる。 Also in the second modified example, similar to the first modified example, the scribe region 3 has a configuration in which the intrusion path of contaminated water during grinding is cut. Furthermore, the amount of grinding by the blade 7 in the second protective film 2B on the scribe region 3 can be reduced. As a result, water can be prevented from entering during back grinding, and clogging of the blade 7 can be significantly suppressed.
　本発明に係る半導体装置及びその製造方法は、半導体ウエハの裏面を研削する際に、スクライブ領域からの研削屑等の浸入を防止できることから、素子形成領域の表面の汚れを防ぐことができ、半導体ウエハの裏面が研削される半導体装置及びその製造方法等に有用である。 Since the semiconductor device and the manufacturing method thereof according to the present invention can prevent the intrusion of grinding debris and the like from the scribe region when grinding the back surface of the semiconductor wafer, the surface of the element forming region can be prevented from being contaminated. This is useful for a semiconductor device in which the back surface of a wafer is ground, a manufacturing method thereof, and the like.
１　　半導体ウエハ
１Ａ　素子形成領域
１ａ　シールリング
２　　保護膜
２Ａ　第１の保護膜
２Ｂ　第２の保護膜
２ａ　接続部
３　　スクライブ領域
３ａ　中心線
４　　保護シート
５　　ステージ
６　　切削部　
７　　ブレード
８　　評価用パッド DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1A Element formation area 1a Seal ring 2 Protective film 2A 1st protective film 2B 2nd protective film 2a Connection part 3 Scribe area 3a Center line 4 Protective sheet 5 Stage 6 Cutting part
7 Blade 8 Pad for evaluation

Claims (13)

  1. 　半導体基板に半導体素子が形成された素子形成領域と、
    　前記半導体基板における前記素子形成領域の周囲に形成されたスクライブ領域と、
    　前記素子形成領域の上及び前記スクライブ領域の上に形成され、前記素子形成領域及びスクライブ領域を保護する保護膜とを備えている半導体装置。     An element formation region in which a semiconductor element is formed on a semiconductor substrate;
    A scribe region formed around the element formation region in the semiconductor substrate;
    A semiconductor device comprising: a protective film formed on the element formation region and the scribe region, and protecting the element formation region and the scribe region.
  2. 　請求項１において、
    　前記保護膜は、樹脂材からなる半導体装置。     In claim 1,
    The protective film is a semiconductor device made of a resin material.
  3. 　請求項１又は２において、
    　前記各素子形成領域は、それぞれを囲むように形成された、導体からなるシールリングを有しており、
    　前記保護膜は、前記スクライブ領域の上における前記シールリングよりも外側の領域の全面に形成されている半導体装置。     In claim 1 or 2,
    Each of the element forming regions has a seal ring made of a conductor formed so as to surround each of the element forming regions,
    The said protective film is a semiconductor device currently formed in the whole surface of the area | region outside the said seal ring on the said scribe area | region.
  4. 　請求項１又は２において、
    　前記スクライブ領域の上に形成され、前記半導体素子を評価する評価用パッドをさらに備え、
    　前記保護膜は、前記スクライブ領域の上における前記評価用パッドを除く領域に形成されている半導体装置。     In claim 1 or 2,
    Further comprising an evaluation pad formed on the scribe region for evaluating the semiconductor element;
    The protective film is a semiconductor device formed in a region excluding the evaluation pad on the scribe region.
  5. 　請求項１又は２において、
    　前記保護膜は、前記スクライブ領域のうちの中央領域に所定の幅で形成されている半導体装置。     In claim 1 or 2,
    The protective film is a semiconductor device formed with a predetermined width in a central region of the scribe region.
  6. 　請求項５において、
    　前記保護膜における所定の幅は、前記半導体基板の切断幅よりも小さい半導体装置。     In claim 5,
    A semiconductor device in which the predetermined width in the protective film is smaller than the cutting width of the semiconductor substrate.
  7. 　請求項６において、
    　前記スクライブ領域の上に形成され、前記半導体素子を評価する評価用パッドをさらに備え、
    　前記保護膜は、前記評価用パッドの周囲の一部を囲むように形成されている半導体装置。     In claim 6,
    Further comprising an evaluation pad formed on the scribe region for evaluating the semiconductor element;
    The protective film is a semiconductor device formed so as to surround a part of the periphery of the evaluation pad.
  8. 　請求項１又は２において、
    　前記保護膜は、前記スクライブ領域の上に該スクライブ領域に沿って線状に形成されている半導体装置。     In claim 1 or 2,
    The protective film is a semiconductor device formed on the scribe region in a line along the scribe region.
  9. 　請求項８において、
    　前記スクライブ領域の上において、前記線状の保護膜は少なくとも２本に分けて形成されている半導体装置。     In claim 8,
    A semiconductor device in which the linear protective film is divided into at least two parts on the scribe region.
  10. 　請求項８において、
    　前記スクライブ領域の上において、前記線状の保護膜は、前記各素子形成領域をそれぞれ囲むように少なくとも２本で形成されている半導体装置。     In claim 8,
    On the scribe region, at least two of the linear protective films are formed so as to surround the element forming regions.
  11. 　半導体基板に半導体素子が形成された素子形成領域と、前記半導体基板における前記素子形成領域の周囲に形成されたスクライブ領域と、前記素子形成領域の上及び前記スクライブ領域の上に形成され、前記素子形成領域及びスクライブ領域を保護する保護膜とを有する半導体装置の製造方法であって、
    　ウエハ状態の半導体基板における前記保護膜の上の全面に、粘着性を有する保護テープを貼る工程と、
    　前記保護テープが貼られた前記半導体基板における前記保護テープと反対側の面を研削する工程と、
    　前記保護テープを前記半導体基板から剥がす工程とを備えている半導体装置の製造方法。     An element forming region in which a semiconductor element is formed on a semiconductor substrate; a scribe region formed around the element forming region in the semiconductor substrate; and the element forming region and the scribe region. A method of manufacturing a semiconductor device having a protective film that protects a formation region and a scribe region,
    A step of applying an adhesive protective tape to the entire surface of the semiconductor substrate in a wafer state on the protective film;
    Grinding the surface opposite to the protective tape in the semiconductor substrate to which the protective tape is affixed;
    And a step of peeling the protective tape from the semiconductor substrate.
  12. 　請求項１１において、
    　前記保護テープを前記半導体基板から剥がした後に、
    　前記スクライブ領域において、ウエハ状態の前記半導体基板を切断手段により前記保護膜を介して切断することにより、前記半導体基板を前記素子形成領域ごとに分割する工程をさらに備えている半導体装置の製造方法。     In claim 11,
    After peeling off the protective tape from the semiconductor substrate,
    A method of manufacturing a semiconductor device, further comprising: dividing the semiconductor substrate into the element formation regions by cutting the semiconductor substrate in a wafer state through the protective film by a cutting means in the scribe region.
  13. 　請求項１２において、
    　前記切断手段には、ブレード及びレーザ光のうちの少なくとも一方を用いる半導体装置の製造方法。     In claim 12,
    A semiconductor device manufacturing method using at least one of a blade and a laser beam as the cutting means.
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Citations (5)

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JPH03129855A (en) * 1989-10-16 1991-06-03 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JPH0456250A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor wafer
JPH05129430A (en) * 1991-11-06 1993-05-25 Matsushita Electric Ind Co Ltd Semiconductor device
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JPH03129855A (en) * 1989-10-16 1991-06-03 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JPH0456250A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor wafer
JPH05129430A (en) * 1991-11-06 1993-05-25 Matsushita Electric Ind Co Ltd Semiconductor device
JP2005285853A (en) * 2004-03-26 2005-10-13 Nec Electronics Corp Semiconductor wafer, manufacturing method thereof, and manufacturing method of semiconductor device
JP2006032482A (en) * 2004-07-13 2006-02-02 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device

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