JP6053256B2 - Semiconductor chip, manufacturing method thereof, and semiconductor device - Google Patents

Semiconductor chip, manufacturing method thereof, and semiconductor device Download PDF

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JP6053256B2
JP6053256B2 JP2011067968A JP2011067968A JP6053256B2 JP 6053256 B2 JP6053256 B2 JP 6053256B2 JP 2011067968 A JP2011067968 A JP 2011067968A JP 2011067968 A JP2011067968 A JP 2011067968A JP 6053256 B2 JP6053256 B2 JP 6053256B2
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semiconductor substrate
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JP2012204618A (en
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昭 井出
昭 井出
康司 鳥井
康司 鳥井
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PS4 Luxco SARL
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Description

本発明は、半導体チップ及びその製造方法、並びに半導体装置に関するものである。   The present invention relates to a semiconductor chip, a manufacturing method thereof, and a semiconductor device.

近年、半導体チップの集積度が年々向上し、それに伴ってチップサイズの大型化や、配線の微細化及び多層化などが進んでいる。一方、高密度実装化のためには、パッケージサイズの小型化及び薄型化が必要となっている。   In recent years, the degree of integration of semiconductor chips has improved year by year, and accordingly, the chip size has been increased, the wiring has been miniaturized, and the number of layers has been increased. On the other hand, for high-density mounting, it is necessary to reduce the package size and reduce the thickness.

このような要求に対して、ＭＣＰ（Multi Chip Package）と呼ばれる１つの配線基板の上に複数の半導体チップを高密度実装する技術が開発されている。その中でも、ＴＳＶ（Through Silicon Via）と呼ばれる貫通電極を有する半導体チップを積層したチップ積層体を配線基板の一面に実装したＣｏＣ（Chip on Chip）型の半導体パッケージ（半導体装置）が注目されている。   In response to such demands, a technology called high-density mounting of a plurality of semiconductor chips on a single wiring board called MCP (Multi Chip Package) has been developed. Among them, a CoC (Chip on Chip) type semiconductor package (semiconductor device) in which a chip stacked body in which semiconductor chips having through electrodes called TSV (Through Silicon Via) are stacked is mounted on one surface of the wiring substrate is attracting attention. .

特開２００６−１４０４０４号公報JP 2006-140404 A

ところで、上述のような貫通電極を有する半導体チップも１枚のウエハに複数製作され、ダイシンングによりチップ化される。かかるダイシング工程においては、チップの表面側や裏面側にチッピングが発生することがある。ここで、表面側へのチッピングに対しては対処が施されている場合も多く、また、貫通電極を有していなければ、裏面側へのチッピングも問題にならないものの、貫通電極を有する半導体チップについては、裏面側へのチッピングが、貫通電極が形成されている領域まで侵入してしまうと問題がある。
ここで、特許文献１は、半導体チップの表面側に、剥離防止用の溝が設けていることを開示しているが、貫通電極については全く関知しておらず、裏面側へのチッピングに対する対処については何ら開示していない。 By the way, a plurality of semiconductor chips having the through electrodes as described above are also manufactured on a single wafer and formed into chips by die-sinking. In such a dicing process, chipping may occur on the front side or the back side of the chip. Here, there are many cases where countermeasures are taken against chipping to the front surface side, and if there is no through electrode, chipping to the back surface is not a problem, but a semiconductor chip having a through electrode With respect to the above, there is a problem if the chipping to the back side penetrates to the region where the through electrode is formed.
Here, Patent Document 1 discloses that a groove for preventing peeling is provided on the front surface side of the semiconductor chip, but does not know about the through electrode at all and copes with chipping on the back surface side. Is not disclosed at all.

本発明の半導体チップは、表面側電極と裏面側電極とをつなぐ貫通電極が貫通する半導体基板を備えた半導体チップであって、前記半導体基板は、その裏面側周縁と前記貫通電極との間に溝が設けられていることを特徴とする。   The semiconductor chip of the present invention is a semiconductor chip provided with a semiconductor substrate through which a through electrode connecting a front surface side electrode and a back surface side electrode penetrates, and the semiconductor substrate is between the back surface side periphery and the through electrode. A groove is provided.

本発明の半導体チップによれば、ウエハからのダイシング工程で発生し得る裏面側のチッピングが、半導体チップのアクティブエリアに侵入することを防止することができる。
また、それに伴い、ダイシング後の裏面外観検査の歩留まりが改善する。
更に、半導体チップのスクライブエリアの縮小が可能となり、それによりチップサイズ全体の縮小化が図れ、ひいてはウエハ当たりの有効チップ数を増加させることができる。 According to the semiconductor chip of the present invention, it is possible to prevent the backside chipping that may occur in the dicing process from the wafer from entering the active area of the semiconductor chip.
Along with this, the yield of back surface appearance inspection after dicing is improved.
Furthermore, it is possible to reduce the scribe area of the semiconductor chip, thereby reducing the entire chip size, and consequently increasing the number of effective chips per wafer.

本発明の半導体チップにおける第一実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。It is the typical top view seen from the back surface side of the memory chip (DRAM) of 1st embodiment in the semiconductor chip of this invention. 図１のＡ−Ａ’における断面図である。It is sectional drawing in A-A 'of FIG. 裏面チッピング防止溝が、アクティブエリアへのチッピングの侵入を防止している様子を示す断面図である。It is sectional drawing which shows a mode that the back surface chipping prevention groove | channel prevents the penetration | invasion of the chipping to an active area. 第一実施形態に係るメモリチップ１Ａの製造方法の手順を示す流れ図である。It is a flowchart which shows the procedure of the manufacturing method of memory chip 1A which concerns on 1st embodiment. 半導体ウエハの平面図である。It is a top view of a semiconductor wafer. メモリチップを積層したチップ積層体を配線基板の一面に実装したＣｏＣ（Chip on Chip）型の半導体パッケージ（半導体装置）の断面図である。It is sectional drawing of the CoC (Chip on Chip) type semiconductor package (semiconductor device) which mounted the chip laminated body which laminated | stacked the memory chip on one surface of the wiring board. 本発明の半導体チップにおける第二実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。It is the typical top view seen from the back surface side of the memory chip (DRAM) of 2nd embodiment in the semiconductor chip of this invention. 本発明の半導体チップにおける第三実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。It is the typical top view seen from the back surface side of the memory chip (DRAM) of 3rd embodiment in the semiconductor chip of this invention. 本発明の半導体チップにおける第四実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。It is the typical top view seen from the back surface side of the memory chip (DRAM) of 4th embodiment in the semiconductor chip of this invention. 本発明の半導体チップにおける第五実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。It is the typical top view seen from the back surface side of the memory chip (DRAM) of 5th embodiment in the semiconductor chip of this invention. 本発明の半導体チップにおける第六実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。It is the typical top view seen from the back surface side of the memory chip (DRAM) of 6th embodiment in the semiconductor chip of this invention. 本発明の半導体チップにおける第七実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。It is the typical top view seen from the back surface side of the memory chip (DRAM) of 7th embodiment in the semiconductor chip of this invention. 本発明の半導体チップにおける第八実施形態のメモリチップ（ＤＲＡＭ）の断面図である。It is sectional drawing of the memory chip (DRAM) of 8th embodiment in the semiconductor chip of this invention. 本発明の半導体チップにおける第八実施形態のメモリチップ（ＤＲＡＭ）の溝の開口パターンを説明するための図である。It is a figure for demonstrating the opening pattern of the groove | channel of the memory chip (DRAM) of 8th embodiment in the semiconductor chip of this invention.

以下、図面を参照して、本発明の実施の形態について詳細に説明する。
＜第一実施形態＞
図１は、本発明の半導体チップにおける第一実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。図２は、図１のＡ−Ａ’における断面図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First embodiment>
FIG. 1 is a schematic plan view seen from the back side of the memory chip (DRAM) of the first embodiment of the semiconductor chip of the present invention. 2 is a cross-sectional view taken along line AA ′ of FIG.

図１に示すメモリチップ１Ａの裏面側においては、長手方向に沿ってその中央領域に、通常動作時に信号、電源等を伝送するための複数の貫通電極２ｂ（第一貫通電極）を備えている。一方、チップの周縁部には、サポート貫通電極２ａ（第二貫通電極）が設けられており、このサポート貫通電極２ａに接続される裏面バンプ電極は、チップを積層する際に、チップ間の間隔を確保するためのサポートバンプとして使用されることになる。サポート貫通電極２ａは、通常動作時においては、フローティング状態、あるいは電源もしくはＧＮＤレベルになっている。   On the back surface side of the memory chip 1A shown in FIG. 1, a plurality of through-electrodes 2b (first through-electrodes) for transmitting signals, power supplies, etc. during normal operation are provided in the central region along the longitudinal direction. . On the other hand, support penetrating electrodes 2a (second penetrating electrodes) are provided at the peripheral edge of the chip, and the back bump electrode connected to the support penetrating electrode 2a has a gap between the chips when the chips are stacked. It will be used as a support bump to secure The support through electrode 2a is in a floating state, a power source or a GND level during normal operation.

更に、チップの裏面周縁とサポート貫通電極２ａとの間には、裏面チッピング防止溝５Ａが設けられている。この裏面チッピング防止溝５Ａによって、チッピングがサポート貫通電極２ａ及び信号等用貫通電極２ｂが形成されている領域に侵入することを防ぐことができる。   Further, a back surface chipping prevention groove 5A is provided between the back surface periphery of the chip and the support through electrode 2a. This back surface chipping prevention groove 5A can prevent chipping from entering the region where the support through electrode 2a and the signal through electrode 2b are formed.

また、図２において、メモリチップ１Ａは、半導体基板１０と、その表側に積層された第１、第２、第３、第４層間絶縁膜１１，１２，１３，１４と、第４層間絶縁膜１４上に積層されたポリイミド（ＰＩ）膜（パッシベーション膜）１５と、半導体基板１０の裏面に積層されたパッシベーション層１６とを有している。   2, the memory chip 1A includes a semiconductor substrate 10, first, second, third, and fourth interlayer insulating films 11, 12, 13, and 14 stacked on the front side, and a fourth interlayer insulating film. 14 has a polyimide (PI) film (passivation film) 15 stacked on the semiconductor substrate 14 and a passivation layer 16 stacked on the back surface of the semiconductor substrate 10.

また、メモリチップ１Ａは、後述するスクライブセンターＳＣ側から、スクライブエリアＳＡ、ガードリングエリアＧＡ、及びアクティブエリアＡＡという領域に区分けされる。   The memory chip 1A is divided into areas called a scribe area SA, a guard ring area GA, and an active area AA from the scribe center SC side described later.

アクティブエリアＡＡのＰＩ膜１５の開口部においては、サポート貫通電極２ａが設けられている。サポート貫通電極２ａは、半導体基板１０を貫通する貫通孔部（ＴＳＶ：Through Silicon Via）２１と、第１、第２、第３、第４層間絶縁膜１１，１２，１３，１４でそれぞれ隔てられる配線２２ａ〜２２ｄと、その配線２２ａ〜２２ｄを縦続的に接続するコンタクトプラグ２３ａ〜２３ｃと、ＰＩ膜１５の開口部から露呈したピラー部２４と、そのピラー部２４の上面に設けられた表面バンプ電極２５と、貫通孔部２１の半導体基板１０の裏面側に露呈した部分に設けられた裏面バンプ電極２６とを備えている。   A support through electrode 2a is provided in the opening of the PI film 15 in the active area AA. The support through electrode 2a is separated from a through hole portion (TSV: Through Silicon Via) 21 penetrating the semiconductor substrate 10 by first, second, third, and fourth interlayer insulating films 11, 12, 13, and 14, respectively. Wirings 22a to 22d, contact plugs 23a to 23c for connecting the wirings 22a to 22d in cascade, a pillar portion 24 exposed from the opening of the PI film 15, and a surface bump provided on the upper surface of the pillar portion 24 The electrode 25 and the back surface bump electrode 26 provided in the part exposed to the back surface side of the semiconductor substrate 10 of the through-hole part 21 are provided.

また、半導体基板１０の貫通孔部２１の近傍には、トレンチ・アイソレーション（ＴＩ：Trench Isolation）１０１が設けられている。   In addition, a trench isolation (TI) 101 is provided in the vicinity of the through hole portion 21 of the semiconductor substrate 10.

スクライブエリアＳＡの層間絶縁膜内には、メモリチップ１Ａの表面側のチッピングを防止するための第１、第２クラックストップ３ａ，３ｂが設けられている。   In the interlayer insulating film of the scribe area SA, first and second crack stops 3a and 3b for preventing chipping on the surface side of the memory chip 1A are provided.

ガードリングエリアＧＡの表面側には、ガードリング（シールリング）４が設けられている。このガードリング４は、水分等の浸入を防ぐ役割を有する。一方、ガードリングエリアＧＡの半導体基板１０側、つまりメモリチップ１Ａの裏面側には、裏面側のチッピングを防止するための溝５Ａが設けられている。   A guard ring (seal ring) 4 is provided on the surface side of the guard ring area GA. The guard ring 4 has a role of preventing moisture and the like from entering. On the other hand, a groove 5A for preventing chipping on the back surface side is provided on the semiconductor substrate 10 side of the guard ring area GA, that is, on the back surface side of the memory chip 1A.

図３は、裏面チッピング防止溝５Ａが、アクティブエリアＡＡへのチッピングの侵入を防止している様子を示す断面図である。   FIG. 3 is a cross-sectional view showing that the back surface chipping prevention groove 5A prevents the chipping from entering the active area AA.

図３において、ダイシングブレード９９によりスクライブセンターＳＣに沿ってダイシングが行われると、表面チッピングＦＣ及び裏面チッピングＢＣが生じるおそれがあるが、表面チッピングＦＣは、第１、第２クラックストップ３ａ，３ｂにより侵入が阻止され、裏面チッピングＢＣは、裏面チッピング防止溝５Ａにより侵入が阻止される。なお、裏面チッピングＢＣの形状はくさび形なので、ガードリングエリアＧＡに設ける裏面チッピング防止溝５Ａは、貫通孔部２１ほど深く形成する必要はない。また、図３は、図２を更に拡大している図面であるため、サポート貫通電極２ａは省略されている。   In FIG. 3, when dicing is performed along the scribe center SC by the dicing blade 99, the front surface chipping FC and the back surface chipping BC may occur. However, the front surface chipping FC is caused by the first and second crack stops 3a and 3b. Intrusion is blocked, and the back surface chipping BC is blocked by the back surface chipping prevention groove 5A. Since the back surface chipping BC has a wedge shape, the back surface chipping prevention groove 5A provided in the guard ring area GA does not need to be formed as deep as the through-hole portion 21. FIG. 3 is a further enlarged view of FIG. 2, and thus the support through electrode 2 a is omitted.

次に、図１及び図２に示した第一実施形態に係るメモリチップ１Ａの製造方法について説明する。図４は、第一実施形態に係るメモリチップ１Ａの製造方法の手順を示す流れ図である。なお、図４に各ステップとして示された工程はすべてウエハ１００上で行われる。更に、図４に示した製造方法の手順は、表面バンプ電極形成までの配線工程が完了した後の手順を示している。   Next, a method for manufacturing the memory chip 1A according to the first embodiment shown in FIGS. 1 and 2 will be described. FIG. 4 is a flowchart showing the procedure of the method for manufacturing the memory chip 1A according to the first embodiment. Note that all the processes shown as the steps in FIG. 4 are performed on the wafer 100. Furthermore, the procedure of the manufacturing method shown in FIG. 4 shows the procedure after the wiring process up to the formation of the surface bump electrode is completed.

具体的には、まず、ウエハ１００の表面が加工され（Ｓ１０１）、その外周が研削される（Ｓ１０２）。次に、表面に接着剤が塗布され（Ｓ１０３）、ＳｉＯ２などで形成された支持体（Wafer Support System; WSS）が貼り付けられる（Ｓ１０４）。なお、接着剤としては、紫外線などでウエハから剥離可能なものを用いる。次に、裏面を研削して５０〜２０ｕｍ程度まで薄くし（Ｓ１０５）、金属汚染防止のためＳｉ３Ｎ４などの窒化膜を成長させる（Ｓ１０６）。 Specifically, first, the surface of the wafer 100 is processed (S101), and the outer periphery thereof is ground (S102). Next, adhesive is applied to the surface (S103), a support body formed like SiO 2 (Wafer Support System; WSS ) is adhered (S104). As the adhesive, an adhesive that can be peeled off from the wafer by ultraviolet rays or the like is used. Next, the back surface is ground and thinned to about 50 to 20 μm (S105), and a nitride film such as Si 3 N 4 is grown to prevent metal contamination (S106).

次に、裏面にフォトレジストを塗布し（Ｓ１０７）、裏面チッピング防止溝５Ａのパターンを露光・現像し（Ｓ１０８）、浅溝エッチ（Ｓ１０９）の各工程を経て、裏面チッピング防止溝５Ａを形成する。そして、ステップＳ１０７において塗布したフォトレジストを除去し（Ｓ１１０）、再度、窒化膜を成長させる（Ｓ１１１）。   Next, a photoresist is applied to the back surface (S107), the pattern of the back surface chipping prevention groove 5A is exposed and developed (S108), and the back surface chipping prevention groove 5A is formed through each step of shallow groove etching (S109). . Then, the photoresist applied in step S107 is removed (S110), and a nitride film is grown again (S111).

次に、フォトレジストを塗布し（Ｓ１１２）、貫通電極２ａ，２ｂの貫通孔のパターンを露光・現像し（Ｓ１１３）、貫通孔エッチ（Ｓ１１４）の各工程を経て、貫通孔部２１を形成する。そして、ステップＳ１１２において塗布したフォトレジストを除去し（Ｓ１１５）、Ｔｉ／Ｃｕなどのシード膜をスパッタなどで形成する（Ｓ１１６）。   Next, a photoresist is applied (S112), the pattern of the through holes of the through electrodes 2a and 2b is exposed and developed (S113), and through hole etching (S114) is performed to form the through hole 21. . Then, the photoresist applied in step S112 is removed (S115), and a seed film such as Ti / Cu is formed by sputtering or the like (S116).

次に、裏面バンプ電極２６を形成するため、フォトレジストを塗布し（Ｓ１１７）、露光・現像（Ｓ１１８）の後、銅（Ｃｕ）をメッキして、貫通孔部２１を充填する（Ｓ１１９）。   Next, in order to form the back surface bump electrode 26, a photoresist is applied (S117), and after exposure and development (S118), copper (Cu) is plated to fill the through-hole portion 21 (S119).

次に、裏面バンプ電極２６として、電極材（例えばＳｎＡｇ）、をメッキする（Ｓ１２０）。最後に、ステップＳ１１７において塗布したフォトレジストを除去し（Ｓ１２１）、ステップＳ１１６においてスパッタ形成したシード膜をウェットエッチ等で除去する（Ｓ１２２）。最後に、図示しないが、支持体から紫外線等でデマウントする。   Next, an electrode material (for example, SnAg) is plated as the back bump electrode 26 (S120). Finally, the photoresist applied in step S117 is removed (S121), and the seed film formed by sputtering in step S116 is removed by wet etching or the like (S122). Finally, although not shown, the substrate is demounted with ultraviolet rays or the like.

上述のような工程を経て、図５に示すような、複数のメモリチップ１Ａを含むウエハ１００が完成する。その後、スクライブセンターＳＣに沿ってチップごとに切断されることにより、複数の各メモリチップ１Ａが完成する。   Through the steps as described above, a wafer 100 including a plurality of memory chips 1A as shown in FIG. 5 is completed. Then, each memory chip 1A is completed by cutting for each chip along the scribe center SC.

次に、上述のように作製されたメモリチップ１Ａを積層したチップ積層体を配線基板の一面に実装したＣｏＣ（Chip on Chip）型の半導体パッケージ（半導体装置）について、図６を参照して説明する。   Next, a CoC (Chip on Chip) type semiconductor package (semiconductor device) in which a chip stack including the memory chips 1A manufactured as described above is mounted on one surface of a wiring board will be described with reference to FIG. To do.

具体的には、半導体パッケージは、略四角形で所定の配線が形成された配線基板６を有している。この配線基板６は、例えば０．２ｍｍ厚のガラスエポキシ基板であり、絶縁基材６１の両面に所定の配線が形成され、その配線は部分的に絶縁膜６２、例えばソルダーレジスト、で覆われている。また、配線基板６の一面の中央領域には開口部が形成されており、絶縁膜（ソルダーレジスト）６２の開口部から露出された部位には、複数の接続パッド６３が形成されている。一方、配線基板６の他面の配線の絶縁膜６２から露出された部位には、複数のランド６４が形成されている。ここで、接続パッド６３と、これに対応するランド６４とは、配線基板６の配線によりそれぞれ電気的に接続されている。   Specifically, the semiconductor package has a wiring substrate 6 that is substantially square and has predetermined wiring formed thereon. The wiring substrate 6 is a glass epoxy substrate having a thickness of 0.2 mm, for example, and predetermined wiring is formed on both surfaces of the insulating base 61, and the wiring is partially covered with an insulating film 62, for example, a solder resist. Yes. In addition, an opening is formed in the central region of one surface of the wiring substrate 6, and a plurality of connection pads 63 are formed in a portion exposed from the opening of the insulating film (solder resist) 62. On the other hand, a plurality of lands 64 are formed in a portion exposed from the insulating film 62 of the wiring on the other surface of the wiring substrate 6. Here, the connection pads 63 and the lands 64 corresponding to the connection pads 63 are electrically connected to each other by the wiring of the wiring board 6.

また、配線基板６の一面には、チップ積層体が搭載されている。チップ積層体は、例えば略四角形の板状で、一面に所定の回路が形成された半導体チップが、複数個、積層された構成となっている。図６に示した半導体パッケージにおいては、例えばメモリ回路が形成された８つのメモリチップ１Ａａ〜１Ａｈと、メモリチップ１Ａと配線基板６とのインターフェースを取るためのインターフェースチップ７を９段積層したものである。それぞれの半導体チップは、例えば５０μｍ厚で構成されており、前述のように、複数の表面バンプ電極２５と、他面側の中央領域に複数の裏面バンプ電極２６が形成されている。表面バンプ電極２５とこれに対応する裏面バンプ電極２６とは貫通電極２により電気的に接続されている。なお、図１乃至図５に基づいた説明においては、半導体チップをメモリチップ１Ａとして説明したが、インターフェースチップ７でも、ウエハは異なるものの同様の裏面チッピング防止溝５Ａを有している。   In addition, a chip stack is mounted on one surface of the wiring board 6. The chip stack has a configuration in which a plurality of semiconductor chips each having a predetermined circuit formed on one surface are stacked, for example, in a substantially rectangular plate shape. In the semiconductor package shown in FIG. 6, for example, eight memory chips 1Aa to 1Ah on which memory circuits are formed, and nine interface chips 7 for interfacing between the memory chip 1A and the wiring board 6 are stacked. is there. Each semiconductor chip has a thickness of 50 μm, for example, and as described above, a plurality of front surface bump electrodes 25 and a plurality of back surface bump electrodes 26 are formed in the central region on the other surface side. The front bump electrode 25 and the corresponding back bump electrode 26 are electrically connected by the through electrode 2. In the description based on FIGS. 1 to 5, the semiconductor chip is described as the memory chip 1 </ b> A. However, the interface chip 7 also has the same back surface chipping prevention groove 5 </ b> A although the wafer is different.

また、最上層のメモリチップ１Ａａの上面はＮＣＦ（Non-conductive Film）８３及びリードフレーム８４によって覆われている。また、チップ積層体には、例えばアンダーフィル材からなる第１の封止樹脂部８１が形成されている。この封止樹脂部８１は、それぞれの半導体チップの間の隙間を充填すると共に、チップ積層体の両側にテーパ状に形成されている。また、配線基板６の一面上には、チップ積層体を覆うように第２の封止樹脂層８２が形成されている。   The upper surface of the uppermost memory chip 1 </ b> Aa is covered with an NCF (Non-conductive Film) 83 and a lead frame 84. In addition, a first sealing resin portion 81 made of, for example, an underfill material is formed on the chip stack. The sealing resin portion 81 fills the gaps between the respective semiconductor chips and is formed in a tapered shape on both sides of the chip stack. A second sealing resin layer 82 is formed on one surface of the wiring board 6 so as to cover the chip stack.

更に、チップ積層体の最下の半導体チップの一面（図６における下側の面）の表面バンプ電極２５は、ワイヤバンプを介して、配線基板６の接続パッド６３に接続されている。   Further, the surface bump electrode 25 on one surface (the lower surface in FIG. 6) of the lowermost semiconductor chip of the chip stack is connected to the connection pad 63 of the wiring substrate 6 through a wire bump.

また、配線基板６の他面の複数のランド６４には、半導体パッケージの外部端子となる半田ボール８５がそれぞれ搭載されており、外部端子は所定の間隔で格子状に配置されている。   In addition, solder balls 85 serving as external terminals of the semiconductor package are mounted on the plurality of lands 64 on the other surface of the wiring board 6, and the external terminals are arranged in a grid at predetermined intervals.

以上のように第一実施形態におけるメモリチップ１Ａにおいては、裏面側のガードリングエリアＧＡに裏面チッピング防止溝５Ａを設けているので、ダイシング工程で発生し得る裏面側のチッピングが、アクティブエリアＡＡに侵入することを防止することができる。また、それに伴い、ダイシング後の裏面外観検査の歩留まりが改善する。更に、スクライブエリアＳＡの縮小が可能となり、それによりチップサイズ全体の縮小化が図れ、ひいてはウエハ当たりの有効チップ数を増加させることができる。   As described above, in the memory chip 1A according to the first embodiment, the back surface chipping prevention groove 5A is provided in the back surface side guard ring area GA, so that back surface chipping that may occur in the dicing process is caused in the active area AA. Intrusion can be prevented. Along with this, the yield of back surface appearance inspection after dicing is improved. Further, the scribe area SA can be reduced, whereby the entire chip size can be reduced, and the number of effective chips per wafer can be increased.

＜第二実施形態＞
次に、本発明の半導体チップにおける第二実施形態のメモリチップ（ＤＲＡＭ）について説明する。図７は、本発明の半導体チップにおける第二実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。 <Second embodiment>
Next, the memory chip (DRAM) of the second embodiment of the semiconductor chip of the present invention will be described. FIG. 7 is a schematic plan view seen from the back side of the memory chip (DRAM) of the second embodiment in the semiconductor chip of the present invention.

第一実施形態のメモリチップ１Ａにおいては、図１に示すように、裏面チッピング防止溝５Ａは、サポート貫通電極２ａを囲む閉曲線として形成されているが、本第二実施形態のメモリチップ１Ｂにおいては、図７に示すように、断続的な裏面チッピング防止溝５Ｂが設けられていることが特徴である。   In the memory chip 1A of the first embodiment, as shown in FIG. 1, the back surface chipping prevention groove 5A is formed as a closed curve surrounding the support through electrode 2a. In the memory chip 1B of the second embodiment, As shown in FIG. 7, an intermittent back surface chipping prevention groove 5B is provided.

貫通電極２は、第一実施形態のチップの製造方法で示したように、シード膜を用いる電気めっきによって形成されることがある。このような場合、図１に示した第一実施形態のようにチップ周縁を全て溝で囲んでしまうと、溝部におけるシード膜のカバレッジが悪いため、シード膜が溝部において断線してしまい、電気めっきの際に必要となる電流をチップの内部に流すことができないことがある。そこで、溝を断続的に設けることによって、チップ周縁部に、溝が形成されていない部分、つまり、溝と溝との間にある平坦部分が残されることになり、溝部においてシード膜のカバレッジが悪くても、平坦部分においてはシード膜が確実に形成されることになるため、電気めっきをする際に平坦部分のシード膜を介してチップ内部の貫通孔部まで電流を流すことができるものである。また、補足的な理由としては、溝によるチップの抗折強度の低下を抑制するということがある。   The through electrode 2 may be formed by electroplating using a seed film as shown in the chip manufacturing method of the first embodiment. In such a case, if the entire periphery of the chip is surrounded by a groove as in the first embodiment shown in FIG. 1, the seed film is broken in the groove because the seed film has poor coverage in the groove, and electroplating is performed. In some cases, it may not be possible to flow the current required for the chip into the chip. Therefore, by intermittently providing the groove, a portion where the groove is not formed, that is, a flat portion between the grooves is left on the peripheral edge portion of the chip, and the coverage of the seed film in the groove portion is left. Even if it is bad, since the seed film is surely formed in the flat part, current can flow to the through hole inside the chip through the seed film in the flat part when electroplating. is there. As a supplementary reason, it is possible to suppress a decrease in the bending strength of the chip due to the groove.

なお、チップの他の構成、チップの製造方法、及び、チップを含む半導体パッケージの構成は、第一実施形態と同様である。   The other configuration of the chip, the manufacturing method of the chip, and the configuration of the semiconductor package including the chip are the same as those in the first embodiment.

＜第三実施形態＞
次に、本発明の半導体チップにおける第三実施形態のメモリチップ（ＤＲＡＭ）について説明する。図８は、本発明の半導体チップにおける第三実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。 <Third embodiment>
Next, a memory chip (DRAM) according to a third embodiment of the semiconductor chip of the present invention will be described. FIG. 8 is a schematic plan view seen from the back side of the memory chip (DRAM) of the third embodiment of the semiconductor chip of the present invention.

本第三実施形態のメモリチップ１Ｃにおいては、図８に示すように、対角に位置する対のチップコーナー部のそれぞれに、浅い溝でフリップチップボンダーの認識マーク９１を設けている。この認識マーク９１により、図６に示した半導体パッケージにおけるチップ積層体の正確な形成が可能となる。図８においては、Ｌ字型の認識マーク９１を例として示しているが、これに限られることはなく、ＦＣボンダーが認識可能であれば、他の形状、例えば十字形状、正方形等であってもよい。   In the memory chip 1 </ b> C of the third embodiment, as shown in FIG. 8, flip chip bonder recognition marks 91 are provided with shallow grooves at each of a pair of chip corners located diagonally. This recognition mark 91 enables accurate formation of the chip stack in the semiconductor package shown in FIG. In FIG. 8, an L-shaped recognition mark 91 is shown as an example. However, the present invention is not limited to this, and other shapes such as a cross shape, a square, etc. may be used as long as the FC bonder can be recognized. Also good.

なお、チップの他の構成、チップの製造方法、及び、チップを含む半導体パッケージの構成は、第一実施形態と同様である。   The other configuration of the chip, the manufacturing method of the chip, and the configuration of the semiconductor package including the chip are the same as those in the first embodiment.

また、図８では、第二実施形態で示した裏面チッピング防止溝５Ｂに認識マーク９１を設けた場合を示したが、認識マークを設けるのは、第一実施形態で示した溝であってもよいし、後述の各実施形態の溝であってもよい。   FIG. 8 shows the case where the recognition mark 91 is provided in the back surface chipping prevention groove 5B shown in the second embodiment. However, the recognition mark may be provided even in the groove shown in the first embodiment. It may be a groove of each embodiment described later.

＜第四実施形態＞
次に、本発明の半導体チップにおける第四実施形態のメモリチップ（ＤＲＡＭ）について説明する。図９は、本発明の半導体チップにおける第四実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。 <Fourth embodiment>
Next, a memory chip (DRAM) according to a fourth embodiment of the semiconductor chip of the present invention will be described. FIG. 9 is a schematic plan view seen from the back side of the memory chip (DRAM) of the fourth embodiment of the semiconductor chip of the present invention.

本第四実施形態に係るメモリチップ１Ｄおいては、図７の第二実施形態のメモリチップ１Ｂの断続的な裏面チッピング防止溝５Ｂに対して、更に、内側に断続的な溝を設けて、全体として裏面チッピング防止溝５Ｃを形成している。このとき、内側の溝と外側の溝において、それぞれの欠落部が重ならないように構成することが重要である。このように形成することにより、第二実施形態の構成における効果、すなわち、確実に電流を流すこと、と、欠落部から裏面チッピングが内部に侵入することを防止する、という二重の効果が期待できる。   In the memory chip 1D according to the fourth embodiment, an intermittent groove is further provided on the inner side of the intermittent back surface chipping prevention groove 5B of the memory chip 1B of the second embodiment of FIG. As a whole, the back surface chipping preventing groove 5C is formed. At this time, it is important to configure the inner groove and the outer groove so that the respective missing portions do not overlap. By forming in this way, the effect of the configuration of the second embodiment, that is, the double effect of reliably flowing current and preventing the backside chipping from entering the inside from the missing part is expected. it can.

なお、チップの他の構成、チップの製造方法、及び、チップを含む半導体パッケージの構成は、第一実施形態と同様である。   The other configuration of the chip, the manufacturing method of the chip, and the configuration of the semiconductor package including the chip are the same as those in the first embodiment.

＜第五実施形態＞
次に、本発明の半導体チップにおける第五実施形態のメモリチップ（ＤＲＡＭ）について説明する。図１０は、本発明の半導体チップにおける第五実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。 <Fifth embodiment>
Next, a memory chip (DRAM) according to a fifth embodiment of the semiconductor chip of the present invention will be described. FIG. 10 is a schematic plan view seen from the back side of the memory chip (DRAM) of the fifth embodiment in the semiconductor chip of the present invention.

第一実施形態のメモリチップ１Ａにおいては、図１に示すように、チップ周縁の全周に渡って溝が形成されているが、本第五実施形態に係るメモリチップ１Ｅにおいては、サポート貫通電極２ａが形成されている部分の、チップ周縁とそのサポート貫通電極２ａの間にのみ裏面チッピング防止溝５Ｄを設けている。   In the memory chip 1A of the first embodiment, as shown in FIG. 1, a groove is formed over the entire periphery of the chip periphery. However, in the memory chip 1E according to the fifth embodiment, the support through electrode The back surface chipping prevention groove 5D is provided only between the chip periphery and the support through electrode 2a in the portion where 2a is formed.

かかる構成により第二実施形態と同様、シード膜のカバレッジの問題を回避できると共に強度も保障できる。なお、溝がない部分においては、長い裏面チッピングがチップ内部に侵攻する可能性があるが、その部分には保護すべき構造体がないので、問題にはならない。   With this configuration, as in the second embodiment, the problem of seed film coverage can be avoided and the strength can be ensured. It should be noted that in a portion where there is no groove, there is a possibility that a long back surface chipping may invade the inside of the chip. However, since there is no structure to be protected in that portion, there is no problem.

なお、チップの他の構成、チップの製造方法、及び、チップを含む半導体パッケージの構成は、第一実施形態と同様である。   The other configuration of the chip, the manufacturing method of the chip, and the configuration of the semiconductor package including the chip are the same as those in the first embodiment.

＜第六実施形態＞
次に、本発明の半導体チップにおける第六実施形態のメモリチップ（ＤＲＡＭ）について説明する。図１１は、本発明の半導体チップにおける第六実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。 <Sixth embodiment>
Next, a memory chip (DRAM) according to a sixth embodiment of the semiconductor chip of the present invention will be described. FIG. 11 is a schematic plan view seen from the back side of the memory chip (DRAM) of the sixth embodiment in the semiconductor chip of the present invention.

本第六実施形態に係るメモリチップ１Ｆは、第五実施形態と第二実施形態の溝を組み合わせた裏面チッピング防止溝５Ｅを設けた態様である。   The memory chip 1F according to the sixth embodiment is a mode in which a back surface chipping prevention groove 5E, which is a combination of the grooves of the fifth embodiment and the second embodiment, is provided.

なお、チップの他の構成、チップの製造方法、及び、チップを含む半導体パッケージの構成は、第一実施形態と同様である。   The other configuration of the chip, the manufacturing method of the chip, and the configuration of the semiconductor package including the chip are the same as those in the first embodiment.

＜第七実施形態＞
次に、本発明の半導体チップにおける第七実施形態のメモリチップ（ＤＲＡＭ）について説明する。図１２は、本発明の半導体チップにおける第七実施形態のメモリチップ（ＤＲＡＭ）の裏面側からみた模式的平面図である。 <Seventh embodiment>
Next, a memory chip (DRAM) according to a seventh embodiment of the semiconductor chip of the present invention will be described. FIG. 12 is a schematic plan view seen from the back side of the memory chip (DRAM) of the seventh embodiment in the semiconductor chip of the present invention.

本第七実施形態に係るメモリチップ１Ｇは、第五実施形態と第四実施形態の溝を組み合わせた裏面チッピング防止溝５Ｆを設けた態様である。   The memory chip 1G according to the seventh embodiment is a mode in which a back surface chipping prevention groove 5F, which is a combination of the grooves of the fifth embodiment and the fourth embodiment, is provided.

なお、チップの他の構成、チップの製造方法、及び、チップを含む半導体パッケージの構成は、第一実施形態と同様である。   The other configuration of the chip, the manufacturing method of the chip, and the configuration of the semiconductor package including the chip are the same as those in the first embodiment.

＜第八実施形態＞
次に、本発明の半導体チップにおける第七実施形態のメモリチップ（ＤＲＡＭ）について説明する。図１３及び図１４は、本発明の半導体チップにおける第八実施形態のメモリチップ（ＤＲＡＭ）を説明するための図である。 <Eighth embodiment>
Next, a memory chip (DRAM) according to a seventh embodiment of the semiconductor chip of the present invention will be described. 13 and 14 are views for explaining a memory chip (DRAM) according to an eighth embodiment of the semiconductor chip of the present invention.

図４に示した、第一実施形態に係るメモリチップを製造する方法によれば、マスクを１枚追加することとなり、工程数が増加するという問題がある（ステップＳ１０７〜ステップＳ１１１）。この工程数の増加という欠点に対処する方法としては、貫通孔部２１のドライエッチ工程において、同時に裏面チッピング防止溝を形成するという方法がある。しかしながら、かかる方法で作製するには以下のように若干の工夫を要する。つまり、貫通孔部２１は、半導体基板１０を貫通するような深い穴を形成する工程であるので、裏面チッピング防止溝において、貫通孔部と同様の大きさの開口を有するように形成すると、不要に深い溝となり、工程中でのウエハの破損の危険性がある。   According to the method of manufacturing the memory chip according to the first embodiment shown in FIG. 4, there is a problem that one mask is added and the number of processes increases (steps S <b> 107 to S <b> 111). As a method for dealing with the drawback of the increase in the number of steps, there is a method in which a back surface chipping preventing groove is formed at the same time in the dry etching step of the through-hole portion 21. However, in order to produce by this method, some ideas are required as follows. That is, since the through-hole portion 21 is a step of forming a deep hole that penetrates the semiconductor substrate 10, it is unnecessary to form the back surface chipping prevention groove so as to have an opening having the same size as the through-hole portion. There is a risk of damage to the wafer during the process.

かかる観点から、貫通孔部２１のドライエッチ工程において、同時に裏面チッピング防止溝を形成するという方法においては、図１３に示すように、裏面チッピング防止溝５Ｇに対応する、レジスト１７の開口をドット形状とし、またその面積を、貫通孔部２１に対応するそれよりも小さく形成する。これにより、マイクロローディング効果により、裏面チッピング防止溝５Ｇは、貫通孔部２１よりも浅いものとなる。   From this point of view, in the method of forming the back surface chipping prevention groove at the same time in the dry etching process of the through-hole portion 21, the opening of the resist 17 corresponding to the back surface chipping prevention groove 5G is formed in a dot shape as shown in FIG. In addition, the area is formed smaller than that corresponding to the through hole 21. Thereby, the back surface chipping prevention groove 5 </ b> G is shallower than the through-hole portion 21 due to the microloading effect.

一方、溝の開口が小さくなって、チッピング防止効果が薄れる分に対しては、開口を複数設けることにより、その効果を回復する。図１４は、その開口のパターンの例を示す図である。図１４（ａ）は、開口が円形の形状で２列設けた場合を示しており、同図（ｂ）はそれが３列になった場合を示している。また、図１４（ｃ）は、開口が矩形の形状で２列設けた場合を示しており、同図（ｂ）はそれが３列になった場合を示している。なお、無論、４列以上でも構わない。   On the other hand, when the opening of the groove is reduced and the chipping prevention effect is reduced, the effect is recovered by providing a plurality of openings. FIG. 14 is a diagram showing an example of the opening pattern. FIG. 14A shows a case where the openings are provided in a circular shape and two rows are provided, and FIG. 14B shows a case where the openings are arranged in three rows. FIG. 14 (c) shows a case where the openings are provided in a rectangular shape and two rows are provided, and FIG. 14 (b) shows a case where the openings are arranged in three rows. Of course, four or more rows may be used.

また、図１３において、メモリチップ１Ｈの他の構成は、第一実施形態のそれと同様である。   In FIG. 13, the other configuration of the memory chip 1H is the same as that of the first embodiment.

なお、上述の各実施形態においては、半導体チップを、メモリチップ、特にＤＲＡＭ、として説明したが、これに限られることはなく、他の半導体メモリ、つまり、ＳＲＡＭ，ＰＲＡＭ、フラッシュメモリ等であってもよい。更に、メモリチップである必要もなく、上述の半導体パッケージの一部を形成するインターフェースチップであってもよい。   In each of the above-described embodiments, the semiconductor chip has been described as a memory chip, particularly a DRAM. However, the present invention is not limited to this, and other semiconductor memories, that is, SRAMs, PRAMs, flash memories, etc. Also good. Furthermore, it is not necessary to be a memory chip, and it may be an interface chip that forms a part of the semiconductor package described above.

１Ａ〜１Ｈ…メモリチップ
２ａ，２ｂ…貫通電極
２１…貫通孔部
２２…配線
２３…コンタクトプラグ
２４…ピラー部
２５…表面バンプ電極
２６…裏面バンプ電極
３ａ，３ｂ…クラックストップ
４…ガードリング
５Ａ〜５Ｇ…裏面チッピング防止溝
１０…半導体基板
１１〜１４…層間絶縁膜
１００…ウエハ
ＳＣ…スクライブセンター
ＳＡ…スクライブエリア
ＧＡ…ガードリングエリア
ＡＡ…アクティブエリア DESCRIPTION OF SYMBOLS 1A-1H ... Memory chip 2a, 2b ... Through electrode 21 ... Through-hole part 22 ... Wiring 23 ... Contact plug 24 ... Pillar part 25 ... Front surface bump electrode 26 ... Back surface bump electrode 3a, 3b ... Crack stop 4 ... Guard ring 5A- 5G ... Back surface chipping prevention groove 10 ... Semiconductor substrate 11-14 ... Interlayer insulating film 100 ... Wafer SC ... Scribe center SA ... Scribe area GA ... Guard ring area AA ... Active area

Claims (11)

表面側電極と裏面側電極とをつなぐ貫通電極が貫通する半導体基板を備えた半導体チップであって、
前記半導体基板は、その裏面側周縁と前記貫通電極との間に溝が設けられており、
前記溝は、前記半導体基板の裏面側周縁と、当該半導体チップを積層する際の目印となるマークとの間に、更に設けられていることを特徴とする半導体チップ。 A semiconductor chip comprising a semiconductor substrate through which a through electrode connecting the front surface side electrode and the back surface side electrode penetrates,
The semiconductor substrate is provided with a groove between the back surface side periphery and the through electrode,
The semiconductor chip according to claim 1, wherein the groove is further provided between a peripheral edge on the back surface side of the semiconductor substrate and a mark serving as a mark when the semiconductor chips are stacked. １枚のウエハに複数の半導体チップを形成してダイシングにより分断する半導体チップの製造方法であって、
表面バンプ電極形成までの配線工程が完了した後、前記ウエハの表面側を加工して外周を研削した後、支持体を貼り付け、
前記ウエハの裏面側を研削して窒化膜を成長させ、
裏面チッピング防止溝を形成するパターンとしてのフォトレジストを塗布し、露光、現像、浅溝エッチング処理を施し、前記フォトレジストを除去した後、再度窒化膜を成長させ、
貫通孔部を形成するためのフォトレジストを塗布し、露光、現像、貫通孔エッチング処理を施して、前記フォトレジストを除去した後、シード膜をスパッタで形成し、
裏面バンプ電極を形成するためのフォトレジストを塗布し、露光、現像処理を施し、銅をメッキすると共に電極材をメッキし、前記フォトレジストを除去すると共に前記シード膜を除去する各工程を少なくとも含むことを特徴とする半導体チップの製造方法。 A method of manufacturing a semiconductor chip, wherein a plurality of semiconductor chips are formed on one wafer and divided by dicing,
After completing the wiring process until the surface bump electrode formation, after processing the surface side of the wafer and grinding the outer periphery, the support is pasted,
Grinding the back side of the wafer to grow a nitride film,
After applying a photoresist as a pattern for forming a back surface chipping prevention groove, exposure, development, shallow groove etching treatment, removing the photoresist, and then growing a nitride film again,
After applying a photoresist for forming a through-hole portion, performing exposure, development, through-hole etching treatment, removing the photoresist, and forming a seed film by sputtering,
It includes at least each step of applying a photoresist for forming a back bump electrode, exposing and developing, plating copper, plating an electrode material, removing the photoresist and removing the seed film. A method of manufacturing a semiconductor chip. 前記裏面チッピング防止溝を形成するためのフォトレジストを、前記貫通孔部の開口よりも小さい複数の開口を有するパターンで構成することにより、前記裏面チッピング防止溝を形成する各工程と、前記貫通孔部を形成する各工程を同時に行うことを特徴とする請求項２に記載の半導体チップの製造方法。   Each step of forming the back surface chipping prevention groove by forming a photoresist for forming the back surface chipping prevention groove with a pattern having a plurality of openings smaller than the opening of the through hole portion, and the through hole The method for manufacturing a semiconductor chip according to claim 2, wherein each step of forming the portion is performed simultaneously. 半導体基板と、
前記半導体基板を貫通する貫通電極と、
前記半導体基板の第１面上に設けられた層間絶縁膜と、
前記層間絶縁膜内に設けられたガードリングと、を備え、
前記半導体基板は、前記半導体基板の第２面に設けられ、前記半導体基板の周縁と前記貫通電極との間に位置する溝構造体を含み、
前記ガードリングは、前記半導体基板の前記第２面と直交する第１方向において少なくとも部分的に前記溝構造体と重なる、半導体装置。 A semiconductor substrate;
A through electrode penetrating the semiconductor substrate;
An interlayer insulating film provided on the first surface of the semiconductor substrate;
A guard ring provided in the interlayer insulating film,
The semiconductor substrate includes a groove structure provided on a second surface of the semiconductor substrate and positioned between a peripheral edge of the semiconductor substrate and the through electrode,
The said guard ring is a semiconductor device which overlaps with the said groove structure at least partially in the 1st direction orthogonal to the said 2nd surface of the said semiconductor substrate. 前記層間絶縁膜内に設けられた多層接続構造体をさらに備え、
前記多層接続構造体は、第１及び第２接続導体と、前記第１接続導体と前記第２接続導体を接続する第１コンタクトプラグとを含み、
前記半導体基板の前記第２面は前記第１面の反対側であり、前記貫通電極の一端は前記第１接続導体に接続されている、請求項４の半導体装置。 A multilayer connection structure provided in the interlayer insulating film;
The multilayer connection structure includes first and second connection conductors, and a first contact plug that connects the first connection conductor and the second connection conductor,
The semiconductor device according to claim 4, wherein the second surface of the semiconductor substrate is opposite to the first surface, and one end of the through electrode is connected to the first connection conductor. 前記多層接続構造体上に設けられた第１電極をさらに備え、
前記多層接続構造体は、前記第２接続導体に電気的に接続された第３接続導体をさらに含み、
前記第１接続導体は前記第３接続導体に接続されている、請求項５の半導体装置。 A first electrode provided on the multilayer connection structure;
The multilayer connection structure further includes a third connection conductor electrically connected to the second connection conductor;
The semiconductor device according to claim 5, wherein the first connection conductor is connected to the third connection conductor. 前記半導体基板の前記第２面上に設けられた第２電極をさらに備え、
前記第２電極は前記貫通電極の他端に接続され、これにより前記第１電極は前記多層接続構造体及び前記貫通電極を介して前記第２電極に電気的に接続されている、請求項６の半導体装置。 A second electrode provided on the second surface of the semiconductor substrate;
The second electrode is connected to the other end of the through electrode, whereby the first electrode is electrically connected to the second electrode through the multilayer connection structure and the through electrode. Semiconductor device. 前記半導体基板は少なくともアライメントマークを有し、前記溝構造体は前記アライメントマークと前記半導体基板の前記周縁との間に位置する、請求項４の半導体装置。   The semiconductor device according to claim 4, wherein the semiconductor substrate has at least an alignment mark, and the groove structure is located between the alignment mark and the peripheral edge of the semiconductor substrate. 前記溝構造体は前記半導体基板を貫通していない、請求項４の半導体装置。   The semiconductor device according to claim 4, wherein the groove structure does not penetrate the semiconductor substrate. 配線基板と、
前記配線基板に積層された複数の半導体チップと、を備え、
前記複数の半導体チップのそれぞれは、
互いに反対側に位置する第１面及び第２面を有する半導体基板と、
前記半導体基板の前記第１面上の層間絶縁膜と、
前記層間絶縁膜内に設けられたガードリング構造体と、
前記層間絶縁膜内に設けられた複数の接続導体と、
前記半導体基板を貫通し、前記複数の接続導体に接続された複数の貫通電極と、を備え、
前記半導体基板は、前記第２面に溝構造体を有し、
前記溝構造体は、前記半導体基板の縁部と前記複数の貫通電極との間に配置され、
前記ガードリング構造体は、前記半導体基板の前記第２面と直交する第１方向において少なくとも部分的に前記溝構造体と重なる、半導体装置。 A wiring board;
A plurality of semiconductor chips stacked on the wiring board,
Each of the plurality of semiconductor chips is
A semiconductor substrate having a first surface and a second surface located on opposite sides;
An interlayer insulating film on the first surface of the semiconductor substrate;
A guard ring structure provided in the interlayer insulating film;
A plurality of connecting conductors provided in the interlayer insulating film;
A plurality of through electrodes penetrating the semiconductor substrate and connected to the plurality of connection conductors,
The semiconductor substrate has a groove structure on the second surface;
The groove structure is disposed between an edge of the semiconductor substrate and the plurality of through electrodes,
The said guard ring structure is a semiconductor device which overlaps with the said groove structure at least partially in the 1st direction orthogonal to the said 2nd surface of the said semiconductor substrate. 互いに反対側に位置する第１表面部分及び第２表面部分を有する半導体基板と、
前記半導体基板の前記第１表面部分上に設けられた層間絶縁膜と、
前記層間絶縁膜内に設けられたガードリングと、
前記半導体基板を貫通する複数の貫通電極と、
前記第１表面部分に設けられた複数の回路素子と、
前記第２表面部分において前記半導体基板を貫通することなく設けられた溝と、を備え、
前記ガードリングは、前記半導体基板の前記第２表面部分と直交する第１方向において少なくとも部分的に前記溝と重なる、半導体装置。 A semiconductor substrate having a first surface portion and a second surface portion located opposite to each other;
An interlayer insulating film provided on the first surface portion of the semiconductor substrate;
A guard ring provided in the interlayer insulating film;
A plurality of through electrodes penetrating the semiconductor substrate;
A plurality of circuit elements provided on the first surface portion;
A groove provided in the second surface portion without penetrating the semiconductor substrate,
The said guard ring is a semiconductor device which overlaps with the said groove | channel at least partially in the 1st direction orthogonal to the said 2nd surface part of the said semiconductor substrate.
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