JP3498459B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3498459B2 JP3498459B2 JP33714695A JP33714695A JP3498459B2 JP 3498459 B2 JP3498459 B2 JP 3498459B2 JP 33714695 A JP33714695 A JP 33714695A JP 33714695 A JP33714695 A JP 33714695A JP 3498459 B2 JP3498459 B2 JP 3498459B2
- Authority
- JP
- Japan
- Prior art keywords
- protective film
- bonding pads
- opening
- adjacent
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.
【０００２】[0002]
【従来の技術】半導体装置においては、半導体チップ上
に複数のボンディングパッドが形成され、その表面にボ
ンディングパッドを残してパッシベーション膜としての
第１保護膜（例えば、Ｓｉ3 Ｎ4 ）が形成され、さらに
第１保護膜を被覆する第２保護膜（例えば、ポリミド保
護膜）が形成されている。この第２保護膜には、ボンデ
ィングパッドに対応した部分に開口部が形成されてお
り、その開口部を介してワイヤボンディングが行われ
る。2. Description of the Related Art In a semiconductor device, a plurality of bonding pads are formed on a semiconductor chip, and a first protective film (eg, Si 3 N 4 ) as a passivation film is formed on the surface of the bonding pad leaving the bonding pads. Further, a second protective film (for example, a polyimide protective film) that covers the first protective film is formed. An opening is formed in the second protective film at a portion corresponding to the bonding pad, and wire bonding is performed through the opening.
【０００３】[0003]
【発明が解決しようとする課題】従来のものでは、第２
保護膜に、個々のボンディングパッドに対応して開口部
が形成されている。すなわち、図３の平面図に示すよう
に、ボンディングパッド２に対応して、第２保護膜４
（斜線で示す部分）には個別に開口部６が形成されてい
る。なお、１は半導体チップである。According to the conventional method, the second
Openings are formed in the protective film so as to correspond to the individual bonding pads. That is, as shown in the plan view of FIG. 3, the second protective film 4 corresponding to the bonding pad 2 is formed.
Openings 6 are individually formed in the (hatched portion). In addition, 1 is a semiconductor chip.
【０００４】このような構成において、素子の微細化が
進み、図３のＡで示す部分のように、隣接するボンディ
ングパッド間の距離が短くなると、その間に存在する第
２保護膜が細くなり、その後の工程で、その部分の第２
保護膜が剥がれ、ボンディングパッドに付着し、ボンデ
ィング不良を起こすおそれがある。このことを図４に示
す工程図を用いて説明する。In such a structure, when the element is further miniaturized and the distance between the adjacent bonding pads is shortened as shown by A in FIG. 3, the second protective film existing between them becomes thin, In the subsequent process, the second of that part
The protective film may peel off and adhere to the bonding pad, resulting in defective bonding. This will be described with reference to the process chart shown in FIG.
【０００５】まず、半導体チップ１上にボンディングパ
ッド２を形成し、さらにボンディングパッド２を残して
半導体チップ１の表面に第１保護膜３を形成する（図４
（ａ））。その後、第２保護膜４を全面に形成する（図
４（ｂ））。次に、ボンディングパッド２の上部を開口
するようにホトレジスト５を形成し（図４（ｃ））、等
方性エッチングにて第２保護膜４に開口部６を形成する
（図４（ｄ））。この時、図に示すように、隣接するボ
ンディングパッド２間の距離が短いと、その間の第２保
護膜４が図に示すように細くなり、剥がれやすくなる。First, the bonding pad 2 is formed on the semiconductor chip 1, and the first protective film 3 is formed on the surface of the semiconductor chip 1 with the bonding pad 2 left (FIG. 4).
(A)). After that, the second protective film 4 is formed on the entire surface (FIG. 4B). Next, a photoresist 5 is formed so as to open the upper portion of the bonding pad 2 (FIG. 4C), and an opening 6 is formed in the second protective film 4 by isotropic etching (FIG. 4D). ). At this time, if the distance between the adjacent bonding pads 2 is short as shown in the figure, the second protective film 4 between them becomes thin as shown in the figure, and is easily peeled off.
【０００６】本発明は上記問題に鑑みたもので、隣接す
るボンディングパッド間の距離が短くなっても、その間
の第２保護膜の剥がれによるボンディング不良をなくす
ことを目的とする。The present invention has been made in view of the above problems, and an object thereof is to eliminate defective bonding due to peeling of the second protective film between the adjacent bonding pads even if the distance between the adjacent bonding pads is shortened.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するた
め、請求項１に記載の発明においては、少なくとも２つ
の隣接するボンディングパッドを含んで１つの共通開口
部とするように第２保護膜に開口部が形成され、前記共
通開口部において隣接するボンディングパッド間に第１
保護膜が残っていることを特徴としている。従って、隣
接するボンディングパッド間の距離が短くなっても、そ
の間の第２保護膜をなくし、１つの開口部としているた
め、第２保護膜の剥がれによるボンディング不良をなく
すことができる。In order to achieve the above object, in the invention described in claim 1, the second protective film is formed so as to include at least two adjacent bonding pads to form one common opening. An opening is formed ,
First between the bonding pads adjacent to each other in the through opening
The feature is that the protective film remains . Therefore, even if the distance between the adjacent bonding pads becomes short, the second protective film between them is eliminated and one opening is formed, so that the defective bonding due to the peeling of the second protective film can be eliminated.
【０００８】請求項２に記載の発明においては、隣接す
るボンディングパッド間の距離が狭い部分に対しては共
通開口部とし、隣接するボンディングパッド間の距離が
広い部分に対しては個別の開口部とするようにしたこと
を特徴としている。従って、隣接するボンディングパッ
ド間の距離が狭い部分に対しては共通開口部として上記
した作用効果を奏するようにし、隣接するボンディング
パッド間の距離が広い部分には、その間に第２保護膜を
残してその下部にも素子が形成できるようにし、素子形
成領域を広くすることができる。According to the second aspect of the present invention, a common opening is provided for a portion where the distance between adjacent bonding pads is small, and an individual opening is provided for a portion where the distance between adjacent bonding pads is wide. It is characterized by doing so. Therefore, the above-described function and effect are provided as the common opening for the portion where the distance between the adjacent bonding pads is narrow, and the second protective film is left between the portions where the distance between the adjacent bonding pads is wide. The element formation region can be widened so that the element can be formed below the electrode.
【０００９】また、請求項２に記載の半導体装置は、請
求項３に記載の発明を用いて適正に製造することができ
る。The semiconductor device described in claim 2 can be properly manufactured by using the invention described in claim 3.
【００１０】[0010]
【発明の実施の形態】以下、本発明を図に示す実施形態
について説明する。図１は、本発明の一実施形態を示す
平面図である。この図１は、図３に示すものと対応する
ものであり、図３のＡで示す、隣接するボンディングパ
ッド２間の距離が短い部分に対しては、その間の第２保
護膜４を除去し、複数のボンディングパッド２に対して
１つの共通開口部６ａを形成するようにしている。な
お、図中の斜線部分が、第２保護膜４の形成領域を示し
ている。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention shown in the drawings will be described. FIG. 1 is a plan view showing an embodiment of the present invention. This FIG. 1 corresponds to that shown in FIG. 3, and for the portion where the distance between the adjacent bonding pads 2 shown in A of FIG. 3 is short, the second protective film 4 between them is removed. , One common opening 6a is formed for the plurality of bonding pads 2. The shaded area in the drawing indicates the formation region of the second protective film 4.
【００１１】図１に示すものの製造工程を図２に示す。
まず、半導体チップ１上にボンディングパッド２を形成
し、さらにボンディングパッド２を残して半導体チップ
１の表面に第１保護膜３を形成し（図２（ａ））、その
後、第２保護膜４を全面に形成する（図２（ｂ））。次
に、複数のボンディングパッド２のうち隣接するボンデ
ィングパッド間の距離が狭い部分に対しては１つの共通
開口部とし、隣接するボンディングパッド間の距離が広
い部分に対しては個別の開口部とするようにホトレジス
トでマスクパターン５を形成する（図２（ｃ））。な
お、図２においては、ボンディングパッド間の距離が狭
い部分に対して図示している。The manufacturing process of the one shown in FIG. 1 is shown in FIG.
First, the bonding pad 2 is formed on the semiconductor chip 1, and the first protective film 3 is further formed on the surface of the semiconductor chip 1 with the bonding pad 2 left (FIG. 2A), and then the second protective film 4 is formed. Are formed on the entire surface (FIG. 2B). Next, among the plurality of bonding pads 2, one common opening is provided for a portion where the distance between adjacent bonding pads is small, and an individual opening is provided for a portion where the distance between adjacent bonding pads is wide. Thus, the mask pattern 5 is formed of photoresist (FIG. 2C). In FIG. 2, a portion where the distance between the bonding pads is narrow is shown.
【００１２】この後、等方性エッチングにて第２保護膜
４に開口部を形成する（図２（ｄ）。この場合、隣接す
るボンディングパッド間の距離が狭い部分に対し、その
間の第２保護膜４が除去されて、１つの共通開口部６ａ
となる。従って、上記した工程により、図１に示すよう
に、隣接するボンディングパッド間の距離が狭い部分に
対しては共通開口部６ａが、隣接するボンディングパッ
ド間の距離が広い部分に対しては個別の開口部６ｂが形
成される。After that, an opening is formed in the second protective film 4 by isotropic etching (FIG. 2 (d). In this case, for the portion where the distance between adjacent bonding pads is narrow, the second portion between them is formed. The protective film 4 is removed and one common opening 6a is formed.
Becomes Therefore, as a result of the above steps, as shown in FIG. 1, the common opening 6a is provided for the portion where the distance between the adjacent bonding pads is narrow, and the individual opening 6a is provided for the portion where the distance between the adjacent bonding pads is wide. The opening 6b is formed.
【００１３】この後、従来のものと同様、ワイヤボンデ
ィングを行い、樹脂封止する。上記した実施形態におい
て、具体的には、ボンディングパッド２の一辺の大きさ
は９６μｍであり、隣接するボンディングパッドの間隔
が３６μｍ（その上部のホトレジスト５の幅としては２
８μｍ）を境に、それ以上の時には個別の開口部６ｂを
形成し、それより小さい時には共通開口部６ａを形成す
るようにしている。After this, wire bonding is performed and resin sealing is performed as in the conventional case. In the above-described embodiment, specifically, the size of one side of the bonding pad 2 is 96 μm, and the interval between the adjacent bonding pads is 36 μm (the width of the photoresist 5 above it is 2 μm).
8 μm), the individual openings 6b are formed when the width is larger than 8 μm, and the common openings 6a are formed when the width is smaller than 8 μm.
【００１４】なお、上記した第２保護膜４としては、ポ
リミド膜等の有機薄膜以外に、Ｐ−ＳｉＮ膜、Ｐ−Ｓｉ
ＯＮ／Ｐ−ＴＥＯＳ酸化膜、ＴＥＯＳ−Ｏ3 膜等を用い
ることができる。また、共通開口部と個別の開口部を設
けずに、半導体チップ１上の周辺領域に形成されるボン
ディングパッドの全てに対し、共通開口部６ａとして形
成することもできる。しかし、上記した実施形態に示す
ように、隣接するボンディングパッド間の距離が広い部
分に対しては個別の開口部を設けた方が、その間の第２
保護膜の下部にも素子が形成できるため、共通開口部と
個別の開口部を混在させるのが好ましい。The second protective film 4 may be a P-SiN film or a P-Si film other than an organic thin film such as a polyimide film.
ON / P-TEOS oxide film, TEOS-O 3 film or the like can be used. Alternatively, the common opening 6a can be formed for all the bonding pads formed in the peripheral region on the semiconductor chip 1 without providing the common opening and the individual openings. However, as shown in the above-described embodiment, it is better to provide a separate opening for a portion where the distance between the adjacent bonding pads is wide, and the second opening therebetween.
Since the element can be formed below the protective film, it is preferable to mix the common opening and the individual openings.
【００１５】さらに、第２保護膜４のエッチングにおい
ては、等方性エッチングに限らず、異方性エッチングを
用いることもできる。さらに、ホトレジスト膜を露光し
た後、ホトレジストを現像すると同時に第２保護膜４を
エッチングする方法を用いてもよい。Further, the etching of the second protective film 4 is not limited to isotropic etching, but anisotropic etching can be used. Furthermore, after exposing the photoresist film, the method of developing the photoresist and simultaneously etching the second protective film 4 may be used.
【図１】本発明の一実施形態を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図２】図１に示すものの製造工程を示す図である。FIG. 2 is a diagram showing a manufacturing process of the one shown in FIG.
【図３】従来構成を示す平面図である。FIG. 3 is a plan view showing a conventional configuration.
【図４】図３に示すものの製造工程を示す図である。FIG. 4 is a diagram showing a manufacturing process of the one shown in FIG. 3;
１…半導体チップ、２…ボンディングパッド、３…第１
保護膜、４…第２保護膜、６ａ…共通開口部、６ｂ…個
別開口部。1 ... Semiconductor chip, 2 ... Bonding pad, 3 ... First
Protective film, 4 ... Second protective film, 6a ... Common opening, 6b ... Individual opening.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−183142（ＪＰ，Ａ) 特開 昭62−224037（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 301 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-3-183142 (JP, A) JP-A-62-124037 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 301
Claims (3)
プ上に形成された複数のボンディングパッド（２）と、
この複数のボンディングパッドを残して前記半導体チッ
プの表面に形成された第１保護膜（３）と、前記複数の
ボンディングパッドに対応した部分に開口部が形成され
前記第１保護膜を被覆する第２保護膜（４）を有してな
る半導体装置において、 少なくとも２つの隣接するボンディングパッドを含んで
１つの共通開口部（６ａ）とするように前記第２保護膜
に開口部が形成され、前記共通開口部において前記隣接
するボンディングパッド間に前記第１保護膜が残ってい
ることを特徴とする半導体装置。1. A semiconductor chip (1) and a plurality of bonding pads (2) formed on the semiconductor chip,
A first protective film (3) formed on the surface of the semiconductor chip leaving the plurality of bonding pads, and an opening formed in a portion corresponding to the plurality of bonding pads to cover the first protective film. in the semiconductor device having a two protective film (4), an opening is formed on the second protective layer to a single common opening includes at least two adjacent bonding pads (6a), wherein Adjacent at the common opening
The semiconductor device , wherein the first protective film remains between the bonding pads .
うち隣接するボンディングパッド間の距離が狭い部分に
対しては前記共通開口部（６ａ）とし、隣接するボンデ
ィングパッド間の距離が広い部分に対しては個別の開口
部（６ｂ）とするように、前記第２保護膜に開口部が形
成されていることを特徴とする請求項１に記載の半導体
装置。2. The common opening (6a) is provided for a portion of the plurality of bonding pads (2) where the distance between adjacent bonding pads is narrow, and for the portion where the distance between adjacent bonding pads is wide. The semiconductor device according to claim 1, wherein an opening is formed in the second protective film so as to form an individual opening (6b).
ングパッド（２）を形成するとともに、この複数のボン
ディングパッドを残して前記半導体チップの表面に第１
保護膜（３）を形成する工程と、 この後、表面に第２保護膜（４）を形成する工程と、 前記複数のボンディングパッドのうち隣接するボンディ
ングパッド間の距離が狭い部分に対しては１つの共通開
口部（６ａ）とし、隣接するボンディングパッド間の距
離が広い部分に対しては個別の開口部（６ｂ）とするよ
うにマスクパターン（５）を形成して、前記第２保護膜
をエッチングする工程とを有し、前記エッチングにより
形成された前記共通開口部において前記隣接するボンデ
ィングパッド間に前記第１保護膜が残っていることを特
徴とする半導体装置の製造方法。3. A plurality of bonding pads (2) are formed on a semiconductor chip (1), and the plurality of bonding pads are left on the surface of the semiconductor chip.
The step of forming the protective film (3), the step of forming the second protective film (4) on the surface thereafter, and the step of forming a second protective film (4) on the surface, and The mask pattern (5) is formed so as to form one common opening (6a) and an individual opening (6b) for a portion where the distance between adjacent bonding pads is wide, and the second protective film is formed. It was closed and etching, by the etching
The adjacent bonders in the formed common opening
A method of manufacturing a semiconductor device , wherein the first protective film remains between the wing pads .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33714695A JP3498459B2 (en) | 1995-12-25 | 1995-12-25 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33714695A JP3498459B2 (en) | 1995-12-25 | 1995-12-25 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09181114A JPH09181114A (en) | 1997-07-11 |
| JP3498459B2 true JP3498459B2 (en) | 2004-02-16 |
Family
ID=18305884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33714695A Expired - Fee Related JP3498459B2 (en) | 1995-12-25 | 1995-12-25 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3498459B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050178498A1 (en) * | 2004-02-18 | 2005-08-18 | Au Optronics Corporation | Method for sealing electroluminescence display devices |
-
1995
- 1995-12-25 JP JP33714695A patent/JP3498459B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09181114A (en) | 1997-07-11 |
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