JP3279309B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP3279309B2
JP3279309B2 JP2000239261A JP2000239261A JP3279309B2 JP 3279309 B2 JP3279309 B2 JP 3279309B2 JP 2000239261 A JP2000239261 A JP 2000239261A JP 2000239261 A JP2000239261 A JP 2000239261A JP 3279309 B2 JP3279309 B2 JP 3279309B2
Authority
JP
Japan
Prior art keywords
connection pad
semiconductor device
forming
wiring
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000239261A
Other languages
Japanese (ja)
Other versions
JP2001085455A (en
Inventor
孝一 金井
孝次 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
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Filing date
Publication date
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Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2000239261A priority Critical patent/JP3279309B2/en
Publication of JP2001085455A publication Critical patent/JP2001085455A/en
Application granted granted Critical
Publication of JP3279309B2 publication Critical patent/JP3279309B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
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    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】この発明は半導体装置及びその製
造方法に関し、例えば、突起電極を有する半導体装置及
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, for example, a semiconductor device having a bump electrode and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】ＣＯＧ(chip on glass)方式やフリップ
チップ方式等と呼ばれる半導体装置（ＩＣチップ）の実
装技術では、半導体装置の接続パッド上に形成された突
起電極を基板上に形成された接続パッド上に直接ボンデ
ィングすることにより、半導体装置を基板上に搭載して
いる。したがって、半導体装置には突起電極を設ける必
要がある。2. Description of the Related Art In a mounting technology of a semiconductor device (IC chip) called a COG (chip on glass) method or a flip chip method, a projection electrode formed on a connection pad of the semiconductor device is connected to a connection formed on a substrate. The semiconductor device is mounted on the substrate by bonding directly to the pads. Therefore, it is necessary to provide a bump electrode in the semiconductor device.

【０００３】図６（Ａ）及び（Ｂ）は従来のこのような
半導体装置の一部を示したものである。この半導体装置
はシリコン基板１を備えている。シリコン基板１は例え
ば平面正方形状であって、図６（Ａ）において一点鎖線
で示すように、四辺部を除く中央部を素子形成領域２と
されている。この素子形成領域２には所定の半導体素子
が多数形成されている。シリコン基板１の上面には絶縁
膜３が形成されている。絶縁膜３の上面には、素子形成
領域２に対応する領域に半導体素子に接続された配線パ
ターン４が形成され、四辺部に接続パッド５が形成さ
れ、その間に配線パターン４と接続パッド５とを接続す
る引き回し線６が形成されている。そして、接続パッド
５の中央部を除く上面全体には絶縁膜７が形成され、接
続パッド５の中央部が絶縁膜７に形成された開口部８を
介して露出されている。この露出された接続パッド５の
上面及びその周囲の絶縁膜７の上面には下地金属層９を
介して突起電極１０が形成されている。FIGS. 6A and 6B show a part of such a conventional semiconductor device. This semiconductor device has a silicon substrate 1. The silicon substrate 1 has, for example, a planar square shape, and a central portion excluding four sides is an element forming region 2 as shown by a dashed line in FIG. In the element formation region 2, a large number of predetermined semiconductor elements are formed. An insulating film 3 is formed on the upper surface of the silicon substrate 1. On the upper surface of the insulating film 3, a wiring pattern 4 connected to the semiconductor element is formed in a region corresponding to the element forming region 2, connection pads 5 are formed on four sides, and the wiring pattern 4 and the connection pads 5 are formed therebetween. Are formed. An insulating film 7 is formed on the entire upper surface of the connection pad 5 except for the center, and the center of the connection pad 5 is exposed through an opening 8 formed in the insulating film 7. A projecting electrode 10 is formed on the exposed upper surface of the connection pad 5 and the upper surface of the insulating film 7 therearound via a base metal layer 9.

【０００４】[0004]

【発明が解決しようとする課題】ところで、従来のこの
ような半導体装置では、半導体素子の集積化が進むにし
たがって、突起電極１０の数が増大することにより、次
のような問題があった。すなわち、シリコン基板１のサ
イズが一定であるとすると、半導体素子に対応した突起
電極１０の数の増大に伴い、突起電極１０のサイズ及び
ピッチが小さくなるので、半導体装置とこれを搭載する
ための基板との位置合わせが極めて困難となり、また電
気的テストをプローブピンを用いて行う際に、プローブ
ピンと突起電極１０との位置合わせが極めて困難となる
という問題があった。特に、後者の電気的テストの場合
には、プローブピンのサイズ及びピッチに対して突起電
極１０のサイズ及びピッチが小さくなりすぎると、ショ
ートしてしまうので、電気的テストを行うことができな
くなってしまう。この発明の目的は、突起電極の数が増
大しても、突起電極のサイズ及びピッチを大きくするこ
とができる半導体装置及びその製造方法を提供すること
にある。However, such a conventional semiconductor device has the following problem because the number of protruding electrodes 10 increases as the integration of semiconductor elements progresses. That is, assuming that the size of the silicon substrate 1 is constant, the size and pitch of the protruding electrodes 10 decrease with an increase in the number of protruding electrodes 10 corresponding to the semiconductor elements. There has been a problem that the alignment with the substrate becomes extremely difficult, and when the electrical test is performed using the probe pins, the alignment between the probe pins and the protruding electrodes 10 becomes extremely difficult. In particular, in the case of the latter electrical test, if the size and pitch of the protruding electrodes 10 are too small with respect to the size and pitch of the probe pins, a short circuit occurs, so that the electrical test cannot be performed. I will. An object of the present invention is to provide a semiconductor device capable of increasing the size and pitch of the projecting electrodes even if the number of projecting electrodes increases, and a method of manufacturing the same.

【０００５】[0005]

【課題を解決するための手段】請求項１記載の発明に係
る半導体装置は、半導体基板上の中央部が素子形成領域
とされ、周縁部の少なくとも相対向する一対の側辺部に
接続パッドが所定ピッチで配列された半導体装置におい
て、前記半導体基板の上面全体に前記各接続パッドを露
出する開口部を有する絶縁層が形成され、前記絶縁層上
に引き回され、前記半導体基板の素子形成領域上に対応
して前記接続パッドよりも大きいサイズの接続パッド部
を有し且つ前記絶縁膜の開口部を介して前記接続パッド
に接続される複数の配線が形成され、少なくとも前記各
配線の前記接続パッド上に前記接続パッドより大きいサ
イズの突起電極が形成されており、前記配線の接続パッ
ド部は、隣接する前記接続パッドに接続された配線の接
続パッド部とは異なる行または列に配置されるように、
側辺部に配列された前記接続パッドよりも大きいピッチ
でマトリックス状に配列されていることを特徴とするも
のである。請求項６記載の発明に係る半導体装置の製造
方法は、半導体基板上の中央部が素子形成領域とされ、
周縁部の少なくとも相対向する一対の側辺部に接続パッ
ドが所定ピッチで配列された半導体装置の製造方法にお
いて、前記半導体基板の上面全体に前記各接続パッドを
露出する開口部を有する絶縁層を形成する工程と、前記
絶縁層上に引き回され、前記半導体基板の素子形成領域
上に対応して前記接続パッドよりも大きいサイズの接続
パッド部を有し且つ前記絶縁膜の開口部を介して前記接
続パッドに接続される複数の配線を形成する工程と、少
なくとも前記各配線の前記接続パッド上に前記接続パッ
ドより大きいサイズの突起電極を形成する工程とを有
し、前記配線形成工程は、前記配線の接続パッド部が隣
接する前記接続パッドに接続された配線の接続パッド部
とは異なる行または列に配置されるように、側辺部に配
列された前記接続パッドよりも大きいピッチでマトリッ
クス状に配列することを特徴とするものである。According to a first aspect of the present invention, there is provided a semiconductor device, wherein a central portion on a semiconductor substrate is an element forming region, and connection pads are formed on at least a pair of side edges of a peripheral portion opposed to each other. In a semiconductor device arranged at a predetermined pitch, an insulating layer having an opening exposing each of the connection pads is formed on the entire upper surface of the semiconductor substrate, and the insulating layer is routed on the insulating layer to form an element forming region of the semiconductor substrate. A plurality of wirings having a connection pad portion corresponding to a size larger than the connection pad and being connected to the connection pad through an opening of the insulating film are formed, and at least the connection of each of the wirings is formed. A projection electrode having a size larger than the connection pad is formed on the pad, and the connection pad portion of the wiring is different from the connection pad portion of the wiring connected to the adjacent connection pad. Line or to be placed in the column that,
The connection pads are arranged in a matrix at a larger pitch than the connection pads arranged on the side. According to a sixth aspect of the invention, there is provided a method of manufacturing a semiconductor device, wherein a central portion on the semiconductor substrate is an element formation region,
In a method of manufacturing a semiconductor device in which connection pads are arranged at a predetermined pitch on at least a pair of side edges of a peripheral portion, an insulating layer having an opening exposing each of the connection pads is entirely formed on an upper surface of the semiconductor substrate. Forming, and having a connection pad portion of a size larger than the connection pad corresponding to the element formation region of the semiconductor substrate, which is routed on the insulating layer, and through an opening of the insulating film. Forming a plurality of wirings connected to the connection pad, and forming a projection electrode having a size larger than the connection pad on at least the connection pad of each of the wirings, the wiring formation step includes: The connection pads arranged on the side portions such that the connection pad parts of the wiring are arranged in different rows or columns from the connection pad parts of the wirings connected to the adjacent connection pads. Doyori in even greater pitch is characterized in that arranged in a matrix.

【０００６】[0006]

【実施例】図１（Ａ）及び（Ｂ）はこの発明の一実施例
における半導体装置の要部を示したものである。これら
の図において、図６（Ａ）及び（Ｂ）と同一部分には同
一の符号を付し、その説明を適宜省略する。この実施例
では、絶縁膜７と、該絶縁膜７上に形成された保護膜１
１とにより絶縁層が形成されている。保護膜１１の絶縁
膜７の開口部８に対応する部分には開口部１２が形成さ
れている。接続パッド５の上面から素子形成領域２上に
おける保護膜１１の上面の所定の個所にかけては、第１
接続パッド部１３ａと引き回し線部１３ｂと第２接続パ
ッド部１３ｃとからなる下地金属層（配線）１３が形成
され、この下地金属層１３の上面には突起電極１４が形
成されている。この場合、突起電極１４は、第１接続パ
ッド部１３ａ上に形成された第１電極部１４ａと、引き
回し線部１３ｂ上に形成された引き回し線部１４ｂと、
第２接続パッド部１３ｃ上に形成された第２電極部１４
ｃとからなっている。また、下地金属層１３の第２接続
パッド部１３ｃのサイズは接続パッド５のサイズのほぼ
４倍となっており、したがって突起電極１４の第２電極
部１４ｃのサイズは接続パッド５上に形成された第１電
極部１４ａのサイズ、すなわち接続パッド５のサイズの
ほぼ４倍となっている。また、下地金属層１３の第２接
続パッド部１３ｃ及びその上に形成された突起電極１４
の第２電極部１４ｃは千鳥状に配置されている。このよ
うに千鳥状に配置する理由は、言うまでもなく、第２電
極部１４ｃの間隔を広げてピッチをかせぐためである。1A and 1B show a main part of a semiconductor device according to an embodiment of the present invention. In these drawings, the same portions as those in FIGS. 6A and 6B are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In this embodiment, an insulating film 7 and a protective film 1 formed on the insulating film 7 are formed.
1 form an insulating layer. An opening 12 is formed in a portion of the protective film 11 corresponding to the opening 8 of the insulating film 7. From the upper surface of the connection pad 5 to a predetermined portion of the upper surface of the protective film 11 on the element formation region 2, the first
A base metal layer (wiring) 13 including a connection pad 13a, a lead line 13b, and a second connection pad 13c is formed, and a projection electrode 14 is formed on an upper surface of the base metal layer 13. In this case, the protruding electrode 14 includes a first electrode portion 14a formed on the first connection pad portion 13a, a leading line portion 14b formed on the leading line portion 13b,
Second electrode portion 14 formed on second connection pad portion 13c
c. Further, the size of the second connection pad portion 13c of the base metal layer 13 is almost four times the size of the connection pad 5, so that the size of the second electrode portion 14c of the bump electrode 14 is formed on the connection pad 5. The size of the first electrode portion 14a, that is, approximately four times the size of the connection pad 5. Further, the second connection pad portion 13c of the base metal layer 13 and the bump electrode 14 formed thereon are formed.
Are arranged in a zigzag pattern. Needless to say, the reason for arranging in a staggered manner is to increase the interval between the second electrode portions 14c to increase the pitch.

【０００７】このように、この半導体装置では、素子形
成領域２上における保護膜１１上に下地金属層１３の一
部からなる第２接続パッド部１３ｃを形成し、この第２
接続パッド部１３ｃ上に突起電極１４の第２電極部１４
ｃを形成しているので、この第２電極部１４ｃを実質的
な突起電極として使用することができることになる。こ
の場合、突起電極１４の第２電極部１４ｃのサイズは接
続パッド５のサイズのほぼ４倍となっており、また突起
電極１４の第２電極部１４ｃは千鳥状に配置されている
ので、突起電極１４の数が増大しても、実質的な突起電
極として使用する第２電極部１４ｃのサイズ及びピッチ
を大きくすることができる。As described above, in this semiconductor device, the second connection pad portion 13c composed of a part of the base metal layer 13 is formed on the protective film 11 on the element formation region 2, and the second connection pad portion 13c is formed.
The second electrode portion 14 of the bump electrode 14 is provided on the connection pad portion 13c.
Since c is formed, the second electrode portion 14c can be used as a substantial protruding electrode. In this case, the size of the second electrode portion 14c of the projecting electrode 14 is substantially four times the size of the connection pad 5, and the second electrode portions 14c of the projecting electrode 14 are arranged in a staggered manner. Even if the number of the electrodes 14 increases, the size and pitch of the second electrode portion 14c used as a substantial protruding electrode can be increased.

【０００８】次に、この半導体装置の製造方法につい
て、図２を参照しながら説明する。まず、図２（Ａ）に
示すように、シリコン基板１上に形成された酸化シリコ
ン等からなる絶縁膜３上にアルミニウムやアルミニウム
合金等からなる配線パターン４、接続パッド５及び引き
回し線６が形成され、その上面の接続パッド５の中央部
を除く部分に酸化シリコンや窒化シリコン等からなる保
護膜７が形成され、接続パッド５の中央部が保護膜７に
形成された開口部８を介して露出されたものを用意す
る。Next, a method for manufacturing the semiconductor device will be described with reference to FIG. First, as shown in FIG. 2A, a wiring pattern 4 made of aluminum, an aluminum alloy, or the like, a connection pad 5, and a lead wire 6 are formed on an insulating film 3 made of silicon oxide or the like formed on a silicon substrate 1. Then, a protective film 7 made of silicon oxide, silicon nitride, or the like is formed on the upper surface except for the central portion of the connection pad 5, and the central portion of the connection pad 5 is formed through an opening 8 formed in the protective film 7. Prepare the exposed one.

【０００９】次に、図２（Ｂ）に示すように、絶縁膜７
の開口部８に連続する開口部１２を有するポリイミド等
からなる保護膜１１を形成する。この場合、上面全体に
保護膜１１をスピンコートにより形成した後、フォトリ
ソグラフィにより開口部１２を形成する。これの一つの
例として、感光性ポリイミドを被覆した後フォトマスク
を介して露光し、その後現像する方法がある。次に、上
面全体に下地金属層（配線）形成用層２１を形成する。
この下地金属層形成用層２１は、チタン−タングステン
（Ｔｉ−Ｗ）、白金−チタン（Ｐｔ−Ｔｉ）、パラジウ
ム−チタン（Ｐｄ−Ｔｉ）等の合金、すなわちバリアメ
タルと接着メタルとの合金からなる下層と、この下層の
上面に形成された金（Ａｕ）薄膜とからなっている。こ
の場合、下層及び金薄膜は共にスパッタにより成膜され
る。ここで、この状態における各膜厚の一例について説
明すると、配線パターン４、接続パッド５及び引き回し
線６は１〜１．５μｍ程度、絶縁膜７は１〜２μｍ程
度、保護膜１１は１０μｍ程度、下地金属層形成用層２
１は０．２〜１μｍ程度となっている。[0009] Next, as shown in FIG.
A protective film 11 made of polyimide or the like having an opening 12 continuous with the opening 8 is formed. In this case, after the protective film 11 is formed on the entire upper surface by spin coating, the opening 12 is formed by photolithography. As one example of this, there is a method in which a photosensitive polyimide is coated, exposed through a photomask, and then developed. Next, a base metal layer (wiring) forming layer 21 is formed on the entire upper surface.
The base metal layer forming layer 21 is made of an alloy such as titanium-tungsten (Ti-W), platinum-titanium (Pt-Ti), palladium-titanium (Pd-Ti), that is, an alloy of a barrier metal and an adhesive metal. And a gold (Au) thin film formed on the upper surface of the lower layer. In this case, both the lower layer and the gold thin film are formed by sputtering. Here, an example of each film thickness in this state will be described. The wiring pattern 4, the connection pad 5, and the wiring 6 are about 1 to 1.5 μm, the insulating film 7 is about 1 to 2 μm, the protective film 11 is about 10 μm, Base metal layer forming layer 2
1 is about 0.2 to 1 μm.

【００１０】次に、保護膜１１の上面の図１に示す突起
電極１０を形成すべき部分を除く部分にメッキレジスト
層２２を形成する。したがって、この状態では、図１に
示す突起電極１０を形成すべき部分におけるメッキレジ
スト層２２には開口部２３が形成されている。次に、下
地金属層形成用層２１をメッキ電流路として金の電解メ
ッキを行うことにより、メッキレジスト層２２の開口部
２３内の下地金属層形成用層２１の上面に突起電極１４
を形成する。次に、メッキレジスト層２２を剥離し、次
いで突起電極１４をマスクとして下地金属層形成用層２
１の不要な部分をエッチングして除去すると、図１
（Ｂ）に示すように、突起電極１４下に下地金属層１３
が形成される。Next, a plating resist layer 22 is formed on a portion of the upper surface of the protective film 11 except for a portion where the bump electrode 10 shown in FIG. 1 is to be formed. Therefore, in this state, an opening 23 is formed in the plating resist layer 22 in a portion where the protruding electrode 10 shown in FIG. 1 is to be formed. Next, gold electroplating is performed using the underlying metal layer forming layer 21 as a plating current path, so that the bump electrode 14 is formed on the upper surface of the underlying metal layer forming layer 21 in the opening 23 of the plating resist layer 22.
To form Next, the plating resist layer 22 is peeled off, and then the base metal layer forming layer 2 is formed using the bump electrodes 14 as a mask.
1 is removed by etching unnecessary portions, and FIG.
As shown in (B), the underlying metal layer 13
Is formed.

【００１１】ところで、このようにして得られた半導体
装置では、突起電極１４及び下地金属層１３下に１０μ
ｍ程度と比較的厚めの保護膜１１が形成されているの
で、突起電極１４のうち実質的な突起電極となる第２電
極部１４ｃを素子形成領域２上に形成しても、ボンディ
ング時における衝撃を保護膜１１によって吸収すること
ができる。したがって、ボンディング時における衝撃に
より、シリコン基板１における素子形成領域２中の半導
体素子がダメージを受けないようにすることができる。By the way, in the semiconductor device thus obtained, 10 μm is formed under the bump electrode 14 and the underlying metal layer 13.
Since the protective film 11 having a relatively large thickness of about m is formed, even if the second electrode portion 14c which is a substantial protruding electrode among the protruding electrodes 14 is formed on the element formation region 2, the impact at the time of bonding does not occur. Can be absorbed by the protective film 11. Therefore, it is possible to prevent the semiconductor elements in the element formation region 2 in the silicon substrate 1 from being damaged by the impact at the time of bonding.

【００１２】次に、図３（Ａ）〜（Ｃ）はそれぞれこの
発明の他の実施例における半導体装置の各製造工程を示
したものである。そこで、これらの図を順に参照しなが
ら、この実施例における半導体装置の構造についてその
製造方法と併せ説明する。まず、図３（Ａ）に示すよう
に、図２（Ａ）に示すものと同じものを用意する。した
がって、図３（Ａ）において、図２（Ａ）と同一部分に
は同一の符号を付し、その説明を省略する。Next, FIGS. 3A to 3C show respective manufacturing steps of a semiconductor device according to another embodiment of the present invention. Therefore, the structure of the semiconductor device in this embodiment will be described together with its manufacturing method with reference to these drawings in order. First, as shown in FIG. 3A, the same one as shown in FIG. 2A is prepared. Therefore, in FIG. 3A, the same portions as those in FIG. 2A are denoted by the same reference numerals, and description thereof will be omitted.

【００１３】次に、図３（Ｂ）に示すように、絶縁膜７
の開口部８に連続する開口部３１を有するポリイミド等
からなる保護膜３２を形成する。この場合、上面全体に
保護膜３２をスピンコートにより形成した後、フォトリ
ソグラフィにより開口部３１を形成する。次に、両開口
部８、３１を介して露出された接続パッド５を含む保護
膜３２の上面にアルミニウムやアルミニウム合金等から
なる配線パターン（配線）３３を形成する。この場合、
配線パターン３３は、図４に示すように、素子形成領域
２上にも形成され、接続パッド５上に形成された第１接
続パッド部３３ａと、素子形成領域２上に形成された第
２接続パッド部３３ｂと、両接続パッド部３３ａ、３３
ｂ間に形成された引き回し線部３３ｃとからなってい
る。また、第２接続パッド部３３ｂのサイズ及びピッチ
は接続パッド５のサイズ及びピッチよりも大きくなって
いる。つまり、配線パターン３３は、後述する突起電極
３９が形成される第２接続パッド部３３ｂが、隣接する
接続パッド５に接続された配線パターン３３の第２接続
パッド部３３ｂとは異なる行または列に配置されるよう
に、側辺部に配列された接続パッド５よりも大きいサイ
ズ及びピッチに形成されている。Next, as shown in FIG.
A protective film 32 made of polyimide or the like having an opening 31 continuous with the opening 8 is formed. In this case, after the protective film 32 is formed on the entire upper surface by spin coating, the opening 31 is formed by photolithography. Next, a wiring pattern (wiring) 33 made of aluminum, an aluminum alloy, or the like is formed on the upper surface of the protective film 32 including the connection pads 5 exposed through the openings 8 and 31. in this case,
As shown in FIG. 4, the wiring pattern 33 is also formed on the element formation region 2, and the first connection pad 33 a formed on the connection pad 5 and the second connection pad 33 formed on the element formation region 2. Pad portion 33b and both connection pad portions 33a, 33
and a lead line portion 33c formed between b. The size and pitch of the second connection pad portion 33b are larger than the size and pitch of the connection pad 5. That is, the wiring pattern 33 is such that the second connection pad portion 33b on which the projecting electrode 39 described later is formed is in a different row or column from the second connection pad portion 33b of the wiring pattern 33 connected to the adjacent connection pad 5. The connection pads 5 are formed in a larger size and a larger pitch than the connection pads 5 arranged on the side portions so as to be arranged.

【００１４】次に、保護膜３２の上面の第２接続パッド
部３３ｂの部分を除く部分にオーバーコート膜３４を形
成する。したがって、この状態では、第２接続パッド部
３３ｂに対応する部分におけるオーバーコート膜３４に
は開口部３５が形成されている。この場合、オーバーコ
ート膜３４の材質は、ポリイミド等の有機材であっても
よく、また酸化シリコンや窒化シリコン等の無機材であ
ってもよい。次に、上面全体に下地金属層形成用層３６
を形成する。次に、下地金属層形成用層３６の上面の第
２接続パッド部３３ｂに対応する部分を除く部分にメッ
キレジスト層３７を形成する。したがって、この状態で
は、第２接続パッド部３３ｂに対応する部分におけるメ
ッキレジスト層３７には開口部３８が形成されている。
次に、下地金属層形成用層３６をメッキ電流路として金
の電解メッキを行うことにより、メッキレジスト層３７
の開口部３８内の下地金属層形成用層３６の上面に突起
電極３９を形成する。次に、図３（Ｃ）に示すように、
メッキレジスト層３７を剥離し、次いで突起電極３９を
マスクとして下地金属層形成用層３６の不要な部分をエ
ッチングして除去すると、突起電極３９下に下地金属層
４０が形成される。この状態の平面図を図５に示す。Next, an overcoat film 34 is formed on a portion of the upper surface of the protective film 32 other than the second connection pad portion 33b. Therefore, in this state, an opening 35 is formed in the overcoat film 34 in a portion corresponding to the second connection pad portion 33b. In this case, the material of the overcoat film 34 may be an organic material such as polyimide or an inorganic material such as silicon oxide or silicon nitride. Next, the base metal layer forming layer 36 is formed on the entire upper surface.
To form Next, a plating resist layer 37 is formed on a portion of the upper surface of the base metal layer forming layer 36 other than a portion corresponding to the second connection pad portion 33b. Therefore, in this state, an opening 38 is formed in the plating resist layer 37 at a portion corresponding to the second connection pad portion 33b.
Next, gold plating is performed by using the base metal layer forming layer 36 as a plating current path, so that the plating resist layer 37 is formed.
A protruding electrode 39 is formed on the upper surface of the base metal layer forming layer 36 in the opening 38 of FIG. Next, as shown in FIG.
The plating resist layer 37 is peeled off, and then unnecessary portions of the base metal layer forming layer 36 are removed by etching using the bump electrodes 39 as a mask, thereby forming a base metal layer 40 under the bump electrodes 39. FIG. 5 shows a plan view of this state.

【００１５】このようにして得られた半導体装置では、
配線パターン３３の一部からなる第２接続パッド部３３
ｂ上のみに下地金属層４０を介して突起電極３９が形成
されることになるので、オーバーコート膜３４上には実
質的な突起電極３９のみが突出されることになる。した
がって、図１（Ａ）及び（Ｂ）に示す半導体装置の場合
と比較して、突起電極３９の材料である高価な金の使用
を少なくすることができる。In the semiconductor device thus obtained,
Second connection pad portion 33 formed of a part of wiring pattern 33
Since the protruding electrode 39 is formed only on “b” via the base metal layer 40, only the substantially protruding electrode 39 protrudes on the overcoat film 34. Therefore, compared to the case of the semiconductor device shown in FIGS. 1A and 1B, it is possible to reduce the use of expensive gold which is a material of the bump electrode 39.

【００１６】なお、上記実施例では、突起電極を金メッ
キによって形成した場合について説明したが、これに限
らず、半田メッキによって形成するようにしてもよい。
また、上記実施例では、突起電極を有する半導体装置に
ついて説明したが、半導体装置を基板上にワイヤボンデ
ィングする場合には、突起電極は不要である。そこで、
半導体装置を基板上にワイヤボンディングする場合に
は、例えば図３（Ｂ）を参照しながら説明すると、オー
バーコート膜３４を形成した状態において工程を終了す
る。すると、オーバーコート膜３４の開口部３５を介し
て配線パターン３３の一部からなる第２接続パッド部３
３ｂが露出された状態となるので、この露出された第２
接続パッド部３３ｂを介して半導体装置を基板上にワイ
ヤボンディングすることになる。In the above embodiment, the case where the protruding electrodes are formed by gold plating has been described. However, the present invention is not limited to this, and they may be formed by solder plating.
Further, in the above embodiment, the semiconductor device having the protruding electrode has been described. However, when the semiconductor device is wire-bonded on the substrate, the protruding electrode is unnecessary. Therefore,
When the semiconductor device is wire-bonded to the substrate, for example, referring to FIG. 3B, the process is completed with the overcoat film 34 formed. Then, the second connection pad portion 3 formed of a part of the wiring pattern 33 through the opening 35 of the overcoat film 34
3b is exposed, so that the exposed second
The semiconductor device is wire-bonded to the substrate via the connection pad 33b.

【００１７】[0017]

【発明の効果】以上説明したように、この発明によれ
ば、周縁部に配列された各接続パッドに接続された配線
を絶縁膜上に引き回し、素子形成領域上に対応する箇所
を前記接続パッドよりも大きいサイズの接続パッド部と
なし、前記配線の接続パッド部を、隣接する前記接続パ
ッドに接続された配線の接続パッド部とは異なる行また
は列に配置されるように、側辺部に配列された前記接続
パッドよりも大きいピッチでマトリックス状に配列し、
少なくとも前記接続パッド上に前記接続パッドより大き
いサイズの突起電極を形成したので、突起電極の数が増
大しても、突起電極のサイズ及びピッチを大きくするこ
とができる。As described above, according to the present invention, the wiring connected to each of the connection pads arranged on the peripheral portion is routed on the insulating film, and the portion corresponding to the element forming region is formed on the connection pad. A connection pad part having a larger size than the connection pad part of the wiring, and the connection pad part of the wiring is arranged in a different row or column from the connection pad part of the wiring connected to the adjacent connection pad. Arranged in a matrix at a pitch greater than the arranged connection pads,
Since the projecting electrode having a size larger than the connection pad is formed at least on the connection pad, the size and pitch of the projecting electrode can be increased even if the number of the projecting electrodes increases.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（Ａ）はこの発明の一実施例における半導体装
置の要部を示す平面図、（Ｂ）はそのＢ−Ｂ線に沿う断
面図。FIG. 1A is a plan view illustrating a main part of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line BB.

【図２】（Ａ）及び（Ｂ）はそれぞれ図１に示す半導体
装置の各製造工程を説明するために示す図１（Ｂ）同様
の断面図。FIGS. 2A and 2B are cross-sectional views similar to FIG. 1B for explaining respective manufacturing steps of the semiconductor device shown in FIG. 1;

【図３】（Ａ）〜（Ｃ）はそれぞれこの発明の他の実施
例における半導体装置の各製造工程を説明するために示
す図１（Ｂ）同様の断面図。FIGS. 3A to 3C are cross-sectional views similar to FIG. 1B for explaining respective manufacturing steps of a semiconductor device in another embodiment of the present invention.

【図４】図３（Ｂ）に示す状態のうち配線パターンを形
成した後の状態の平面図。FIG. 4 is a plan view of the state shown in FIG. 3B after a wiring pattern is formed;

【図５】図３（Ｃ）に示す状態の平面図。FIG. 5 is a plan view of the state shown in FIG.

【図６】（Ａ）は従来の半導体装置の一部を示す平面
図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。FIG. 6A is a plan view showing a part of a conventional semiconductor device, and FIG. 6B is a cross-sectional view along the line BB.

【符号の説明】[Explanation of symbols]

１ シリコン基板 ２ 素子形成領域 ５ 接続パッド ７ 絶縁膜 ８ 開口部 ３１ 開口部 ３２ 保護膜 ３３ 配線パターン ３３ａ 第１接続パッド部 ３３ｂ 第２接続パッド部 ３３ｃ 引き回し線部 ３４ オーバーコート膜 ３５ 開口部 ３９ 突起電極 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element formation area 5 Connection pad 7 Insulating film 8 Opening 31 Opening 32 Protective film 33 Wiring pattern 33a First connection pad part 33b Second connection pad part 33c Leading line part 34 Overcoat film 35 Opening 39 Projection electrode

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭52−8785（ＪＰ，Ａ) 特開 昭64−1257（ＪＰ，Ａ) 特開 平３−159152（ＪＰ，Ａ) 特開 平５−218042（ＪＰ，Ａ) 特開 平５−343408（ＪＰ，Ａ) 特開 平７−183425（ＪＰ，Ａ) 実開 昭63−38328（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-52-8785 (JP, A) JP-A-64-1257 (JP, A) JP-A-3-159152 (JP, A) JP-A-5-85 218042 (JP, A) JP-A-5-343408 (JP, A) JP-A-7-183425 (JP, A) JP-A-63-138328 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60

Claims (10)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体基板上の中央部が素子形成領域と
され、周縁部の少なくとも相対向する一対の側辺部に接
続パッドが所定ピッチで配列された半導体装置におい
て、前記半導体基板の上面全体に前記各接続パッドを露
出する開口部を有する絶縁層が形成され、前記絶縁層上
に引き回され、前記半導体基板の素子形成領域上に対応
して前記接続パッドよりも大きいサイズの接続パッド部
を有し且つ前記絶縁膜の開口部を介して前記接続パッド
に接続される複数の配線が形成され、少なくとも前記各
配線の前記接続パッド上に前記接続パッドより大きいサ
イズの突起電極が形成されており、前記配線の接続パッ
ド部は、隣接する前記接続パッドに接続された配線の接
続パッド部とは異なる行または列に配置されるように、
側辺部に配列された前記接続パッドよりも大きいピッチ
でマトリックス状に配列されていることを特徴とする半
導体装置。1. A semiconductor device in which a central portion on a semiconductor substrate is an element forming region, and connection pads are arranged at a predetermined pitch on at least a pair of side edges of a peripheral portion of the semiconductor substrate. An insulating layer having an opening for exposing each of the connection pads is formed, routed on the insulating layer, and has a size larger than the connection pad corresponding to the element formation region of the semiconductor substrate. And a plurality of wirings connected to the connection pad through an opening of the insulating film are formed, and a projection electrode having a size larger than the connection pad is formed on at least the connection pad of each of the wirings. The connection pad part of the wiring is arranged in a different row or column from the connection pad part of the wiring connected to the adjacent connection pad,
A semiconductor device, wherein the semiconductor devices are arranged in a matrix at a larger pitch than the connection pads arranged on a side portion. 【請求項２】 請求項１記載の発明において、前記突起
電極は、その高さ全体にわたりほぼ同一径の円柱状であ
ることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said protruding electrode has a columnar shape having substantially the same diameter over the entire height thereof. 【請求項３】 請求項２記載の発明において、前記突起
電極は、その上面が平坦であることを特徴とする半導体
装置。3. The semiconductor device according to claim 2, wherein the bump electrode has a flat upper surface. 【請求項４】 請求項１または２記載の発明において、
前記絶縁層及び前記各配線の前記接続パッド部を除く部
分が有機材からなるオーバーコート膜で被覆されている
ことを特徴とする半導体装置。4. The invention according to claim 1 or 2,
A semiconductor device, wherein portions of the insulating layer and the respective wirings other than the connection pad portions are covered with an overcoat film made of an organic material. 【請求項５】 請求項１または２記載の発明において、
前記絶縁層は有機材からなる絶縁膜を含むことを特徴と
する半導体装置。5. The method according to claim 1, wherein
The semiconductor device, wherein the insulating layer includes an insulating film made of an organic material. 【請求項６】 半導体基板上の中央部が素子形成領域と
され、周縁部の少なくとも相対向する一対の側辺部に接
続パッドが所定ピッチで配列された半導体装置の製造方
法において、前記半導体基板の上面全体に前記各接続パ
ッドを露出する開口部を有する絶縁層を形成する工程
と、前記絶縁層上に引き回され、前記半導体基板の素子
形成領域上に対応して前記接続パッドよりも大きいサイ
ズの接続パッド部を有し且つ前記絶縁膜の開口部を介し
て前記接続パッドに接続される複数の配線を形成する工
程と、少なくとも前記各配線の前記接続パッド上に前記
接続パッドより大きいサイズの突起電極を形成する工程
とを有し、前記配線形成工程は、前記配線の接続パッド
部が隣接する前記接続パッドに接続された配線の接続パ
ッド部とは異なる行または列に配置されるように、側辺
部に配列された前記接続パッドよりも大きいピッチでマ
トリックス状に配列することを特徴とする半導体装置の
製造方法。6. A method of manufacturing a semiconductor device in which a central portion on a semiconductor substrate is an element formation region, and connection pads are arranged at a predetermined pitch on at least a pair of side edges of a peripheral portion facing each other. Forming an insulating layer having an opening exposing each of the connection pads on the entire upper surface of the semiconductor substrate; and routing the insulating layer over the insulating layer to be larger than the connection pads corresponding to the element formation region of the semiconductor substrate. Forming a plurality of wirings having a connection pad portion of a size and being connected to the connection pad through the opening of the insulating film; and at least a size larger than the connection pad on the connection pad of each of the wirings Forming a projection electrode of the wiring, wherein the wiring forming step is performed in a row in which the connection pad part of the wiring is different from the connection pad part of the wiring connected to the adjacent connection pad. A method of manufacturing a semiconductor device, comprising arranging in a matrix at a larger pitch than the connection pads arranged on the side so as to be arranged in a row. 【請求項７】 請求項６記載の発明において、前記突起
電極の形成工程は、前記絶縁層全体に前記配線形成用の
金属層を形成し、該金属層を電流路とする電解メッキを
行う工程を含むことを特徴とする半導体装置の製造方
法。7. The method according to claim 6, wherein the step of forming the protruding electrode includes the step of forming a metal layer for forming the wiring on the entire insulating layer, and performing electrolytic plating using the metal layer as a current path. A method for manufacturing a semiconductor device, comprising: 【請求項８】 請求項７記載の発明において、前記突起
電極の形成工程は、前記配線形成用の金属層上にメッキ
レジスト層を形成する工程を含み、該メッキレジスト層
の厚さを形成される前記突起電極の高さよりも大きく形
成することを特徴とする半導体装置の製造方法。8. The invention according to claim 7, wherein the step of forming the projecting electrode includes a step of forming a plating resist layer on the metal layer for forming the wiring, wherein the thickness of the plating resist layer is formed. A height of the projection electrode is larger than a height of the projection electrode. 【請求項９】 請求項８記載の発明において、前記突起
電極を形成した後、前記突起電極をマスクとして前記金
属層を除去する工程を含むことを特徴とする半導体装置
の製造方法。9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of removing the metal layer using the bump electrode as a mask after forming the bump electrode. 【請求項１０】 請求項６記載の発明において、前記絶
縁層及び前記各配線の前記接続パッド部を除く部分を有
機材からなるオーバーコート膜で被覆する工程を有する
ことを特徴とする半導体装置の製造方法。10. The semiconductor device according to claim 6, further comprising a step of covering a portion of the insulating layer and each of the wires except for the connection pad portion with an overcoat film made of an organic material. Production method.
JP2000239261A 2000-08-08 2000-08-08 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3279309B2 (en)

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