JPS6226839A - Semiconductor substrate - Google Patents

Abstract

PURPOSE:To eliminate the generation of chippings and cracks in the surface layer and the laminated film of the substrate in a dicing process and to improve the productivity by a method wherein a trench part to be recessed along the grid line region is formed. CONSTITUTION:A trench part 8, both the end parts of which are formed conforming to both the end parts of the grid line region 7 and whose section is a recessed form, is formed in the grid line region 7. First a resist mask is formed by a photolithography technique, then an etching is continuously performed on a passivation film 5 and the surface part of an Si substrate 1 by a Freon gas-using anisotropic RIE method and the trench part 8 is formed in the grid line region 7. By this way, the spread of the mechanical vibrations and so forth due to the dicing blade to the chip in the dicing process is sufficiently reduced and the cutting strain is relaxed. As a result, the generation of cracks or chippings to spread to the surface layer from the chip side surfaces (dicing surfaces) is suppressed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor substrate, and particularly to a region where chips are cut out from an S1 wafer (hereinafter referred to as a grid line region).
related to the processing structure.

[Conventional technology]

When semiconductor elements are fabricated on a St wafer through processes such as diffusion and photoetching, a large number of identical elements are regularly arranged within one wafer. Then, in order to incorporate these elements into a package, they are cut out and divided into individual chips.

Conventionally, as shown in FIG. 5, the grid line region 7 for cutting out chips from the ST wafer is formed by selectively etching away a laminated film, for example, an insipation film 5, on the silicon substrate 1. Ta. Further, this grid line area 7 was not subjected to any processing. In the figure, 2 is a field oxide film, 3 is an intermediate insulating film, and 4 is a conductor wiring, and the semiconductor element on each chip is formed using these as constituent elements.

The chips are cut out by positioning the dicing blade on the scribe line a and then rotating it at high speed. In this case, in order to increase the number of chips per wafer, it is desirable to make the width of the grid line area as narrow as possible, but in order to suppress cutting distortion during the dicing process and maintain yield and reliability. ,
Normally, a size of about 1OOAWE is not required.

9. In the processing structure of the grid line area, especially in the case of chips mounted on glass packages, moisture intrusion from the outside through cracks etc. that occur during the dicing process is a problem, and this has a large effect on reliability. It is also an important topic that those skilled in the field are working on.

In this way, the conventional dicing process is a technology that will continue to be followed in the future.
As a measure to suppress the occurrence of chipping and cracking in the substrate or laminated film, a grid line area of a certain width or more is required.

[Problem that the invention seeks to solve]

However, until now, reduction of grid line area width,
In addition, a technology that simultaneously satisfies improvement in reliability has not been obtained. That is, in the conventional grid line region processing structure, there is a problem in that chipping or cranking at the contact surface of the dicing blade during the dicing process cannot be suppressed completely, resulting in insufficient yield and reliability. In addition, the setting of the grid line area was originally a hindrance to high-density technology and large-area wafers aimed at improving productivity. As performance improves, the effects of the above-mentioned chipping and cracking on yield and reliability become increasingly large.

Therefore, the present invention has a grid line area processing structure that eliminates the occurrence of chipping and cracking in the St substrate surface layer and laminated film during the dicing process due to the conventional grid line area processing structure described above, and improves productivity. The purpose is to provide semiconductor substrates.

[Means for solving problems]

In the semiconductor substrate according to the present invention, a trench portion recessed along the grid line region is formed to form a subsequent structure.

[Effect]

In the present invention, since the semiconductor substrate has a structure in which a trench portion is formed recessed along the grid line region,
In the dicing process, the spread of mechanical vibration to the surroundings is suppressed, and therefore cutting strain and occurrence of chipping, cracking, etc. in the passivation film on the surface of the Si substrate are suppressed.

〔Example〕

Hereinafter, the present invention will be explained in detail based on the drawings. In the figures, parts corresponding to those in the conventional example are given the same reference numerals.

FIG. 1 shows a first embodiment of the present invention, in which a trench portion having a concave cross section is formed in a grid line region 7 so that its both ends coincide with both ends of the grid line region 7. 8 is formed.

As a manufacturing method for forming this first embodiment, first a resist mask (not shown) is formed by photolithography, and then an anisotropic R is formed using a fluorocarbon gas.
The surface portions of the passivation film 5 and the St substrate 1 are continuously etched by IE to form grid line regions 7.
A trench portion 8 is formed therein. This manufacturing method can be implemented without adding any new process to the conventional process.

FIG. 2 is a diagram showing a second embodiment of the present invention, in which trench portions 8 having a concave cross section are formed at a predetermined distance from both ends of a grid line region 70 inwardly. In this manufacturing method, first, as shown in FIG. 2(a), a resist mask 6 is formed by photolithography technology,
Next, as shown in FIG. 2(b), by forcibly overetching the passivation film 5 using an isotropic dry etching technique, an undercut region (b) is formed at the lower part of the side edge of the resist mask 6. area). Next, trench portions 8 are formed in the grid line region 7 by subjecting the surface portion of the Si substrate 1 to anisotropic dry etching using a fluorocarbon gas through the resist mask 6. Thereafter, when the resist mask 6 is removed, a processed structure having the cross-sectional shape shown in FIG. 2(e) is obtained. This manufacturing method can also be implemented without adding a new process to the conventional process.

Note that, as shown in FIG. 2(b), an undercut region (region b) is formed by isotropic dry etching, and based on this undercut amount, both ends of the trench portion 8 and both ends of the grid line region 7 are formed. To set the distance from
Limits arise on their own. Therefore, in order to further arbitrarily set this distance, for example, the third method of the present invention as shown in FIG.
The manufacturing method of the embodiment may be used. That is, first, as shown in FIG. 3(a), after removing a required portion of the /4' ossification film 5 by etching to form a grid line region 7 (passivation photolithography/etching process), both ends of this grid line region 7 are removed. To cover the top surface as well,
A resist mask 6 is formed. Next, as shown in FIG. 3(b), by subjecting the Sl substrate 1 to anisotropic dry etching, a trench portion having a concave cross section is formed by placing an arbitrary distance inward from both ends of the grid line region 7. is formed (
Gridline Photolin Fist Etching Process). In this way, this manufacturing method is different from conventional passivation photolithography.
After the etching process, a new grid line photolithography
An etching process has been introduced.

FIG. 4 shows a fourth embodiment, in which the trench portion 8 is constituted by two trench portions formed at a predetermined interval in the grid line region 7. In this manufacturing method, first, as shown in FIG. 4(a), a resist mask 6 having two line-shaped cutouts 6' on the grid line region 7 is formed. Next, by performing anisotropic dry etching using a fluorocarbon gas through this resist mask 6, the Sl substrate 1 is etched.
A trench portion 8 consisting of two trenches is formed in the grid line region 7 . Then, when the resist mask 6 is removed, a cross-sectional shape shown in FIG. 4(b) is obtained. In this case, it is desirable that the cutout portions 6' of the resist mask 602 be formed at a certain distance from both ends of the grid line region 7.

This manufacturing method is also the same as that shown in Figure 3 above.
This can be carried out by completely introducing a new grid line photolithography/etching process after the conventional passivation photolithography/etching process.

According to the fourth embodiment, since the trench portions 8 are provided in the vicinity of both ends of the grid line region 70, there is an effect that mechanical vibrations, especially to the chips, are reduced when cutting with a dicing blade. Chiru.

Three representative embodiments of the present invention have been described above, and by providing the trench portion 8, positioning to the scribe line a in the dicing process is facilitated 9, and the occurrence of cutting strain temples is suppressed. Therefore, the width of the grid line area 7 is changed from the conventional 100μ? It can be significantly reduced from about n to about 1/2 of that.

〔Effect of the invention〕

As described above in detail, the present invention employs a semiconductor substrate structure in which the trench portion 8 is formed along the grid line region 7, so that mechanical vibrations caused by the dicing blade are not affected by ticks in the dicing process. Since the cutting strain is sufficiently reduced, surface layer cracking or chipping from the chip side surface (dicing surface) is suppressed.

Therefore, the yield of chips in the dicing process can be improved, and the reliability of the chips, especially the reliability of chips mounted on glass packages, which are excellent in economic efficiency, can be improved.

Since the width of the grid line region can be reduced, there is also the effect that productivity can be improved due to higher integration of chips and larger area of wafers.

Note that the above effect can be further enhanced by forming the trench portion 8 at a certain distance from both ends of the grid line region 7, and by increasing the number of trenches constituting the trench portion 8. I can do it.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of the main parts explaining the first embodiment of the present invention and the manufacturing method thereof, and Fig. 4 is a cross-sectional view of the main parts explaining the tenth embodiment of the present invention and the manufacturing method thereof. , FIG. 5 is a similar sectional view of the main part showing a conventional example. ■...Si substrate, 5...9 Tension film, 6
...Resist mask, 6'...<) Cutout, 7...
- Grid line area, 8...trench part. J's spear is 'l'I + phantom decoy 3rd cause for the dented 3rd laughter to the tree

Claims (4)

[Claims] (1) A semiconductor substrate provided with a grid line region for chip cutting, characterized in that a trench portion recessed along the grid line region is formed. (2) The semiconductor substrate according to claim 1, wherein the trench portion is constituted by one trench, and both ends of the trench portion are formed to coincide with both ends of the grid line region. (3) The semiconductor substrate according to claim 1, wherein the trench portion is constituted by one trench and is formed at a predetermined distance inward from both ends of the grid line region. (4) The trench portion is constituted by two trenches near both ends of the grid line.
Semiconductor substrate as described in section.