JPS63300508A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPS63300508A
JPS63300508A JP62137242A JP13724287A JPS63300508A JP S63300508 A JPS63300508 A JP S63300508A JP 62137242 A JP62137242 A JP 62137242A JP 13724287 A JP13724287 A JP 13724287A JP S63300508 A JPS63300508 A JP S63300508A
Authority
JP
Japan
Prior art keywords
semiconductor chip
main surface
resin
chamfering
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62137242A
Other languages
Japanese (ja)
Inventor
Toshiyuki Sakuma
敏幸 佐久間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62137242A priority Critical patent/JPS63300508A/en
Publication of JPS63300508A publication Critical patent/JPS63300508A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent generation of cracks and improve reliability of resin package and semiconductor chip by alleviating concentration of stress of resin by conducting the chamfering to the edge of main surface of semiconductor chip. CONSTITUTION:A semiconductor chip 1 in which the edge of main surface is chamfered is included. The chamfering 2 with the chamfering angle theta of 30-70 deg. is conducted to the edge of main surface of semiconductor chip 1. For this chamfering, a dicing blade with top angle of 20 is used and a semiconductor chip 1 obtained by cutting the wafer to which the groove is formed in the depth of about 200mum is also used.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

従来の樹脂封止型半導体装置は内部の半導体チップの主
面端部の四辺には面取りが施されていなかった。In conventional resin-sealed semiconductor devices, the four edges of the main surface of the internal semiconductor chip are not chamfered.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の樹脂封止型半導体装置は、内部の半導体
チップの四辺に面取りが施されていないので、樹脂封止
後に半導体チップ周辺の角部に応力が集中し、温度サイ
クルやプレッシャクッ力試験において上述の角部から樹
脂にクラックが発生したり、また半導体チップにクラッ
クが発生し著しく信頼性が悪化するという欠点がある。In the conventional resin-sealed semiconductor device described above, the four sides of the internal semiconductor chip are not chamfered, so stress concentrates on the corners around the semiconductor chip after resin-sealing, and the temperature cycle and pressure cracking force test However, there are disadvantages in that cracks occur in the resin from the above-mentioned corners, and cracks occur in the semiconductor chip, resulting in a significant deterioration in reliability.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の樹脂封止型半導体装置は、主面端部が面取りさ
れた半導体チップを有しているというものである。The resin-sealed semiconductor device of the present invention includes a semiconductor chip with a chamfered main surface end.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の第１の実施例の断面図である。半導体
チップ１の主面端部に面取り角θが３０〜７０°の面取
り２が施されている。この面取りを行うには頂角２θの
ダイシング刃を使い、深さ２００μｍ程度の深さまでウ
ェーハに溝を形成したものを切断した半導体チップを使
用している。FIG. 1 is a sectional view of a first embodiment of the invention. A chamfer 2 with a chamfer angle θ of 30 to 70° is provided at the end of the main surface of the semiconductor chip 1. To perform this chamfering, a dicing blade with an apex angle of 2θ is used to cut a semiconductor chip into which a groove is formed in the wafer to a depth of about 200 μm.

第２図は、本発明の第２の実施例の主要部を示すリード
フレームに搭載した半導体チップ部分の断面図である。FIG. 2 is a sectional view of a semiconductor chip mounted on a lead frame showing the main part of a second embodiment of the present invention.

この実施例は面取り２′部分の形状が第１の実施例と異
なっている。これは面取りをエツチングで行ったもので
ある。This embodiment differs from the first embodiment in the shape of the chamfered portion 2'. This is a chamfer made by etching.

第３図（ａ＞、（ｂ）は第２の実施例の製造方法を説明
するための工程順に配列したウェーハの断面図である。FIGS. 3(a) and 3(b) are cross-sectional views of wafers arranged in the order of steps for explaining the manufacturing method of the second embodiment.

まず、第３図（ａ）に示すように、スクライブ予定部８
のみを露出するように一般的な光リソグラフィー技術に
よりウェーハ７上にレジストマスク８を形成する。次に
、第３図（ｂ）に示すように、レジストマスク８をマス
クにしてエツチングを行い深さ２０〜７０μｍ、好まし
くは５０μｍの溝９を形成し、レジストマスク８を剥離
後、ウェーハをスクラブ予定部に沿って切断しペレッタ
イズすると第２図に示すような面取りされた半導体チッ
プを得ることができる。First, as shown in FIG. 3(a), the area to be scribed 8
A resist mask 8 is formed on the wafer 7 by a general photolithography technique so as to expose only the wafer 7. Next, as shown in FIG. 3(b), etching is performed using the resist mask 8 as a mask to form a groove 9 with a depth of 20 to 70 μm, preferably 50 μm, and after peeling off the resist mask 8, the wafer is scrubbed. By cutting along the planned portions and pelletizing, a chamfered semiconductor chip as shown in FIG. 2 can be obtained.

なお、エツチングにはＨＦ　：　ＨＮＯｓ　＝１　：　
２０のエツチング液を使用したが、ＣＦ４と０２の混合
気体を使用したプラズマエツチングでも第２図（ｂ）に
類似したエツチング断面形状を得ることができる。In addition, for etching, HF:HNOs=1:
Although an etching solution of No. 20 was used, an etched cross-sectional shape similar to that shown in FIG. 2(b) can also be obtained by plasma etching using a mixed gas of CF4 and 02.

なお、以上の実施例において、面取りは半導体主面端部
の全て（平面形状が四辺形なら全ての辺）に施す必要は
ないが、少なくとも相対する二辺に施すのが望しい。In the above embodiments, although it is not necessary to chamfer all of the edges of the main surface of the semiconductor (all sides if the planar shape is quadrilateral), it is preferable to chamfer at least two opposing sides.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体チップの主面端部
に面取りが施されているので、樹脂による応力集中が緩
和され、樹脂パッケージや半導体チップのクラックが発
生せず信頼性の向上がもたらされる効果がある。As explained above, in the present invention, since the edges of the main surface of the semiconductor chip are chamfered, stress concentration due to the resin is alleviated, and cracks do not occur in the resin package or the semiconductor chip, resulting in improved reliability. It has the effect of

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の主要部を示すリードフレームに搭載
した半導体チップ部分の断面図、第３図（ａ）、（ｂ）
は第２の実施例の製造方法を説明するための工程順に配
列したウェーハの断面図である。 １．１−１．１−２・・・半導体チップ、３・・・ボン
ディング線、４・・・リード、５・・・樹脂パッケージ
、６・・・チップ搭載部、７・・・ウェーハ、８・・・
レジストマスク、９・・・溝。FIG. 1 is a cross-sectional view of a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor chip mounted on a lead frame showing the main part of a second embodiment of the present invention, and FIG. ), (b)
FIG. 3 is a cross-sectional view of wafers arranged in the order of steps for explaining the manufacturing method of the second embodiment. 1.1-1.1-2... Semiconductor chip, 3... Bonding wire, 4... Lead, 5... Resin package, 6... Chip mounting part, 7... Wafer, 8 ...
Resist mask, 9...grooves.

Claims (1)

【特許請求の範囲】[Claims] 主面端部が面取りされた半導体チップを有することを特
徴とする樹脂封止型半導体装置。A resin-sealed semiconductor device comprising a semiconductor chip with a chamfered main surface end.
JP62137242A 1987-05-29 1987-05-29 Resin sealed semiconductor device Pending JPS63300508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62137242A JPS63300508A (en) 1987-05-29 1987-05-29 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62137242A JPS63300508A (en) 1987-05-29 1987-05-29 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS63300508A true JPS63300508A (en) 1988-12-07

Family

ID=15194093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62137242A Pending JPS63300508A (en) 1987-05-29 1987-05-29 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS63300508A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5800931A (en) * 1994-09-29 1998-09-01 Carnegie Mellon University Magnetic recording medium with a MgO sputter deposited seed layer
US6649277B1 (en) 1994-09-29 2003-11-18 Carnegie Mellon University Structure for and method of making magnetic recording media
US8358018B2 (en) 2008-05-07 2013-01-22 Panasonic Corporation Resin sealing structure for electronic component and resin sealing method for electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5800931A (en) * 1994-09-29 1998-09-01 Carnegie Mellon University Magnetic recording medium with a MgO sputter deposited seed layer
US6649277B1 (en) 1994-09-29 2003-11-18 Carnegie Mellon University Structure for and method of making magnetic recording media
US8358018B2 (en) 2008-05-07 2013-01-22 Panasonic Corporation Resin sealing structure for electronic component and resin sealing method for electronic component

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