JPS58218136A - Die collet for semiconductor device - Google Patents
Die collet for semiconductor deviceInfo
- Publication number
- JPS58218136A JPS58218136A JP10059482A JP10059482A JPS58218136A JP S58218136 A JPS58218136 A JP S58218136A JP 10059482 A JP10059482 A JP 10059482A JP 10059482 A JP10059482 A JP 10059482A JP S58218136 A JPS58218136 A JP S58218136A
- Authority
- JP
- Japan
- Prior art keywords
- die
- collet
- notching
- decompression
- size
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置のマウント工程に用いられるダイ
コレットの改良構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improved structure of a die collet used in a semiconductor device mounting process.
近年半導体装置の製造技術は特に顕著な発展を示してい
る。それは64KRAMによって代表される超微細加工
技術の成果によるもので、これらの技術によって形成さ
れた半導体素子(ダイ)の集積度は著しく高いが、それ
に伴ってピン数の割にはチップサイズが拡大されること
も多い。しかるに、ダイを実装し保護するためのパッケ
ージは基板への実装密度を上げるために、ますます小型
化される傾向にある。このノξツケージの小型化は特に
幅方向の縮小が強く要望されており、1974年代には
0.6ミルで適していたものが0.5ミル、0.4ミル
、0.3ミルと市場の要求はきつくなる一途をたどりつ
つある。In recent years, semiconductor device manufacturing technology has shown particularly remarkable development. This is due to the results of ultra-fine processing technology typified by 64KRAM, and although the degree of integration of semiconductor elements (dies) formed using these technologies is extremely high, the chip size has increased in proportion to the number of pins. Often. However, there is a tendency for packages for mounting and protecting dies to become smaller and smaller in order to increase packaging density on substrates. There is a strong demand for the miniaturization of this ξ cage, especially in the width direction, and in 1974, the suitable size of 0.6 mil became available in the market as 0.5 mil, 0.4 mil, and 0.3 mil. The demands are becoming increasingly strict.
従来からダイはリードフレームのアイランドに接着され
、ついでその電極はリードフレームのリードにワイヤボ
ンデングによって接続後にエポキーシレジンでトランス
ファモールドを施して半導体装置が形成されていた。次
にダイをリードフレームに接着させる方法につき詳述す
る。Conventionally, a semiconductor device has been formed by bonding a die to an island of a lead frame, and then connecting its electrodes to the leads of the lead frame by wire bonding, followed by transfer molding with epoxy resin. Next, a method for bonding the die to the lead frame will be described in detail.
リードフレームにダイを例えばはんだで接着させる方法
では予めリードフレームを200〜450℃(はんだの
種類により、また接着剤の種類疋よって異なる)に加熱
し、そのアイランドの中央にはんだを設置する。次に1
第、1図ないし第3図に示すコレット(1)(第1図お
よび第2図はコレットのダイ吸着部を示す)のダイ吸着
部(1a)内にダイ(2)を減圧導入路(1b)によっ
て減圧吸着して保持させ、上記はんだ上に搬送して圧接
させ、スクラブして接着させる。その後ト述の如く、ワ
イヤボンディングからモールディングを経て半導体装置
の形成が達成される゛。In the method of bonding a die to a lead frame with, for example, solder, the lead frame is heated in advance to 200 to 450°C (depending on the type of solder and adhesive), and solder is placed in the center of the island. Next 1
The die (2) is inserted into the vacuum introduction path (1b) in the die adsorption part (1a) of the collet (1) shown in Figs. 1 to 3 (Figs. 1 and 2 show the die adsorption part of the collet). ), the solder is vacuum-adsorbed and held, transported onto the solder, pressed into contact with the solder, and then scrubbed and bonded. Thereafter, as described above, the semiconductor device is formed through wire bonding and molding.
斜上の従来の技術には次にあげろ問題点があった。 The conventional technique of tilting has the following problems.
第4図に示すように、リードフレーム(3)のアイラン
ド(3a)は、これを囲むインナーリード(3b) 。As shown in FIG. 4, the island (3a) of the lead frame (3) is surrounded by inner leads (3b).
(3b)・・・の内端を結んだ域内に低く位置しキャビ
ティ(深さt)を形成する。まだ、インナーリードはボ
ンディング性、信頼性、加工面からその各内端で形成す
る前記キャビティの4隅(4a)〜(4d)が0.5〜
0.8 rrm RK円められそいる。そこで、このキ
ャビティの底にあるアイレンド(3a)にダイ(2)を
マウント(スクラブ接着)させるコレーット(1)は4
角柱型であり、マウントにあたりコレットをスクラブす
る余裕、位置ぎめ精度等を考慮すると第5図に大きさの
み示す(コレットの)ダイ吸着部(1a)の1例のサイ
ズ4.54 m@X 8.20間対し接着できるダイ(
2)は3.35iiX5゜61闘が限度である。しかし
、リードフレームにおけるアイランドの位置をインナー
リードと同じ平面にあるよう処するとワイヤポンディジ
グ性、信頼性に支障を生ずるので、パッケージのサイズ
を変えたり、高価な他の材質のパッケージに変えるなど
する必要があるなどの問題点があった。(3b) A cavity (depth t) is formed in a region connecting the inner ends of... (3b). However, from the viewpoint of bonding performance, reliability, and processing surface, the inner lead has four corners (4a) to (4d) of the cavity formed at each inner end of the inner lead of 0.5 to 0.5.
0.8 rrm RK is about to be rounded. Therefore, the collet (1) for mounting (scrubbing) the die (2) on the eyelend (3a) at the bottom of this cavity is 4
It is a prismatic type, and considering the margin for scrubbing the collet on the mount, the positioning accuracy, etc., the size of an example of the die adsorption part (1a) (of the collet) shown in Figure 5 is 4.54 m @ X 8. .Die that can be bonded between 20 (
For 2), the limit is 3.35ii x 5°61 fights. However, if the island in the lead frame is placed on the same plane as the inner lead, wire bonding performance and reliability will be affected, so it may be necessary to change the size of the package or use a package made of other expensive materials. There were problems such as the need to
この発明はリードフレームに従来よシも大きいサイズの
ダイか接着できるコレットの形状を提供する。The present invention provides a collet shape that can be bonded to a lead frame with a die of a larger size than previously available.
この発明にかかる半導体装置用ダイコレットは、半導体
装置の製麺におけるダイボンディング工程に用いられる
ダイコレットがダイチャック部の角部を切欠いているこ
とを特徴とする。The die collet for semiconductor devices according to the present invention is characterized in that the die collet used in the die bonding process in noodle making of semiconductor devices has a corner portion of the die chuck portion cut out.
〔発明の実施例5
1実施例のダイ1コレツトを第6図ないし第8図に示す
。図において、aυはコレットでそのダイ吸着部(ll
a)内にダイ(2)が減圧導入路(1b)によって減圧
吸着して保持される。ここで、コレットaυは4角柱型
の角部が1例の0.5〜1. 、Q am以下切欠され
た8角柱型をなしている。すなわち、切欠されて生じた
切欠面(llb)、(llb)・・・はこの発明の要部
であり、切欠長さはリードフレームのキャビティの深さ
よりもやや大であればよい。次に、上記切欠面の形状は
必らずしも平面に限られず、曲面に切欠してコレットが
円柱に近い形状であってもよいことは勿論である。なお
、切欠によシ減圧吸着のニアリークの問題は減圧の排気
速度を10チ程度増大することで解決される。[Embodiment 5 of the Invention A die collection of one embodiment is shown in FIGS. 6 to 8. In the figure, aυ is the collet and its die adsorption part (ll
The die (2) is held in a) by being adsorbed under reduced pressure by the reduced pressure introduction path (1b). Here, the collet aυ has a rectangular prism-shaped corner with an example of 0.5 to 1. , Q am has an octagonal prism shape with a notch below. In other words, the notched surfaces (llb), (llb), . . . are essential parts of the present invention, and the notch length may be slightly larger than the depth of the cavity of the lead frame. Next, the shape of the cutout surface is not necessarily limited to a flat surface, and it goes without saying that the collet may be cut into a curved surface so that the collet has a shape close to a cylinder. Incidentally, the problem of near leakage in vacuum adsorption through the notch can be solved by increasing the vacuum pumping speed by about 10 inches.
次にこの発明は上記実施例のリードフレームにつき説明
したが、キャビティを有するセラミックパッケージにつ
いても同様に適用できる。また、切欠の形状はダイが正
方形のとき、コレットの対角線上45°でダイサイズに
合わせて施した例を示したが、これに限られず、ダイが
矩形の場合↑、ダイサイズ、とノぐツケージの関係で2
8°〜45°位の範囲内で適宜選択して実施してよい。Next, although the present invention has been described with respect to the lead frame of the above embodiment, it can be similarly applied to a ceramic package having a cavity. In addition, when the die is square, the notch shape is shown as an example in which the cutout is made at 45 degrees on the diagonal line of the collet according to the die size, but the shape is not limited to this.If the die is rectangular, the die size 2 due to the cage
The angle may be suitably selected within the range of about 8° to 45°.
この発明によれば、従来と同じ大きさのコレットに゛よ
って従、来よりも大きいサイズのダイをマウントできる
という顕著な効果がある。すなわち、背景技術の問題点
の項で第5図によって説明した従来例の寸法のコレット
で・1実施例を示す第9図によって説明する。この場合
、支持しマウントできるダイの寸法は3.74朋X 7
.10 mで、面積で20%程大きくできるというきわ
めて顕著な利点がある。さらに、広くパッケージのサイ
ズとこれに組立可能なダイサイズとの相関を第10図に
従来例と対比して示す。図中(5)は従来、(B)は1
実施例を夫々示す。これによっても方形の一辺について
約7%増大をみている。According to this invention, there is a remarkable effect that a die of a larger size than conventionally can be mounted using a collet of the same size as conventionally. That is, an explanation will be given with reference to FIG. 9, which shows one embodiment of a collet having the dimensions of the conventional example described with reference to FIG. 5 in the section on problems in the background art. In this case, the dimensions of the die that can be supported and mounted are 3.74 x 7
.. 10 m, which has the very remarkable advantage of being about 20% larger in area. Further, FIG. 10 shows the correlation between the package size and the die size that can be assembled into the package, in comparison with the conventional example. In the figure, (5) is conventional, (B) is 1
Examples are shown below. This also results in an increase of approximately 7% on each side of the square.
第1図ないし第3図は従来のコレットにかかり、第1図
は斜視図、第2図は正面図、第3図は第2図のxX′線
に沿う断面図、第4図はリードフレームを説明するだめ
の一部の斜視図、第5図はリードフレームのキャビティ
とコレットとダイとの従来の相関を示す正面図、第6図
ないし第8図は1実施例のコレットにかかり、第6図は
斜視図、第7図は正面図、第8図は第7図のYY′線に
沿う断面図、第9図はリードフレームのキャビティとコ
レットとダイとの1実施例の相関を示す正面図、第10
図はパッケージサイズとダイのサイズとの相関を示す線
図である。
2 ダイ
11 コレット
11a(コレットの)ダイ吸着部
11b(コレット側面の)切欠面
代理人 弁理士 井 上 −男
第 I 図
第 2 図
−3図
:゛:
第 4 図
第 5 図
第 6 図
第 7 図
第8図Figures 1 to 3 show a conventional collet, Figure 1 is a perspective view, Figure 2 is a front view, Figure 3 is a sectional view taken along line xX' in Figure 2, and Figure 4 is a lead frame. FIG. 5 is a front view showing the conventional relationship between the cavity of the lead frame, the collet, and the die, and FIGS. 6 to 8 show the collet of one embodiment, and Fig. 6 is a perspective view, Fig. 7 is a front view, Fig. 8 is a sectional view taken along the line YY' in Fig. 7, and Fig. 9 shows the relationship between the cavity of the lead frame, the collet, and the die in one embodiment. Front view, No. 10
The figure is a diagram showing the correlation between package size and die size. 2 Die 11 Collet 11a (of the collet) Die suction part 11b (of the collet) Notch surface agent Patent attorney Inoue-O No. I Fig. 2 Fig. 3: ゛: Fig. 4 Fig. 5 Fig. 6 Fig. 6 7 Figure 8
Claims (1)
られる角形のダイコレットがダイチャック部の角部を切
欠いていることを特徴とする半導体装置用ダイコレット
。A die collet for semiconductor devices, characterized in that the rectangular die collet used in the die bonding process in the manufacture of semiconductor devices has a corner portion of a die chuck portion cut out.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10059482A JPS58218136A (en) | 1982-06-14 | 1982-06-14 | Die collet for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10059482A JPS58218136A (en) | 1982-06-14 | 1982-06-14 | Die collet for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58218136A true JPS58218136A (en) | 1983-12-19 |
Family
ID=14278193
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10059482A Pending JPS58218136A (en) | 1982-06-14 | 1982-06-14 | Die collet for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58218136A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0715340A3 (en) * | 1994-11-30 | 1998-02-04 | Texas Instruments Incorporated | Improvements in or relating to semiconductor processing |
EP2568782A1 (en) * | 2011-09-12 | 2013-03-13 | Oberthur Technologies | Tool and method for embedding a module in a data carrier |
CN103474385A (en) * | 2013-09-09 | 2013-12-25 | 江阴迪林生物电子技术有限公司 | Chip bonding working table |
FR2998204A1 (en) * | 2012-11-19 | 2014-05-23 | Oberthur Technologies | TOOL FOR INSERTING A MODULE IN A HOUSING |
-
1982
- 1982-06-14 JP JP10059482A patent/JPS58218136A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0715340A3 (en) * | 1994-11-30 | 1998-02-04 | Texas Instruments Incorporated | Improvements in or relating to semiconductor processing |
EP2568782A1 (en) * | 2011-09-12 | 2013-03-13 | Oberthur Technologies | Tool and method for embedding a module in a data carrier |
FR2998204A1 (en) * | 2012-11-19 | 2014-05-23 | Oberthur Technologies | TOOL FOR INSERTING A MODULE IN A HOUSING |
CN103474385A (en) * | 2013-09-09 | 2013-12-25 | 江阴迪林生物电子技术有限公司 | Chip bonding working table |
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