KR20020005935A - Multi chip package and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A multi-chip package and a method for fabricating the same are provided to prevent a mechanical contact between a processing apparatus and a conductive metal line used for a semiconductor chip and wire bonding. CONSTITUTION: The first semiconductor chip(11) and the second semiconductor chip(13) are adhered to upper faces and lower faces of two rectangular die pads(23a,23b) by using an adhesive(35). Each edge portion of the first semiconductor chip(11) and the second semiconductor chip(13) are supported by the die pads(23a,23b). The die pads(23a,23b) have projected areas(A,B), respectively. Each electrode pad(12,14) of the first semiconductor chip(11) and the second semiconductor chip(13) is connected with an upper face and a lower face of an inner end portion of an inner lead(21) by using conductive metal lines(31,32). A package body(40) is formed by an epoxy molding resin. The epoxy molding resin is filled between first semiconductor chip(11) and the second semiconductor chip(13).

Description

Multi chip package and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a multi-chip package comprising a plurality of semiconductor chips mounted on a lead frame and electrically connected to a single package, and a method of manufacturing the same.

With the recent development of the semiconductor industry and the demands of users, electronic devices are required to be smaller and lighter. One of the technologies mainly applied thereto is a multi chip packaging technology in which a plurality of semiconductor chips are mounted in a lead frame and configured into one package.

Multi-chip packaging technology has been widely applied to reduce the mounting area and light weight, especially in portable telephones requiring miniaturization and light weight. For example, when a flash memory device and a synchronous RAM (SRAM) device that performs a memory function are configured into one thin small outline package (TSOP), a unit semiconductor chip package containing each semiconductor device is included. It is more advantageous for miniaturization and weight reduction in size, weight, and mounting area than using two.

In general, a method of forming two semiconductor devices in one package includes a method of stacking two semiconductor devices and arranging them in parallel. The former has a disadvantage in that it is difficult to secure a stable process at a limited thickness due to the structure of stacking semiconductor elements. Difficult to obtain Usually, as a form applied to a package requiring miniaturization and light weight, a form of stacking semiconductor elements is frequently used. An example of such a multi-chip package is as follows.

1 is a cross-sectional view illustrating an example of a multi-chip package according to the prior art, and FIGS. 2A and 2B are cross-sectional views illustrating a wire bonding process in the multi-chip package manufacturing process of FIG. 1.

1 to 2B, in the multi-chip package 110, a first semiconductor chip 111 and a second semiconductor chip 113 are attached to an upper surface and a lower surface of the die pad 123, respectively. The upper surface of the inner end portion of the lead 121 of the electrode pad 112 of the semiconductor chip 111 and the electrode pad 114 of the second semiconductor chip 113 are spaced apart from the die pad 123 by a predetermined interval. The bottom surface is electrically bonded with conductive metal wires 131 and 132 to form an electrical connection, and the package body 140 is made of a plastic encapsulant such as an epoxy molding compound (EMC) for protection from external environments. The structure is formed. The outer lead 122 protruding to the outside of the package body 140 is molded in a shape suitable for mounting.

Such a multi-chip package 110 has the advantage that it can be developed in a low cost and a short period of time rather than increase the integration through the metallization technology that takes a lot of cost and development period, and can utilize 100% of the existing plastic package process. However, when the die attach or wire bonding process is performed, as shown in FIG. 2A, the semiconductor chips 111 and 113 are mounted on the block 210 in the lead frame 120 in which the semiconductor chips 111 and 113 are mounted. The block 210 supporting the 113 may directly contact the semiconductor chip 113, and foreign matter may enter between the semiconductor chip 113 and the block 210 supporting the semiconductor chip 113. Accordingly, damage to the semiconductor chip may occur, such as scratching, cracking, and contamination of the semiconductor chip 113. In addition, breaks, short circuits, and the like of the conductive metal wires 131 and 133 used for wire bonding may also occur during the progress of the wire bonding process. In order to prevent direct contact between the semiconductor chip 113 and the block 210, as shown in FIG. 2B, a buffer layer 220 is formed of a soft material between the semiconductor chip 113 and the block 210. However, the impact on the semiconductor chip 113 is not 100% prevented.

In addition, since the structure of the upper and lower electrode pads 112 and 114 has to be manufactured in a mirror image with each other, the conventional multi-chip package 110 introduced above is restricted to use two types of semiconductor chips 111 and 113. This follows.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-chip package and a method of manufacturing the same, in which mechanical contact between the conductive metal wire and the process equipment used for the semiconductor chip and the wire bonding does not occur.

1 is a cross-sectional view showing an example of a multi-chip package according to the prior art,

2A and 2B are cross-sectional views illustrating a wire bonding process in the multi-chip package manufacturing process of FIG. 1;

3 is a cross-sectional view showing an embodiment of a multichip package according to the present invention;

4A-4F are schematic manufacturing process diagrams of a multichip package according to the present invention.

Explanation of symbols on the main parts of the drawings

10; Multi-chip package 11,13; Semiconductor chip

12,14; Bonding pads 21; Internal lead

22; Outer leads 23a, 23b; Die pad

31,32; Bonding wire 35; glue

40; Package body 230,240; Die bonding block

250; Wire bonding block

The multi-chip package according to the present invention for achieving the above object, a plurality of die pads are formed spaced apart from each other and extending to the outside, a first semiconductor chip and a second semiconductor chip formed with a plurality of electrode pads and An inner lead spaced apart from the die pad by a predetermined distance, a conductive metal wire electrically connecting the electrode pads of the semiconductor chips and a lead thereof, and formed to encapsulate the semiconductor chips, the conductive metal wire, and the inner lead; The package body is formed of resin, and the upper and lower surfaces of each die pad are attached to the edge portions of the first semiconductor chip and the second semiconductor chip, and the die pad is disposed outwardly of the first semiconductor chip and the second semiconductor chip. An extended area is characterized in that it protrudes.

In addition, the multi-chip package manufacturing method according to the present invention for achieving the above object, a lead frame having a plurality of internal leads and two die pads each formed with an extended area formed and spaced apart from each other by a predetermined distance are prepared And attaching a first semiconductor chip having a plurality of electrode pads to a lower edge of a lower surface of the first semiconductor chip to protrude to the side of the first semiconductor chip. A second semiconductor chip having a plurality of electrode pads formed thereon while supporting the first semiconductor chip mounting step and (i) inverting a lead frame in which the first semiconductor chip is mounted, supporting an area in which the die pad extends from the outside of the first semiconductor chip; Of the second semiconductor chip such that the extended region of the die pad protrudes to the side of the second semiconductor chip. A second semiconductor chip mounting step of attaching a surface edge portion to the die pad, and (f) the electrode pad of the first semiconductor chip, the inner lead and the second semiconductor chip in a state of supporting the extended region of the die pad. A wire bonding step of wire-bonding the electrode pad and the inner lead with a conductive metal wire, and a molding step of forming a package body encapsulating the first semiconductor chip, the second semiconductor chip, the inner lead, and the conductive metal wire with a molding resin. It is characterized by including.

Hereinafter, a multi-chip package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view showing an embodiment of a multi-chip package according to the present invention.

Referring to FIG. 3, the multi-chip package 10 of the present invention has a first semiconductor chip 11 and a second semiconductor chip 13 on the top and bottom surfaces of two rectangular die pads 23a and 23b spaced apart from each other. ) Is attached with an adhesive 35. Two die pads 23a and 23b support edge portions of the first semiconductor chip 11 and the second semiconductor chip 13. Each of the die pads 23a and 23b has regions A and B that are formed to extend laterally by a predetermined length.

In the first semiconductor chip 11 and the second semiconductor chip 13 mounted on the die pads 23a and 23b, the electrode pads 12 and 14 are spaced apart from the die pads 23a and 23b at predetermined intervals. The upper and lower surfaces of the inner end portion of the lead 121 are wire-bonded with conductive metal wires 31 and 32 to form an electrical connection, and the package body 140 is formed of an epoxy molding resin for protection from the external environment. It is. Here, the epoxy molding resin also fills the space between the first semiconductor chip 11 and the second semiconductor chip 13.

The outer lead 22 protruding to the outside of the package body 40 is formed into a shape suitable for mounting through cutting and bending.

Such a multi-chip package structure is formed such that a plurality of die pads formed in two parts are separated from each other so as to support edges of the semiconductor chips so that no contact with the block on which the lead frame is placed occurs during the semiconductor assembly process. Protrudes to the side of the field by a certain length. In addition, a space is formed between the semiconductor chips, whereby the molding resin enters, thereby improving structural stability, thereby improving reliability. The manufacturing process of such a multi-chip package will be described.

4A-4F are schematic manufacturing process diagrams of a multichip package according to the present invention.

Referring to FIG. 4A, first, a lead frame 20 having a plurality of internal leads 21 and two die pads 23a and 23b formed to be spaced apart from each other by a predetermined distance is mounted on the die bonding block 230. Here, the die pads 23a and 23b are formed to be spaced apart from each other to support the edges of the mounted semiconductor chips, and have regions A and B extending outwardly. And the adhesive agent 35 is apply | coated to each of the die pads 23a and 23b of the lead frame 20 mounted.

Referring to FIG. 4B, a first semiconductor chip 11 having a plurality of electrode pads 12 is mounted next. Edges of the lower surface of the first semiconductor chip 11 are bonded to each other, and the die pads 23a and 23b are protruded by predetermined lengths of the regions A and B extending laterally of the first semiconductor chip 11.

Referring to FIG. 4C, a die bonding block supporting the edge portions of the die pads 23a and 23b from the outside of the first semiconductor chip 11 by inverting the lead frame 20 on which the first semiconductor chip 11 has been mounted. Mount on (240). And the adhesive agent 35 is apply | coated to the die pads 23a and 23b of the lead frame 20 mounted upside down.

Referring to FIG. 4D, a second semiconductor chip 13 having a plurality of electrode pads 14 formed on the die pads 23a and 23b of the lead frame 20 where the application of the adhesive 35 is completed is mounted. The lower edge portion of the second semiconductor chip 13 is bonded to the die pads 23a and 23b, and the extended areas A and B of the die pads 23a and 23b protrude outward of the second semiconductor chip 13. .

Referring to FIG. 4E, when the mounting of the semiconductor chips 11 and 13 is completed, the regions A and B in which the lead frames 20 are extended to the die pads 23a and 23b are formed outside the second semiconductor chip 13. The electrode pad 12 and the inner lead 21 of the first semiconductor chip 11 may be electrically conductive with the lead frame 20 mounted on the wire bonding block 250a so as to be placed on the die pad support part 250a. ) Wire bond. As a result, the electrode pad 12 of the first semiconductor chip 11 and the internal lead 21 corresponding thereto are electrically connected to each other. At this time, the regions A and B extending from the die pads 23a and 23b are supported outside the first semiconductor chip 13 so that the wire bonding block 250 does not come into contact with the first semiconductor chip 13.

Referring to FIG. 4F, when the wire bonding of the first semiconductor chip 11 and the inner lead 21 is completed, the lead pad 20 is turned upside down and the die pad 23a protrudes out of the first semiconductor chip 11. The electrode pad 14 and the inner lead 21 of the second semiconductor chip 13 are wired to the conductive metal wire 32 while the lead frame 20 is mounted on the wire bonding blocks 255 and 256 so that the 23b is supported. Bond As a result, the inner lead 21 corresponding to the electrode pad 14 of the second semiconductor chip 13 is electrically connected thereto. In this case, the wire bonding block 255 supports the die pads 23a and 23b so that the wire bonding block 255 does not come into contact with the first semiconductor chip 13.

Referring to FIG. 3, when the wire bonding of the second semiconductor chip 13 and the inner lead 21 is completed, the first semiconductor chip 11, the second semiconductor chip 13, the inner lead 21, and the conductivity The package body 40 is formed by molding with a molding resin such as an epoxy molding resin to seal the metal wires 31 and 32. During the molding process, the molding resin is divided into three flows between the upper portion of the first semiconductor chip 11 and the lower portion of the second semiconductor chip 13 and the gap between the first semiconductor chip 11 and the second semiconductor chip 13. Divided and supplied. At this time, the outer lead 22 protrudes out of the package body 40 and is bent and cut into a form suitable for mounting by a subsequent process.

In this method of manufacturing a multi-chip package according to the present invention, since the die bonding block or the wire bonding block supports the die pad, not the semiconductor chip, the semiconductor chip and the conductive metal wire used for the wire bonding do not occur and the semiconductor No foreign material is inserted between the chip and the block.

According to the multi-chip package and the manufacturing method according to the present invention as described above, mechanical contact between the semiconductor chip and the die bonding block or wire bonding block does not occur during the assembly process and foreign matter is not inserted into the semiconductor chip surface. 100% damage can be prevented. In addition, the molding resin may be filled between the semiconductor chips to have structural stability.

Claims (4)

A plurality of die pads formed to be spaced apart from each other and extending outwardly, a first semiconductor chip and a second semiconductor chip having a plurality of electrode pads formed thereon, and spaced apart from the die pad by a predetermined distance; An inner lead, a conductive metal wire electrically connecting the electrode pads of the semiconductor chips to the lead corresponding thereto, and a package body formed of a molding resin to seal the semiconductor chips, the conductive metal wire, and the inner lead, An edge portion of the first semiconductor chip and the second semiconductor chip is attached to the upper and lower surfaces of each of the die pads, and an area in which the die pad extends outside the first semiconductor chip and the second semiconductor chip is formed. Multi-chip package, characterized in that protruding. The multichip package of claim 1, wherein the die pads are two die pads each having a rectangular shape. The multi-chip package according to claim 1, wherein a molding resin is filled between the first semiconductor chip and the second semiconductor chip. Preparing a lead frame having two die pads formed with a plurality of inner leads and regions extending from each other and spaced apart from each other by a predetermined distance; A first semiconductor chip for attaching a first semiconductor chip having a plurality of electrode pads to an edge portion of a lower surface of the first semiconductor chip such that an extended region of the die pad protrudes to the side of the first semiconductor chip; Mounting step; A region in which the second semiconductor chip having a plurality of electrode pads formed thereon is extended by supporting the region where the first semiconductor chip has been mounted and supporting the region where the die pad extends from the outside of the first semiconductor chip A second semiconductor chip mounting step of attaching an edge portion of a lower surface of the second semiconductor chip to the die pad so as to protrude to the side of the second semiconductor chip; A wire bonding step of wire bonding the electrode pad and the inner lead of the first semiconductor chip and the electrode pad and the inner lead of the second semiconductor chip with a conductive metal wire, respectively, while supporting the extended region of the die pad; A molding step of forming a package body encapsulating the first semiconductor chip, the second semiconductor chip, the inner lead, and the conductive metal wire with a molding resin; Multi-chip package manufacturing method comprising a.