KR100422608B1 - Stack chip package - Google Patents

Stack chip package Download PDF

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Publication number
KR100422608B1
KR100422608B1 KR1019970018062A KR19970018062A KR100422608B1 KR 100422608 B1 KR100422608 B1 KR 100422608B1 KR 1019970018062 A KR1019970018062 A KR 1019970018062A KR 19970018062 A KR19970018062 A KR 19970018062A KR 100422608 B1 KR100422608 B1 KR 100422608B1
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South Korea
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semiconductor chip
lead
chip package
package
bonding
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KR1019970018062A
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Korean (ko)
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KR19980082949A (en
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조민교
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삼성전자주식회사
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Priority to KR1019970018062A priority Critical patent/KR100422608B1/en
Publication of KR19980082949A publication Critical patent/KR19980082949A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A stack chip package is provided to decrease the size of a package by reducing the vertical height of the package as compared with that of a conventional stack chip package, and to shorten an interval of fabricating time by eliminating the necessity of a process such as a lead bending process. CONSTITUTION: A semiconductor chip(10) has a plurality of bonding pads(11). The inner end of a lead(21) of a leadframe is of a convex type. A predetermined space between inner leads is formed in the leadframe. Insulating adhesion tape is attached to a lower surface of a lead end part having a decreased thickness and to the lower surface of the semiconductor chip so as to fix the semiconductor chip. The bonding pad is electrically connected to the leadframe by a bonding wire(32). A plurality of vertically stacked unit semiconductor chip packages(50) have resin encapsulant(34) that exposes the side surface of the leadframe and protects the lead from the outer environments. A junction unit is attached to each lead of the unit semiconductor chip package to perform a vertical electrical connection.

Description

적층 칩 패키지{Stack chip package}Stacked chip package

본 발명은 적층 칩 패키지에 관한 것으로, 더욱 상세하게는 리드의 내측 말단 부분이 철(凸)자 형상을 갖는 단위 반도체 칩 패키지를 이용함으로써, 적층 칩 패키지의 크기를 감소시킬 수 있는 적층 칩 패키지에 관한 것이다.The present invention relates to a stacked chip package, and more particularly, to a stacked chip package capable of reducing the size of the stacked chip package by using a unit semiconductor chip package having an inner end portion of a lead having an iron shape. It is about.

반도체 소자의 발달과 함께 반도체 소자의 패키징(packaging) 기술은 소형화 및 박형화로 진행되고 있으며, 기능적인 측면에서는 다기능화되고 있다. 특히 메모리 반도체 칩의 경우에 용량이 점점 증가함에 따라 반도체 칩의 크기가 점점 증가하고 있는 추세에 따라서 여러 형태의 반도체 칩 패키지가 개발 적용되고 있다. 특히 단위 반도체 칩 패키지 적층 기술을 이용하여 고밀도화시킨 적층 칩 패키지의 개발도 진행되고 있다. 이러한 적층 칩 패키지의 일 실시예를 소개하면 다음과 같다.BACKGROUND With the development of semiconductor devices, the packaging technology of semiconductor devices has been progressed to miniaturization and thinning, and in terms of functional aspects, they have become multifunctional. In particular, in the case of a memory semiconductor chip, various types of semiconductor chip packages have been developed and applied in accordance with a trend in which the size of the semiconductor chip is gradually increasing as the capacity is increased. In particular, development of a multilayer chip package having a high density by using a unit semiconductor chip package stacking technology is also in progress. An embodiment of such a stacked chip package is described as follows.

도 1은 종래 기술에 의한 적층 칩 패키지를 나타낸 단면도이다.1 is a cross-sectional view showing a laminated chip package according to the prior art.

도 1을 참조하면, 종래 기술에 의한 적층 칩 패키지(200)는 단위 반도체 칩 패키지(100) 복수 개, 예컨대 4개가 적층되어 있는 구조를 갖고 있다. 적층 칩 패키지(200)의 각 단위 반도체 칩 패키지(100)는 반도체 칩(110)의 하면과 다이패드(120)의 상면이 접착제(도시 안됨)에 의해 접착되어 있고, 그 반도체 칩(110)상에 형성된 본딩패드(도시 안됨)와 그에 대응되는 내부리드(130)가 금선(145)에 의해 전기적으로 연결되어 있으며, 내부리드(130)와 일체형으로 형성된 외부리드(140)가 "J"자 형상을 갖고 있고, 반도체 칩(110)과 다이패드(120)와 내부리드(130)들이 성형 수지(180)에 의해 봉지되어 있는 구조이다. 단위 반도체 칩 패키지(100)들은 외부리드(140)들이 전도성 접착제(190)에 의해 접합되어 전기적으로 연결되어 있다.Referring to FIG. 1, the stacked chip package 200 according to the related art has a structure in which a plurality of unit semiconductor chip packages 100, for example, four are stacked. The lower surface of the semiconductor chip 110 and the upper surface of the die pad 120 are bonded to each unit semiconductor chip package 100 of the stacked chip package 200 by an adhesive (not shown), and on the semiconductor chip 110. Bonding pads (not shown) formed therein and the inner leads 130 corresponding thereto are electrically connected by gold wires 145, and the outer leads 140 formed integrally with the inner leads 130 have a “J” shape. The semiconductor chip 110, the die pad 120, and the inner lead 130 are sealed by the molding resin 180. In the unit semiconductor chip package 100, the outer leads 140 are bonded to each other by the conductive adhesive 190 and electrically connected thereto.

그런데, 반도체 칩의 크기가 커지면 패키지의 크기를 증가시키기 않고서는 패키지의 신뢰성을 확보하기가 매우 어렵다. 따라서, 단위 반도체 칩 패키지의 크기가 증가되고 그에 따라 적층 칩 패키지의 크기도 증가하며 적층 면적도 증가하게 된다. 즉, 패키지 및 기판의 경박단소화에 역행하게 되는 것이다.However, as the size of the semiconductor chip increases, it is very difficult to secure the reliability of the package without increasing the size of the package. Therefore, the size of the unit semiconductor chip package is increased, thereby increasing the size of the stacked chip package and the stacking area. In other words, the thickness of the package and the substrate is reversed.

따라서 본 발명의 목적은 반도체 칩 패키지의 크기를 증가시키지 않으면서도 기존의 적층 칩 패키지가 가지고 있는 여러 장점들을 제공해 주는 적층 칩 패키지를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a multilayer chip package that provides various advantages of a conventional multilayer chip package without increasing the size of the semiconductor chip package.

도 1은 종래 기술에 따른 적층 칩 패키지의 일 실시예를 나타낸 단면도.1 is a cross-sectional view showing an embodiment of a stacked chip package according to the prior art.

도 2내지 도 5는 본 발명에 따른 적층 칩 패키지에 사용되는 단위 반도체 칩 패키지의 제조 공정도.2 to 5 are manufacturing process diagrams of the unit semiconductor chip package used in the stacked chip package according to the present invention.

도 6은 본 발명에 따른 적층 칩 패키지의 일 실시예를 나타낸 단면도.6 is a cross-sectional view showing an embodiment of a stacked chip package according to the present invention.

도 7은 본 발명에 따른 적층 칩 패키지의 다른 실시예를 나타낸 단면도.7 is a cross-sectional view showing another embodiment of a stacked chip package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10,110 : 반도체 칩 11 : 본딩 패드10,110 semiconductor chip 11: bonding pad

20 : 리드 프레임 21 : 리드20: lead frame 21: lead

30 : 절연성 접착 필름 32,145 : 본딩 와이어30: insulating adhesive film 32145: bonding wire

34 : 수지 봉지재 36,190 : 솔더34: resin encapsulant 36,190: solder

40 ; 절단 장치 50,100 : 단위 반도체 칩 패키지40; Cutting device 50100: unit semiconductor chip package

60 : 절연층 70,200 : 적층 칩 패키지60: insulation layer 70, 200: laminated chip package

130 : 내부 리드 140 : 외부 리드130: internal lead 140: external lead

상기 목적을 달성하기 위한 본 발명에 따른 적층 칩 패키지는 복수 개의 본딩 패드를 갖는 반도체 칩, 리드의 내측 말단부가 철(凸)자 형상을 갖고 있으며 마주보는 내측 리드간 소정의 공간을 갖는 리드 프레임, 반도체 칩을 고정시켜주기 위하여 리드 말단부의 두께가 얇아진 부분의 하면과 반도체 칩의 하면에 부착되는 절연성 접착 테이프, 본딩 패드와 상기 리드 프레임을 전기적으로 연결하는 본딩 와이어, 및 리드 프레임의 측면이 노출되도록 하며 외부로부터의 환경을 보호하기 위한 수지 봉지재를 갖는 수직으로 적층된 복수의 단위 반도체 칩 패키지; 단위 반도체 칩 패키지의 각각의 리드에 부착되어 수직으로 전기적인 연결을 이루도록 하는 접합 수단;을 포함하는 것을 특징으로 한다.The stacked chip package according to the present invention for achieving the above object is a semiconductor chip having a plurality of bonding pads, a lead frame having an inner end portion of the lead has an iron shape and has a predetermined space between the opposite inner lead, In order to fix the semiconductor chip, the lower surface of the thinned portion of the lead end portion and the insulating adhesive tape attached to the lower surface of the semiconductor chip, the bonding wire electrically connecting the bonding pad and the lead frame, and the side of the lead frame are exposed. A plurality of vertically stacked unit semiconductor chip packages having a resin encapsulant for protecting the environment from the outside; And bonding means attached to each lead of the unit semiconductor chip package to form a vertical electrical connection.

이하 첨부 도면을 참조하여 본 발명에 따른 적층 칩 패키지를 보다 상세하게설명하고자 한다.Hereinafter, a multilayer chip package according to the present invention will be described in detail with reference to the accompanying drawings.

도 2내지 도 5는 본 발명에 따른 적층 칩 패키지에 사용되는 단위 반도체 칩 패키지의 제조 공정도이다.2 to 5 are manufacturing process diagrams of the unit semiconductor chip package used in the stacked chip package according to the present invention.

본 발명에 따른 적층 칩 패키지를 구현하기 위한 단위 반도체 칩 패키지는 다음과 같이 제조된다. 도 2내조 도 5를 참조하기로 한다. 먼저, 복수의 본딩 패드(11)를 갖는 반도체 칩(10)과 리드(21)의 내측 말단이 철(凸)자 형상을 갖는 리드 프레임(20)을 준비한다. 철(凸)자 형상의 리드(21)를 갖는 리드 프레임(20)은 일반적인 리드 프레임에 대한 하프-에칭(half-etching)법 또는 기계적인 펀칭법 등을 진행하여 만들어질 수 있다.The unit semiconductor chip package for implementing the stacked chip package according to the present invention is manufactured as follows. Reference will be made to FIG. 2 and FIG. 5. First, a semiconductor chip 10 having a plurality of bonding pads 11 and a lead frame 20 having an inner end of the lead 21 in an iron shape are prepared. The lead frame 20 having the iron-shaped lead 21 may be made by performing a half-etching method or a mechanical punching method with respect to a general lead frame.

그리고, 일반적인 리드 온 칩(lead on chip) 기술에서 사용되는 절연성의 접착 필름(30)을 반도체 칩(10)의 하면과 리드(21)의 내측 말단의 하면에 부착시킴으로써 반도체 칩(10)을 리드(21)에 고정시킨다. 이때, 절연성 접착 필름(30)과 부착되는 리드(21)부분은 철(凸)자 형상에서 두께가 감소된 부분이다. 반도체 칩(10)이 리드(21)에 고정되면, 금선과 같은 전도성의 금속선인 본딩 와이어(32)를 본딩 패드(11)와 리드(21)에 각각 접합시켜 전기적으로 상호 연결시킨다.Then, the semiconductor chip 10 is lead by attaching the insulating adhesive film 30 used in general lead on chip technology to the lower surface of the semiconductor chip 10 and the lower surface of the inner end of the lead 21. Fix to (21). At this time, the portion of the lead 21 attached to the insulating adhesive film 30 is a portion in which the thickness is reduced in the shape of iron. When the semiconductor chip 10 is fixed to the lead 21, bonding wires 32, which are conductive metal wires such as gold wires, are bonded to the bonding pads 11 and the leads 21, respectively, to be electrically connected to each other.

그리고, 와이어 본딩된 부분과 반도체 칩(10)을 감싸도록 하여 에폭시 성형수지와 같은 수지 봉지재(34)로 봉지한다. 다음에, 절단 장치(40)를 이용하여 리드(21)를 절단한다. 이 절단되고 남은 리드(21) 부분이 외부 접속 단자의 역할을 하게 된다. 절단까지 완료되면, 단위 반도체 칩 패키지(50)의 제조가 완료된다.Then, the wire bonded portion and the semiconductor chip 10 are wrapped to be encapsulated with a resin encapsulant 34 such as an epoxy molding resin. Next, the lid 21 is cut using the cutting device 40. The part of the lead 21 remaining after the cutting serves as an external connection terminal. When the cutting is completed, the manufacturing of the unit semiconductor chip package 50 is completed.

도 6은 본 발명에 따른 적층 칩 패키지의 일 실시예를 나타낸 단면도이고,도 7은 본 발명에 따른 적층 칩 패키지의 다른 실시예를 나타낸 단면도이다.6 is a cross-sectional view showing an embodiment of a stacked chip package according to the present invention, and FIG. 7 is a cross-sectional view showing another embodiment of a stacked chip package according to the present invention.

도 6과 도 7을 참조하면, 상기한 작업에 의해 제조되는 단위 반도체 칩 패키지(50)를 이용하여 적층 칩 패키지(70)를 제조하기 위해, 동일한 기능의 단위 반도체 칩 패키지(50)를 수직으로 적층하는 작업을 진행하게 된다. 준비된 단위 반도체 칩 패키지(50)의 리드(21) 하면에 리플로우 솔더링(reflow soldering)을 위해 접합수단인 솔더(solder;36)를 도포하고, 이 단위 반도체 칩 패키지(50)들을 리드(21)와 리드(21)가 전기적으로 연결되도록 하여 수직으로 적층한다. 이러한 상태를 유지하기 위하여 소정의 치공구를 이용하여 적층된 상태를 고정시킨 후에 리플로우 퍼니스(reflow furnace)를 통과시켜 리플로우하므로써, 외부 단자인 리드(21)를 상하로 전기적으로 상호 연결되는 상태를 만들어 주면 적층 칩 패키지(70)가 된다. 리드와 리드의 접합부분에는 저융점 금속(Sn, Solder Alloy 등)을 미리 도금하여 상하 단위 반도체 칩 패키지의 접합부가 저온에서 직접 리플로우 솔더링 될 수 있도록 하거나, 솔더 볼을 이용할 수 있다.6 and 7, in order to manufacture the stacked chip package 70 using the unit semiconductor chip package 50 manufactured by the above operation, the unit semiconductor chip package 50 having the same function is vertically formed. The lamination work is performed. A solder 36, which is a bonding means, is applied to the lower surface of the lead 21 of the prepared unit semiconductor chip package 50, and the unit semiconductor chip packages 50 are connected to the lead 21. And leads 21 are electrically connected so as to be stacked vertically. In order to maintain such a state, the state in which the lead 21, which is an external terminal, is electrically connected up and down by reflowing through a reflow furnace after fixing the stacked state using a predetermined tool. If made, it becomes a laminated chip package 70. The lead-to-lead joint may be plated with a low melting point metal (Sn, solder alloy, etc.) in advance so that the joint of the upper and lower unit semiconductor chip packages may be directly reflow soldered at a low temperature, or solder balls may be used.

이상과 같은 적층 칩 패키지는 각각의 단위 반도체 칩 패키지의 리드 상하면에 외부 단자 역할을 하는 수단들을 선택적 또는 모두 형성시켜 줄 수 있기 때문에 적층하기에 용이하고, 적층 칩 패키지를 구성한 다음에라도 리드 상하면을 이용하여 테스트가 가능하게 된다. 만약, 최상층의 단위 반도체 칩 패키지의 경우 리드가 노출되어 전기적인 단락의 가능성이 있을 경우에는 도 7에서와 같이 적층 칩 패키지(70)의 리드를 보호하도록 리드(21) 외벽에 절연층(60)이 형성된 구조를 갖도록 하는 것도 가능하다.The multilayer chip package as described above is easy to stack because it can selectively or all the means serving as an external terminal on the upper and lower leads of each unit semiconductor chip package. Test is possible. In the case of the uppermost unit semiconductor chip package, if the lead is exposed and there is a possibility of an electrical short, as shown in FIG. 7, the insulating layer 60 is formed on the outer wall of the lead 21 to protect the lead of the multilayer chip package 70. It is also possible to have this formed structure.

이상과 같은 적층 칩 패키지는 종래에 적층 칩 패키지를 제조하기 위하여 단위 반도체 칩 패키지의 리드들을 수직으로 전기적으로 연결할 때, 리드가 "J"자 형상 등으로 굴곡되어 상하 접합되었기 때문에 수직 높이가 상승되었으나, 리드가 굴곡된 부분이 없고, 또한 리드 내측 말단부가 철(凸)자 형상을 갖고 있음으로 해서 리드 하면보다 내측에서 반도체 칩의 실장이 일어나기 때문에 수직 높이가 크게 감소될 수 있다. 또한, 리드들이 외부로 노출되어 있기 때문에 열 방출 또는 방열 효과가 우수하다. 전체적인 리드의 길이도 축소되어 전기적 경로가 짧아지기 때문에 전기적 특성이 향상되어 고속 소자에 실장할 수도 있게 된다.In the multilayer chip package as described above, when the leads of the unit semiconductor chip package are electrically connected vertically in order to manufacture the multilayer chip package, the vertical height is increased because the leads are bent in a “J” shape or the like and vertically joined. Since the lead is not bent and the inner end portion of the lead has an iron shape, the vertical height can be greatly reduced because mounting of the semiconductor chip occurs inside the lower surface of the lead. In addition, since the leads are exposed to the outside, the heat dissipation or heat dissipation effect is excellent. The overall lead length is also shortened to shorten the electrical path, which improves the electrical characteristics and can be mounted on high-speed devices.

따라서 본 발명에 의한 적층 칩 패키지 구조에 따르면, 종래 적층 칩 패키지보다 수직 높이를 감소시켜 패키지 크기 감소를 가능하게 하고, 리드의 굴곡 공정 등과 같은 공정이 생략될 수 있어 그 제조 공정을 진행하는 것이 용이해져 생산에 소요되는 시간을 절약할 수 있을 뿐만 아니라 비용 절감의 효과를 볼 수 있어, 생산성을 향상시킬 수 있는 이점(利點)이 있다.Therefore, according to the stacked chip package structure according to the present invention, it is possible to reduce the package size by reducing the vertical height than the conventional stacked chip package, it is possible to skip the process such as the bending process of the lead, it is easy to proceed with the manufacturing process As well as saving the time required for production, the cost reduction effect can be seen, which has the advantage of improving productivity.

Claims (2)

복수 개의 본딩 패드를 갖는 반도체 칩, 리드의 내측 말단부가 철(凸)자 형상을 갖고 있으며 마주보는 내측 리드간 소정의 공간을 갖는 리드 프레임, 상기 반도체 칩을 고정시켜주기 위하여 상기 리드 말단부의 두께가 얇아진 부분을 하면과 상기 반도체 칩의 하면에 부착되는 절연성 접착 테이프, 상기 본딩 패드와 상기 리드 프레임을 전기적으로 연결하는 본딩 와이어, 및 상기 리드 프레임의 측면이 노출되도록 하며 외부로부터의 환경을 보호하기 위한 수지 봉지재를 갖는 수직으로 적층된 복수의 단위 반도체 칩 패키지; 상기 단위 반도체 칩 패키지의 각각의 리드에 부착되어 수직으로 전기적인 연결을 이루도록 하는 접합 수단;을 포함하는 것을 특징으로 하는 적층 칩 패키지.A semiconductor chip having a plurality of bonding pads, an inner end portion of the lead having an iron shape, a lead frame having a predetermined space between opposite inner leads, and a thickness of the lead end portion for fixing the semiconductor chip. An insulating adhesive tape attached to a lower surface of the thinner portion and a lower surface of the semiconductor chip, a bonding wire electrically connecting the bonding pad and the lead frame, and side surfaces of the lead frame are exposed to protect the environment from the outside. A plurality of unit semiconductor chip packages stacked vertically with a resin encapsulant; And bonding means attached to each lead of the unit semiconductor chip package to form a vertical electrical connection. 제 1항에 있어서, 상기 접합 수단이 솔더인 것을 특징으로 하는 적층 칩 패키지.2. The laminated chip package of claim 1, wherein the bonding means is solder.
KR1019970018062A 1997-05-10 1997-05-10 Stack chip package KR100422608B1 (en)

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