KR19980034119A - Semiconductor Chip Stack Package - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip stack type package, wherein a connection caused by a defect of a lead resin caused by bleeding of an encapsulation resin or a deflection of an encapsulation resin, which is a problem in a method of stacking a plurality of semiconductor packages in the related art, or a deflection of the encapsulation resin, This is to solve the stacking failure problem.

In other words, the conventional lead frame used in the lead-on-chip (LOC) package is modified and applied, and the two lead frames, each of which the semiconductor chip is bonded and electrically connected to each other, are formed in a step to face each other, and are then bonded and electrically connected. By encapsulating, a stacked package is implemented in one package. At this time, one lead frame is cut at the dam bar, and the entire lead frame is encapsulated, and the other lead frame has an external lead projecting out of the encapsulation region to form a package of a conventional TSOP or TSOJ type.

Since the stacked package is a structure in which two semiconductor chips are stacked in one package by using a conventional plastic package manufacturing facility and a conventional lead frame, the stacking failure caused by the bleeding or warping of the encapsulating resin can be prevented. And, there is an advantage that can be mass-produced without burden of additional investment cost.

Description

Semiconductor Chip Stack Package

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip stacked package, and more particularly, to a plurality of semiconductor chips using a conventional lead frame in order to prevent stacking defects caused by bleeding or warpage of encapsulating resin in a conventional stacked package. The present invention relates to a semiconductor chip stacked package stacked in a package.

In the assembly technology of semiconductor packages, lamination technology has been advanced in an effort to reduce the size of electronic devices, increase the mounting density of electronic devices, and improve performance. For example, by stacking two separate memory chips, the memory capacity can be doubled. Such a stacking technology includes a method of stacking and packaging a plurality of bare chips, a method of packaging a semiconductor chip and then stacking a plurality of packages, a multi-chip module (MCM); Multi Chip Module), and then it can be divided into a stacking method.

Among them, a method of stacking packages is stacking a plurality of thin small outline packages (TSOPs) or thin small outline J-bend packages (TSOJs), and each package is individually assembled and the upper layer package is completed after electrical testing is completed. The lamination is implemented by connecting the external leads of the lower layer package and the external leads of the lower layer package to each other.

Hereinafter, two embodiments of a conventional stacked package will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing a first embodiment of a stacked package according to the prior art.

2 is a cross-sectional view showing a second embodiment of a stacked package according to the prior art.

Referring first to FIG. 1, a conventional stacked package 100 in which two TSOJs 100a and 100b are stacked, and the semiconductor chip 10 and the lead frames 11 and 12 are mechanically bonded by an adhesive tape 14. And a conventional lead on chip (LOC) structure bonded to each other and electrically connected by the fine metal wires 13.

In addition, the external leads of the lead frames 11 and 12 are bent in a J shape, and the connection between the external leads is soldered by thermally compressing the flux after applying flux to the external lead portions in which tin / lead (Sn / Pb) is plated. (Soldering) is done. That is, the outer lead of the upper layer package 100a is connected to the outer lead shoulder portion of the lower layer package 100b. Therefore, the body shape of the lower layer package 100b made of the encapsulation resin 16 is different from that of the upper layer package 100a. That is, the body form of the lower layer package 100b is a form in which a portion of the upper body is removed in order to connect the external leads of the upper layer package 100a.

In the stacked package 200 illustrated in FIG. 2, the lower layer package is a TSOP, and the basic structure is the same as the stacked package described above.

However, a common problem of the conventional stacked package is that flashing of the encapsulating resins 16 and 26 occurs on the shoulder portions of the outer leads 12 and 22 of the lower layer packages 100b and 200b. As described above, in order to establish a connection between the external leads 11, 12, 21, and 22, the plating of the leads 12 and 22 must be performed first, followed by soldering. Since the encapsulation resins 16 and 26 are smeared, the plating is performed. This is not done and therefore no soldering is possible.

In addition, when warpage of the encapsulation resins 16 and 26 occurs, a poor connection between the leads 11, 12, 21, and 22 may occur due to poor flatness of the leads 12 and 22. In addition, since a separate facility for lamination is required, further development of the facility is required.

Accordingly, an object of the present invention is to prevent the stacking failure caused by the bleeding or warpage of the encapsulation resin in the case of the conventional laminated package, and by using the manufacturing equipment of the conventional plastic package as it is, no additional equipment investment is required. To provide.

1 is a cross-sectional view showing a first embodiment of a stacked package according to the prior art.

2 is a cross-sectional view showing a second embodiment of the stacked package according to the prior art.

3 is a partial cross-sectional view showing an embodiment of a stacked package according to the present invention.

4 is a partial plan view showing a lower lead frame of the stacked package shown in FIG.

5 and 6 are partial plan views showing an upper lead frame of the stacked package shown in FIG.

* Description of the symbols for the main parts of the drawings *

300: Semiconductor Chip Stacked Package

30a, 30b: semiconductor chip

31a, 31b, 32, 33: adhesive means

34a, 34b, 34c: Metal Wire

35 Encapsulation Resin

36a, 36b, 36c: Plating Area

40: Lower Lead Frame

50: Upper Lead Frame

41, 51: inner lead

42, 52: outer lead

43, 53: tie bar

44, 54: Dam Bar

45, 55: side rail

In order to achieve the above object, the present invention is a plurality of chip electrode pads are each formed, the first semiconductor chip and the second semiconductor chip and the first semiconductor chip and the opposite surface of the surface on which the chip electrode pad is formed are bonded to each other; A first lead frame that is mechanically and electrically connected, a second lead frame that is mechanically and electrically connected to the second semiconductor chip and is mechanically and electrically connected to the first lead frame, and the first semiconductor chip and the first Provided are a semiconductor chip stacked package including a sealing resin for encapsulating a second semiconductor chip, a part of a first lead frame, and an entirety of a second lead frame.

The part of the 1st lead frame which is not sealed with sealing resin is an external connection terminal, and the form is the same as the external lead of TSOP or TSOJ.

The first semiconductor chip and the first lead frame, and the second semiconductor chip and the second lead frame are each mechanically connected by an adhesive tape and electrically connected by thin metal wires.

In addition, the first lead frame and the second lead frame face each other to form a step, mechanically connected by an adhesive tape, it is electrically connected by a fine metal wire.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a partial cross-sectional view showing an embodiment of a stacked package according to the present invention.

4 is a partial plan view illustrating a lower lead frame of the stacked package illustrated in FIG. 3.

5 and 6 are partial plan views illustrating an upper lead frame of the stacked package shown in FIG. 3.

First, referring to FIG. 3, the stacked package 300 according to the present exemplary embodiment is a kind of a structure in which a plurality of unpacked bare chips are stacked and packaged, and the first semiconductor chip 30b and the second semiconductor chip 30a are chips. Opposite sides of the surface on which the electrode pads (not shown; Chip Electrode Pads) are formed are bonded to each other (33) and stacked and packaged. At this time, the adhesive means 33 between the two semiconductor chips uses an insulating adhesive means that is commonly used.

The two semiconductor chips 30a and 30b each form a mechanical and electrical connection in a form of a lead on chip (LOC) on a separate lead frame. That is, the first semiconductor chip 30b on the lower side and the lower lead frame (40 in FIG. 4; lower lead frame) and the second semiconductor chip 30a on the upper side and the upper lead frame (50 in FIG. 6) ) Are mechanically connected by adhesive tapes 31b and 31a, respectively, and are electrically connected by metal wires 34b and 34a (Metal Wire). In addition, the inner lead 41 (inner lead) of the lower lead frame and the inner lead 51 of the upper lead frame form a step facing each other, are mechanically connected by the adhesive tape 32, and the fine metal wire 34c. ) Is electrically connected.

Of these two lead frames, the lower first lead frame has a shape of a typical lead frame including the inner lead 41 and the outer lead 42, but the second upper lead frame of the other upper side has a dam bar (FIG. 5). The inner lead 51 is cut away at a portion of 54 Dam Bar, so that only the inner lead 51 is included in the encapsulation resin region 35.

The outer lead 42 of the first lead frame, which is not sealed with the encapsulating resin, is an external connection terminal and has the same form as the external lead of TSOP or TSOJ.

Next, referring to FIG. 4, a plan view of the lower lead frame 40 of the stacked package shown in FIG. 3, in which the inner lead 41 and the outer lead 42 are integrally arranged in series and arranged on the dam bar 44. Are divided. The dam bar 44 and the tie bar 43 are connected to the side rails 45 to form a skeleton of the lead frame 40. Dam bar 44, tie bar 43 and side rails 45 are identical to those of a conventional lead frame.

The inner end of the inner lead 41 is bonded with a double-sided adhesive tape 31b for mechanical adhesion with the lower semiconductor chip 30b, and on the opposite side to which the adhesive tape 31b is bonded, the semiconductor chip 30b. And a plating region (not shown) for electrical connection is formed by the fine metal wire 34b, and the second lead frame (50 in FIG. 6) is formed inside the dam bar 44 of the inner lead 41. As shown in FIG. The plating region 36c is formed to be electrically connected by the fine metal wire 34c. In FIG. 4, reference numeral 32 denotes a part which is mechanically bonded to the second lead frame. The inner lead 41 forms a step (ie, is bent) between the two bonding portions 31b and 32, and the step height corresponds to the thickness of the semiconductor chip 30b.

Next, referring to FIGS. 5 and 6, FIG. 6 is a partial plan view showing the upper lead frame 50 of the stacked package shown in FIG. 3, and FIG. 5 is the original lead frame before being encapsulated in the form shown in FIG. 6. Form.

First, in the upper lead frame 50 shown in FIG. 5, the inner lead 51 and the outer lead 52 are integrally arranged and integrally arranged like the lower lead frame 40 (FIG. 4), and the dam bar 54. Separated by. The dam bar 54 and the tie bar 53 are connected to the side rails 55 to form a frame of the lead frame 50. The dam bar 54, tie bar 53 and side rail 55 are identical to that of the lower lead frame.

A double-sided adhesive tape 31a for mechanically bonding to the upper semiconductor chip 30a is attached to the inner end of the inner lead 51 and extends to the tie bar 53 to form an adhesive. A double-sided adhesive tape 32 for adhering to the first lead frame (40 in FIG. 4) is attached to the inner portion of the dam bar 54 of the inner lead 51. The adhesive tape 32 also extends to the side rails 55 to form an adhesive. The reason why the two adhesive tapes 31a and 32 adhere to the tie bars 53 and the side rails 55, respectively, is to be sealed into the package body 35 (encapsulation resin region) as shown in FIG. This is to support the inner lead 51 when it is cut.

At the inner end of the inner lead 51 which is in contact with the semiconductor chip 30a, a plating region 36a for electrical connection is formed by the semiconductor chip 30a and the fine metal wire 34a. In the inner portion of the dam bar 54 of 51, a plating region 36b is formed to be electrically connected to the first lead frame 40 (FIG. 4) by the metal thin wire 34c. The plating regions 36a and 36b are formed so as to have good connectivity between the fine metal wires 34b and 34c and the internal lead 51. The plating regions 36a and 36b may be implemented as a conventional plating method using a material such as silver (Ag).

Lastly, referring to FIGS. 3 to 6, a process of manufacturing the stacked package 300 of the present invention using the two lead frames 40 and 50 described so far will be described. First, the two lead frames 40, After the semiconductor chips 30a and 30b are bonded to each other and the electrical connection by the fine metal wires 34a and 34b, respectively, is carried out, the bonding means is attached to the surface of the lower semiconductor chip 30b while the lower lead frame 40 is turned over. (33) is applied and adhered to the semiconductor chip 30a adhered to the upper lead frame 50, and the lead frames 40 and 50 are also bonded between the lead frames 40 and 50 by using an adhesive means such as adhesive tape 32. Adhesion is carried out. After the electrical connection is performed between the two lead frames 40 and 50 with the fine metal wire 34c, the sealing is carried out with the encapsulating resin 35 and the finishing process such as cutting and bending is performed as in a conventional package. Complete the stacked package.

Therefore, according to the structure of the present invention, by implementing a laminated package in which two semiconductor chips are stacked in one package by using a conventional plastic package manufacturing equipment and a conventional lead frame, lamination due to bleeding or warpage of the encapsulating resin Defects can be prevented, and there is an advantage that it can be mass-produced without any extra investment cost.

Claims (5)

A first semiconductor chip and a second semiconductor chip each having a plurality of chip electrode pads formed thereon, and opposite surfaces of the surface on which the chip electrode pads are formed adhere to each other; A first lead frame mechanically and electrically connected to the first semiconductor chip; A second lead frame which is mechanically and electrically connected to the second semiconductor chip and is mechanically and electrically connected to the first lead frame; An encapsulation resin encapsulating the two semiconductor chips, a part of the first lead frame, and all of the second lead frame; Semiconductor chip stacked package comprising a. The semiconductor chip stack package according to claim 1, wherein a part of the first lead frame not encapsulated with the encapsulating resin is an external connection terminal and has the same form as an external lead of TSOP or TSOJ. The semiconductor chip stack package of claim 1, wherein the first semiconductor chip and the first lead frame are mechanically connected by an adhesive tape and electrically connected by a fine metal wire. The semiconductor chip stack package of claim 1, wherein the second semiconductor chip and the second lead frame are mechanically connected by an adhesive tape and electrically connected by a fine metal wire. The semiconductor chip stack type of claim 1, wherein the first lead frame and the second lead frame face each other in a stepped manner, are mechanically connected by an adhesive tape, and electrically connected by a fine metal wire. package.