JPH03268347A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03268347A JPH03268347A JP2066169A JP6616990A JPH03268347A JP H03268347 A JPH03268347 A JP H03268347A JP 2066169 A JP2066169 A JP 2066169A JP 6616990 A JP6616990 A JP 6616990A JP H03268347 A JPH03268347 A JP H03268347A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- mounting surface
- semiconductor chip
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 239000011347 resin Substances 0.000 claims description 19
- 229920005989 resin Polymers 0.000 claims description 19
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、配線基板の実装面
上に複数個の半導体チップを実装し、この配線基板及び
半導体チップをモールド封止した半導体装置に適用して
有効な技術に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular, a method for mounting a plurality of semiconductor chips on a mounting surface of a wiring board, and mold-sealing the wiring board and semiconductor chips. The present invention relates to techniques that are effective when applied to semiconductor devices.
配線基板の実装面上に複数個の半導体チップを実装し、
この配線基板及び半導体チップを樹脂でモールド封止し
た半導体装置が開発されている。Multiple semiconductor chips are mounted on the mounting surface of the wiring board,
A semiconductor device in which the wiring board and semiconductor chip are molded and sealed with resin has been developed.
本発明者が開発中の半導体装置は、第４図（断面図）に
示すように、例えばＤ Ｉ Ｐ （Ｄｕａｌ Ｉ ｎ−
１ｉｎｅ Ｐ ａｃｋａｇｅ）型の樹脂封止型パッケー
ジ１で構成されている。前記半導体装置は、リードフレ
ームのタブ７Ｃ上に配線基板２を搭載している。この配
線基板２の実装面上には、複数個の半導体チップ３を実
装している。前記半導体チップ３はボンディングワイヤ
ー５で配線基板２と電気的に接続され、配線基板２はボ
ンディングワイヤー６でリードピン（インナーリード７
Ａ及びアウターリード７Ｂ）７と電気的に接続されてい
る。As shown in FIG. 4 (cross-sectional view), the semiconductor device currently being developed by the present inventor is, for example, a DIP (Dual In-
1ine package) type resin-sealed package 1. The semiconductor device has a wiring board 2 mounted on a tab 7C of a lead frame. A plurality of semiconductor chips 3 are mounted on the mounting surface of this wiring board 2. The semiconductor chip 3 is electrically connected to the wiring board 2 by a bonding wire 5, and the wiring board 2 is connected to a lead pin (inner lead 7) by a bonding wire 6.
A and the outer lead 7B) 7 are electrically connected.
前記タブフＣ１配線基板２、半導体チップ３、ボンディ
ングワイヤー５，６及びインナーリード７Ａは、例えば
絶縁性のエポキシ系樹脂ＩＡでモールド封止されている
。The Tabuf C1 wiring board 2, semiconductor chip 3, bonding wires 5 and 6, and inner leads 7A are molded and sealed with, for example, an insulating epoxy resin IA.
前記配線基板２は、例えば絶縁性のガラスポリイミド系
樹脂基板の表面に配線が施されたプリント配線基板を複
数枚積み重ねた多層配線構造で構成されている。前記半
導体チップ３は１例えばＩＭ［ｂｉｔコＸ １ ［ｂｉ
ｔコの容量のマスクＲＯＭ（Ｒｅａｄ ０ｎｌｙ Ｍｅ
ｍｏｒｙ）で構成されている。この半導体チップ３は図
示していないが前記配線基板２の主面上に絶縁材を介在
させ、接着剤で固定されている。The wiring board 2 has a multilayer wiring structure in which a plurality of printed wiring boards each having wiring provided on the surface of, for example, an insulating glass polyimide resin board are stacked. The semiconductor chip 3 is 1, for example, IM [bit
t capacity mask ROM (Read Only Me
It is composed of Although not shown, this semiconductor chip 3 is fixed on the main surface of the wiring board 2 with an adhesive with an insulating material interposed therebetween.
この種の半導体装置はメモリモジュールとして、例えば
メモリボード、ＣＰＵ等の実装基板に複数個搭載される
。この半導体装置は、複数個の半導体チップ３を個々に
モールド封止した場合に比べて、複数個の半導体チップ
３の夫々のモールド封止に共用領域を有するので、実装
基板に搭載される半導体チップ３の搭載個数（実装密度
）を高めることができる特徴がある。A plurality of semiconductor devices of this type are mounted as memory modules on a mounting board such as a memory board or a CPU. This semiconductor device has a common area in the mold sealing of each of the plurality of semiconductor chips 3, compared to a case where the plurality of semiconductor chips 3 are individually mold-sealed. It has the feature that it can increase the number (packing density) of No. 3.
なお、モールド封止型半導体装置については、例えば、
応用技術出版株式会社、最近の半導体アセンブリ技術と
その高信頼化、全自動化、第１２２頁及び第１２３頁に
記載されている。For mold-sealed semiconductor devices, for example,
It is described in Applied Technology Publishing Co., Ltd., Recent Semiconductor Assembly Technology, Its High Reliability, and Full Automation, pages 122 and 123.
前記半導体装置は、配線基板２をモールド封止している
ため、この配線基板２の厚さに相当する分、厚さが厚く
なり、パッケージ１の厚みの制約からボンディングワイ
ヤー５のループの高さを高くすることができない６ボン
デイングワイヤー５は、半導体チップ３のポンディング
パッドから一旦上方に引き上げられ、この引き上げられ
た位置から半導体チップ３の厚さに相当する段差下の配
線基板２の表面まで引き回される。つまり、急峻なルー
プでボンディングワイヤー５を引き回すので、半導体チ
ップ３の端部とボンディングワイヤー５との隙間Ｙが狭
くなる。特に、エポキシ系樹脂ＩＡでモールド封止する
場合、金型に注入されるエポキシ系樹脂ＩＡは粘度を有
するのでボンディングワイヤー５が変形しゃすい。よっ
て、半導体チップ３の端部とボンディングワイヤー５と
が短絡するという問題があった。Since the semiconductor device has the wiring board 2 sealed in a mold, the thickness becomes thicker by an amount corresponding to the thickness of the wiring board 2, and the height of the loop of the bonding wire 5 is limited due to the restriction of the thickness of the package 1. The bonding wire 5, which cannot be made high, is once lifted upward from the bonding pad of the semiconductor chip 3, and from this lifted position to the surface of the wiring board 2 under the step corresponding to the thickness of the semiconductor chip 3. being dragged around. That is, since the bonding wire 5 is routed in a steep loop, the gap Y between the end of the semiconductor chip 3 and the bonding wire 5 becomes narrow. In particular, when mold-sealing with epoxy resin IA, the bonding wire 5 is easily deformed because the epoxy resin IA injected into the mold has viscosity. Therefore, there was a problem in that the end of the semiconductor chip 3 and the bonding wire 5 were short-circuited.
本発明の目的は、複数個の半導体チップを実装した配線
基板をモールド封止する半導体装置において、半導体チ
ップの端部とボンディングワイヤーとの短絡を防止する
ことが可能な技術を提供することにある。An object of the present invention is to provide a technique that can prevent short circuits between the ends of semiconductor chips and bonding wires in a semiconductor device that mold-seals a wiring board on which a plurality of semiconductor chips are mounted. .
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
配線基板の実装面上に半導体チップを実装し。A semiconductor chip is mounted on the mounting surface of a wiring board.
この半導体チップの外部端子と前記配線基板の実装面上
の端子とをボンディングワイヤーで電気的に接続し、前
記配線基板及び半導体チップを樹脂でモールド封止した
半導体装置において、前記配線基板の実装面上に凹部を
設け、この凹部に前記半導体チップを実装する。In the semiconductor device, an external terminal of the semiconductor chip and a terminal on the mounting surface of the wiring board are electrically connected with a bonding wire, and the wiring board and the semiconductor chip are molded and sealed with resin. A recess is provided on the top, and the semiconductor chip is mounted in this recess.
上述した手段によれば、配線基板の実装面の端子の位置
と半導体チップの外部端子の位置との差（高さ）を縮小
し、半導体チップの端部とボンディングワイヤーとの隙
間を広くすることがでる。よって、半導体チップの端部
とボンディングワイヤーとの短絡を防止することができ
、半導体装置の電気的信頼性を向上できる。According to the above-mentioned means, the difference (height) between the position of the terminal on the mounting surface of the wiring board and the position of the external terminal of the semiconductor chip can be reduced, and the gap between the end of the semiconductor chip and the bonding wire can be widened. comes out. Therefore, short circuits between the ends of the semiconductor chip and the bonding wires can be prevented, and the electrical reliability of the semiconductor device can be improved.
以下、本発明の構成について、樹脂モールド型半導体装
置に本発明を適用した一実施例とともに説明する。Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to a resin molded semiconductor device.
なお、実施例を説明するための全図において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
本発明の一実施例である樹脂モールド型半導体装置を第
１図（樹脂モールドの上部を除去した状態の平面図）及
び第２図（第１図の■−■線で切った断面図）に示す。A resin molded semiconductor device according to an embodiment of the present invention is shown in FIG. 1 (a plan view with the upper part of the resin mold removed) and FIG. 2 (a sectional view taken along the line ■-■ in FIG. 1). show.
第１図及び第２図に示すように、樹脂モールド型半導体
装置はＤ Ｉ Ｐ（Ｄｕａｌ Ｉｎ−１ｉｎｅ Ｐａｃ
ｋａｇｅ）型のパッケージ１で構成されている。この樹
脂モールド型半導体装置は、リードフレームのタブ７Ｃ
上に配線基板２を介在して複数個の半導体チップ３を搭
載している。As shown in FIGS. 1 and 2, the resin molded semiconductor device is a DIP (Dual In-line Pac)
It consists of a package 1 of the type Kage). This resin molded semiconductor device has tab 7C of the lead frame.
A plurality of semiconductor chips 3 are mounted thereon with a wiring board 2 interposed therebetween.
前記半導体チップ３のうち、例えばＩＭＥｂｉｔ］Ｘ
ｌ ［Ｍｔ］の容量のマスクＲＯＭ （Ｒｅａｄ Ｏｎ
ｌｙＭ ｅｍｏｒｙ）で構成された半導体チップ３Ａが
２個搭載されている。前記半導体チップ３のうち、例え
ば半導体チップ３Ａの動作を制御する５ＳＩ（Ｓ＋ａａ
ｌｌ ５ｃａｌｅ Ｉｎｔｅｇｒａｔｅｄ Ｃ１ｒｃｕ
ｉｔ：小規模集積回路）で構成された半導体チップ３Ｂ
が１個搭載されている。Among the semiconductor chips 3, for example, IMEbit]X
l [Mt] capacity mask ROM (Read On
Two semiconductor chips 3A each configured with lyMemory are mounted. Among the semiconductor chips 3, for example, 5SI (S+aa
ll 5cale Integrated C1rcu
it: Semiconductor chip 3B composed of small-scale integrated circuit)
One is installed.
前記半導体チップ３Ａ、３Ｂの夫々は平面が方形状の例
えば単結晶珪素基板で構成されている。Each of the semiconductor chips 3A and 3B is composed of, for example, a single-crystal silicon substrate having a rectangular plane.
半導体チップ３Ａ、３Ｂの夫々の主面上には、方形状の
各辺に沿った最外周部分に複数の外部端子（ポンディン
グパッド）ＢＰが配置されている。この外部端子ＢＰは
、半導体チップ３の内部に形成された素子と電気的に接
続されている。On the main surface of each of the semiconductor chips 3A and 3B, a plurality of external terminals (ponding pads) BP are arranged at the outermost periphery along each side of the rectangular shape. This external terminal BP is electrically connected to an element formed inside the semiconductor chip 3.
前記配線基板２は平面が長方形状で構成されている。こ
の配線基板２の実装面上には、長方形状の長辺に沿った
最外周部分に形成された複数の端子２ｂと前記半導体チ
ップ３Ａ、３Ｂの夫々に配置された外部端子ＢＰに沿っ
て形成された複数の端子２ａとが配置されている。前記
端子２ａと端子２ｂとは配線基板２に形成された多層配
線構造（又は単層配線構造）の配線で電気的に接続され
ている。The wiring board 2 has a rectangular plane. On the mounting surface of the wiring board 2, a plurality of terminals 2b are formed at the outermost periphery along the long sides of the rectangular shape, and external terminals BP are formed on each of the semiconductor chips 3A and 3B. A plurality of terminals 2a are arranged. The terminals 2a and 2b are electrically connected by wiring of a multilayer wiring structure (or a single layer wiring structure) formed on the wiring board 2.
前記端子２ａは、ボンディングワイヤー５を介在させて
半導体チップ３Ａ、３Ｂの夫々の外部端子ＢＰと電気的
に接続されている。前記端子２ｂは、ボンディングワイ
ヤー６を介在させてリードビン（インナーリード７Ａ及
びアウターリード７Ｂ）７と電気的に接続されている。The terminal 2a is electrically connected to the external terminal BP of each of the semiconductor chips 3A and 3B with a bonding wire 5 interposed therebetween. The terminal 2b is electrically connected to a lead bin (inner lead 7A and outer lead 7B) 7 with a bonding wire 6 interposed therebetween.
ボンディングワイヤー５．６の夫々は、例えばアルミニ
ウム（Ａｌ）ワイヤーを使用する。また、ボンディング
ワイヤー５．６の夫々は金（Ａｕ）ワイヤーを使用して
もよい、このボンディングワイヤー５．６は、例えば熱
圧着に超音波振動を併用したボンディング法によりボン
ディングされている。Each of the bonding wires 5.6 uses, for example, an aluminum (Al) wire. Further, each of the bonding wires 5.6 may be a gold (Au) wire, and the bonding wires 5.6 are bonded, for example, by a bonding method that uses thermocompression bonding in combination with ultrasonic vibration.
前記半導体チップ３Ａ、３Ｂの夫々は、配線基板２の実
装面に形成された凹部２Ａ内に実装されている。つまり
、凹部２Ａの開口サイズは半導体チップ３の平面形状に
比べて、ひとまわり大きなサイズで形成され、凹部２Ａ
の底面の位置は配線基板２の実装面の位置よりも低く構
成されている。Each of the semiconductor chips 3A and 3B is mounted in a recess 2A formed on the mounting surface of the wiring board 2. In other words, the opening size of the recess 2A is slightly larger than the planar shape of the semiconductor chip 3.
The position of the bottom surface of is configured to be lower than the position of the mounting surface of the wiring board 2.
従って、前記半導体チップ３Ａ、３Ｂの夫々の外部端子
ＢＰの位置と配線基板２の端子２ａの位置との差（高さ
）は、凹部２Ａの深さ分、小く構成されている。これに
より、ボンディングワイヤー５の引き回しを緩やかにす
ることができ、半導体チップ３Ａ、３Ｂの夫々の端部と
ボンディングワイヤー５との間の隙間Ｙを広くすること
ができる。Therefore, the difference (height) between the position of the external terminal BP of each of the semiconductor chips 3A, 3B and the position of the terminal 2a of the wiring board 2 is made smaller by the depth of the recess 2A. Thereby, the routing of the bonding wire 5 can be made gentler, and the gap Y between each end of the semiconductor chips 3A, 3B and the bonding wire 5 can be widened.
つまり、半導体チップ３のエリアショートのマージンを
大きくすることができる。In other words, the margin of area short circuit of the semiconductor chip 3 can be increased.
前記半導体チップ３Ａ、３Ｂの夫々は、配線基板２の実
装面に形成された凹部２Ａ内に導電性の接着剤で接着固
定されている。導電性の接着剤としては、例えば銀（Ａ
ｇ）エポキシペーストが使用されている。この導電性の
接着剤は、凹部２Ａ内の実装面に塗布されるので、前記
半導体チップ３Ａ、３Ｂの夫々を実装した時、凹部２Ａ
外の配線基板２の他の部分に流出することがない。つま
り、配線基板２の実装面に凹部２Ａを形成することによ
り、前記導電性の接着剤のはみ出しを防止することがで
きると共に、充分に接着剤を供給することができるので
、配線基板２と半導体チップ３との接着性を向上するこ
とができる。なお、接着剤としては絶縁性のものでもよ
い。Each of the semiconductor chips 3A and 3B is adhesively fixed in a recess 2A formed in the mounting surface of the wiring board 2 using a conductive adhesive. As the conductive adhesive, for example, silver (A
g) Epoxy paste is used. This conductive adhesive is applied to the mounting surface in the recess 2A, so when the semiconductor chips 3A and 3B are mounted, the recess 2A
It does not leak to other parts of the external wiring board 2. In other words, by forming the recess 2A on the mounting surface of the wiring board 2, it is possible to prevent the conductive adhesive from protruding, and also to supply a sufficient amount of adhesive. Adhesion to the chip 3 can be improved. Note that the adhesive may be insulating.
前記配線基板２は、第３図（第２図の要部拡大断面図）
に示すように、凹部２Ａが形成されたベース基板２ｃの
主面上に配線層２ｄを設け、この配線層２ｄの主面上に
絶縁材２ｅを設けた構成になっている。ベース基板２Ｃ
は例えばエポキシ系樹脂で形成され、前記凹部２Ａを含
め、このベース基板２ｃは樹脂成型により形成されてい
る。配線層２ｄは、例えば配線が施されたポリイミド系
樹脂フィルムを複数枚積み重ねた多層配線構造で形成さ
れている。この配線層２ｄの配線は例えば銅（Ｃｕ）で
構成されている。絶縁材（レジスト材）２ｅは配線基板
２の全面に形成されている。この絶縁材２ｅには、ボン
デインゲンワイヤー５，６の夫々が接続される配線層２
ｄに形成された端子２ａ、２ｂの夫々の配置に合せて接
続孔５ａ、６ａの夫々が形成されている。The wiring board 2 is shown in FIG. 3 (an enlarged sectional view of the main part of FIG. 2).
As shown in FIG. 2, a wiring layer 2d is provided on the main surface of the base substrate 2c in which the recess 2A is formed, and an insulating material 2e is provided on the main surface of the wiring layer 2d. Base board 2C
is made of, for example, epoxy resin, and the base substrate 2c, including the recess 2A, is formed by resin molding. The wiring layer 2d is formed, for example, of a multilayer wiring structure in which a plurality of polyimide resin films provided with wiring are stacked. The wiring of this wiring layer 2d is made of copper (Cu), for example. An insulating material (resist material) 2e is formed on the entire surface of the wiring board 2. A wiring layer 2 to which bonding wires 5 and 6 are connected to the insulating material 2e.
Connection holes 5a and 6a are formed in accordance with the respective locations of terminals 2a and 2b formed in d.
前記タブ７Ｃ、インナーリード７Ａ、配線基板２、半導
体チップ３Ａ、３Ｂの夫々は、低応力化を図るために例
えばフェノール系硬化剤、シリコーンゴム及びフィラー
が添加された絶縁性のエポキシ系樹脂ＩＡでモールド封
止されている。シリコーンゴムはエポキシ系樹脂の弾性
率と熱膨張率を低下させる作用がある。フィラーは球形
の酸化珪素粒で形成されており、同様に熱膨張率を低下
させる作用がある。Each of the tabs 7C, inner leads 7A, wiring board 2, and semiconductor chips 3A and 3B is made of insulating epoxy resin IA to which, for example, a phenolic curing agent, silicone rubber, and filler are added in order to reduce stress. Mold sealed. Silicone rubber has the effect of lowering the elastic modulus and thermal expansion coefficient of epoxy resin. The filler is made of spherical silicon oxide particles, and similarly has the effect of lowering the coefficient of thermal expansion.
このように、配線基板２の実装面上に複数個の半導体チ
ップ３を実装し、この半導体チップ３の外部端子と配線
基板２の実装面上の端子とをボンディングワイヤー５で
電気的に接続し、前記配線基板２及び半導体チップ３を
樹脂でモールド封止した樹脂モールド型半導体装置にお
いて、前記配線基板２の実装面上に凹部２Ａを設け、こ
の凹部２Ａ内に半導体チップ３を実装する。この構成に
より、前記配線基板２の実装面の端子２ａの位置と半導
体チップ３の外部端子ＢＰの位置との差を縮小すること
ができ、半導体チップ３の端部とボンディングワイヤー
５との隙間Ｙを広くすることができる。よって、半導体
チップ３の端部とボンディングワイヤー５との短絡を防
止することができ、樹脂モールド型半導体装置の電気的
信頼性を向上できる。In this way, a plurality of semiconductor chips 3 are mounted on the mounting surface of the wiring board 2, and the external terminals of the semiconductor chips 3 and the terminals on the mounting surface of the wiring board 2 are electrically connected with the bonding wires 5. In a resin-molded semiconductor device in which the wiring board 2 and the semiconductor chip 3 are mold-sealed with resin, a recess 2A is provided on the mounting surface of the wiring board 2, and the semiconductor chip 3 is mounted in the recess 2A. With this configuration, the difference between the position of the terminal 2a on the mounting surface of the wiring board 2 and the position of the external terminal BP of the semiconductor chip 3 can be reduced, and the gap Y between the end of the semiconductor chip 3 and the bonding wire 5 can be reduced. can be made wider. Therefore, short circuit between the end of the semiconductor chip 3 and the bonding wire 5 can be prevented, and the electrical reliability of the resin molded semiconductor device can be improved.
また、前記配線基板２の凹部２Ａの実装面に半導体チッ
プ３を接着固定する接着剤を凹部２Ａ内に充分に補給す
ることができるので、配線基板２と半導体チップ３との
接着性を向上することができる。Further, since the adhesive for bonding and fixing the semiconductor chip 3 to the mounting surface of the recess 2A of the wiring board 2 can be sufficiently supplied in the recess 2A, the adhesiveness between the wiring board 2 and the semiconductor chip 3 is improved. be able to.
以上、本発明者によってなされた発明を、前記実施例に
基づき具体的に説明したが、本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて種々変更可能であることは勿論である。As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
配線基板の実装面上に複数個の半導体チップを実装し、
この半導体チップの外部端子と前記配線基板の実装面上
の端子とをボンディングワイヤーで電気的に接続し、前
記配線基板及び半導体チップを樹脂でモールド封止した
半導体装置において、前記半導体チップの端部とボンデ
ィングワイヤーとの短絡を防止することができるので、
半導体装置の電気的信頼性を向上することができる。Multiple semiconductor chips are mounted on the mounting surface of the wiring board,
In a semiconductor device in which an external terminal of the semiconductor chip and a terminal on the mounting surface of the wiring board are electrically connected with a bonding wire, and the wiring board and the semiconductor chip are molded and sealed with resin, an end of the semiconductor chip This can prevent short circuits between the wire and the bonding wire.
The electrical reliability of a semiconductor device can be improved.
第１図は、本発明の一実施例である樹脂モールド型半導
体装置の樹脂モールドの上部部分を削除した状態の概略
構成を示す平面図、
第２図は、第１図の■−■線で切った断面図。
第３図は、第２図の要部拡大断面図、
第４図は、従来の樹脂モールド型半導体装置の断面図で
ある。
図中、１・・・樹脂モールド型半導体装置、２・・・配
線基板、２Ａ・・・凹部、２ａ、２ｂ・・・端子、ＢＰ
・・外部端子、３・・・半導体チップ、５，６ボンデイ
ングワイヤー、７・・・リードピンである。FIG. 1 is a plan view showing a schematic configuration of a resin molded semiconductor device according to an embodiment of the present invention, with the upper part of the resin mold removed. FIG. A cut sectional view. FIG. 3 is an enlarged sectional view of the main part of FIG. 2, and FIG. 4 is a sectional view of a conventional resin molded semiconductor device. In the figure, 1...resin molded semiconductor device, 2...wiring board, 2A...recess, 2a, 2b...terminal, BP
. . . external terminal, 3 . . . semiconductor chip, 5, 6 bonding wires, 7 . . . lead pin.
Claims (1)
し、この半導体チップの外部端子と前記配線基板の実装
面上の端子とをボンディングワイヤーで電気的に接続し
、前記配線基板及び半導体チップを樹脂でモールド封止
した半導体装置において、前記配線基板の実装面に凹部
を設け、この凹部内に半導体チップを実装したことを特
徴とする半導体装置。 ２、前記配線基板は、成形された実装面側に凹部をもつ
絶縁性の樹脂ベース基板と、この樹脂ベース基板基板の
主面上に設けられた多層配線構造をもつ絶縁性の樹脂フ
ィルム基板とで構成されたことを特徴とする請求項１に
記載の半導体装置。[Claims] 1. A plurality of semiconductor chips are mounted on a mounting surface of a wiring board, and external terminals of the semiconductor chips and terminals on the mounting surface of the wiring board are electrically connected with bonding wires. . A semiconductor device in which the wiring board and the semiconductor chip are mold-sealed with resin, wherein a recess is provided on the mounting surface of the wiring board, and the semiconductor chip is mounted in the recess. 2. The wiring board includes an insulating resin base board having a recess on the molded mounting surface side, and an insulating resin film board having a multilayer wiring structure provided on the main surface of the resin base board. 2. The semiconductor device according to claim 1, wherein the semiconductor device is comprised of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2066169A JPH03268347A (en) | 1990-03-16 | 1990-03-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2066169A JPH03268347A (en) | 1990-03-16 | 1990-03-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03268347A true JPH03268347A (en) | 1991-11-29 |
Family
ID=13308082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2066169A Pending JPH03268347A (en) | 1990-03-16 | 1990-03-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03268347A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009212360A (en) * | 2008-03-05 | 2009-09-17 | Renesas Technology Corp | Semiconductor device, and manufacturing method and mounting method therefor |
-
1990
- 1990-03-16 JP JP2066169A patent/JPH03268347A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009212360A (en) * | 2008-03-05 | 2009-09-17 | Renesas Technology Corp | Semiconductor device, and manufacturing method and mounting method therefor |
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