JPH06244313A - Semiconductor package and mounting method - Google Patents
Semiconductor package and mounting methodInfo
- Publication number
- JPH06244313A JPH06244313A JP5028730A JP2873093A JPH06244313A JP H06244313 A JPH06244313 A JP H06244313A JP 5028730 A JP5028730 A JP 5028730A JP 2873093 A JP2873093 A JP 2873093A JP H06244313 A JPH06244313 A JP H06244313A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- package
- semiconductor element
- semiconductor package
- semiconductor chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体パッケージの構成
と実装方法に関し、例えばメモリー素子のパッケージに
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure and a mounting method, for example, a memory device package.
【０００２】[0002]
【従来の技術】近年、電子機器の小型、薄型、高性能化
の傾向は著しく、これにともない電子部品を高密度実装
する技術が求められている。特にメモリーをはじめとす
る半導体素子の分野ではこの傾向が強く、より薄型、低
コスト、高密度実装に適した半導体パッケージが求めら
れている。2. Description of the Related Art In recent years, there has been a remarkable trend toward miniaturization, thinness and high performance of electronic equipment, and accordingly, a technology for mounting electronic parts at high density is required. This tendency is particularly strong in the field of semiconductor devices such as memories, and there is a demand for semiconductor packages that are thinner, lower in cost, and suitable for high-density mounting.
【０００３】ＤＲＡＭ等のメモリー素子の場合、以前は
セラミックパッケージが主流であったが、前記要求から
現在はプラスチックモールドによるパッケージが主流と
なっており、その中でも挿入型に比べ高密度実装に有利
な面実装型の需要が増えている。面実装型のプラスチッ
クモールドによるパッケージは実装形態によりＳＯＰ、
ＳＯＪ（Small Outline J-bend Package）等多くの種類
があるが、メモリーパッケージ、特にＤＲＡＭパッケー
ジにおいては現在ＳＯＪ型のパッケージが主流にある。In the case of memory elements such as DRAMs, ceramic packages have been the mainstream before, but nowadays plastic packages are the mainstream because of the above requirements, and among them, it is advantageous for high-density mounting as compared with the insertion type. Demand for surface mount type is increasing. The surface mount type plastic mold package has SOP,
Although there are many types such as SOJ (Small Outline J-bend Package), SOJ type packages are currently the mainstream in memory packages, especially DRAM packages.
【０００４】以下図面を参照しながら、従来のＳＯＪ型
のプラスチックモールドによる半導体パッケージの一例
について説明する。図８（ａ）、（ｂ）、（ｃ）は、そ
れぞれ従来のＳＯＪ型の半導体パッケージの上面図、側
面図、正面図を示すものである。また図９はそのＡ−
Ａ’面での断面図である。An example of a conventional semiconductor package using an SOJ type plastic mold will be described below with reference to the drawings. 8A, 8B, and 8C are a top view, a side view, and a front view, respectively, of a conventional SOJ type semiconductor package. In addition, FIG. 9 shows the A-
It is sectional drawing in A'plane.
【０００５】図８、図９において、２１は半導体素子、
２２は封止樹脂、２３はリード、２４はダイパッド、２
５はＡｌ電極、２６はＡｌワイヤである。半導体素子２
１はＡｇペーストによりダイパッド２４に固定され、半
導体素子２１のＡｌ電極２５はＡｌワイヤ２６によりリ
ード２３に接続され、これを封止樹脂２２が封止してい
る。リード２３は半導体素子２１から半導体パッケージ
外部に導出され、Ｊ型の形状で内側に折り曲げられてい
る。In FIGS. 8 and 9, reference numeral 21 denotes a semiconductor element,
22 is a sealing resin, 23 is a lead, 24 is a die pad, 2
Reference numeral 5 is an Al electrode, and 26 is an Al wire. Semiconductor element 2
1 is fixed to the die pad 24 by Ag paste, the Al electrode 25 of the semiconductor element 21 is connected to the lead 23 by the Al wire 26, and this is sealed by the sealing resin 22. The lead 23 is led out of the semiconductor package from the semiconductor element 21 and is bent inward in a J-shape.
【０００６】近年の電子機器では、非常に多くの半導体
パッケージ（特にメモリー等の半導体パッケージ）を回
路基板上に登載する必要があり、この場合は図１０に示
すように、複数の半導体パッケージを横に並べて実装す
る。In the recent electronic equipment, it is necessary to mount a great number of semiconductor packages (especially semiconductor packages such as memories) on a circuit board. In this case, as shown in FIG. To be installed side by side.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、従来の
半導体パッケージをいくつも回路基板上に搭載すると、
その分だけ実装面積が増大し、実装の手間も多くなる。
特にメモリー等の非常に多くのパッケージを必要とする
場合は、実装面積が非常に大きくなり、高コスト化す
る。このため、電子機器の小型化、低コスト化の障害に
なってきた。However, when many conventional semiconductor packages are mounted on a circuit board,
As a result, the mounting area increases, and the mounting time increases.
In particular, when a very large number of packages such as memories are required, the mounting area becomes very large and the cost increases. This has been an obstacle to downsizing and cost reduction of electronic devices.
【０００８】複数のメモリーチップを一つのパッケージ
に搭載することもできるが、この場合、メモリーチップ
をパッケージ内に搭載する手間が増大し、また、パッケ
ージ内のメモリーチップの数があらかじめ決まってしま
うため、汎用性がなくなる。It is possible to mount a plurality of memory chips in one package, but in this case, the labor for mounting the memory chips in the package increases, and the number of memory chips in the package is predetermined. , Loses versatility.
【０００９】一方、複数のパッケージをモジュール化す
る方法もあるが、この方法ではパッケージを基板に搭載
する手間がかかり、実装面積もあまり小さくできない。On the other hand, there is also a method of modularizing a plurality of packages, but this method requires a lot of labor to mount the packages on the substrate and the mounting area cannot be reduced so much.
【００１０】本発明は上記問題点に鑑み、低コストで複
数の半導体素子を高密度で、しかも汎用性のある形で収
納可能とする半導体パッケージを提供するものである。In view of the above problems, the present invention provides a semiconductor package that can accommodate a plurality of semiconductor elements at a low cost with a high density and in a versatile manner.
【００１１】[0011]
【課題を解決するための手段】上記問題点を解決するた
めに本発明では、半導体素子、半導体素子の電極に接続
されたリード材、半導体素子とリード材の一部を被覆し
た成形樹脂からなる半導体パッケージにおいて、分割領
域を共有した半導体素子が１方向に並んで配置され、リ
ード材の一部が、半導体素子が分割領域を有していない
辺の方向から、成形樹脂の外部まで導出され、分割領域
で成形樹脂の厚みが薄くなっており、分割領域でありか
つ成形樹脂の厚みが薄くなっている領域で半導体パッケ
ージが個々に分割可能とした。In order to solve the above problems, the present invention comprises a semiconductor element, a lead material connected to an electrode of the semiconductor element, and a molding resin which covers the semiconductor element and a part of the lead material. In the semiconductor package, the semiconductor elements sharing the divided region are arranged side by side in one direction, and a part of the lead material is led out of the molding resin from the direction of the side where the semiconductor element does not have the divided region, The thickness of the molding resin is thin in the divided regions, and the semiconductor packages can be individually divided in the divided regions and the regions where the molding resin is thin.
【００１２】[0012]
【作用】本発明は上記した構成により、複数の半導体素
子を最小面積でまとめてパッケージ内に収納できるた
め、パッケージの実装面積が縮小し、実装工程が減少す
る。また、半導体素子の辺の上下に形成した半導体パッ
ケージの分割領域で半導体パッケージを分割することに
より、半導体素子を個別の半導体パッケージに分離する
ことができ、使用する電子機器に応じて必要な数の半導
体素子を有するパッケージになる。According to the present invention, since the plurality of semiconductor elements can be collectively housed in the package with the minimum area by the above-mentioned structure, the mounting area of the package is reduced and the mounting process is reduced. Further, by dividing the semiconductor package at the division regions of the semiconductor package formed above and below the sides of the semiconductor element, the semiconductor element can be separated into individual semiconductor packages, and the required number of semiconductor devices can be obtained according to the electronic device used. The package has a semiconductor element.
【００１３】[0013]
【実施例】以下本発明の一実施例のプラスチックモール
ドによる半導体パッケージの構造について、図面を参照
しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a semiconductor package formed by a plastic mold according to an embodiment of the present invention will be described below with reference to the drawings.
【００１４】図１（ａ）、（ｂ）、（Ｃ）は、本発明の
実施例におけるＳＯＪ型の半導体パッケージのそれぞれ
正面図、側面図、上面図を示すものである。図２
（ａ）、（ｂ）、（Ｃ）は、本発明のＳＯＪ型の半導体
パッケージの内部構造のそれぞれ正面図、側面図、上面
図を示すものである。1 (a), 1 (b) and 1 (C) are a front view, a side view and a top view of an SOJ type semiconductor package according to an embodiment of the present invention, respectively. Figure 2
(A), (b), (C) is a front view, a side view, and a top view, respectively, of the internal structure of the SOJ type semiconductor package of the present invention.
【００１５】図１、図２において、１は封止樹脂、２は
半導体素子、３はリード、４はポリイミドテープ、５は
Ａｕワイヤ、６は半導体素子２の電極、７は半導体パッ
ケージの分割用の肉薄部、８は半導体素子の分割領域で
ある。In FIGS. 1 and 2, 1 is a sealing resin, 2 is a semiconductor element, 3 is a lead, 4 is a polyimide tape, 5 is an Au wire, 6 is an electrode of the semiconductor element 2, and 7 is for dividing a semiconductor package. Is a thin portion, and 8 is a divided region of the semiconductor element.
【００１６】半導体パッケージは、複数の同一の半導体
素子２を短辺を切り放さずに１列に並べて収納してい
る。実装する半導体素子２はメモリーチップを想定し、
チップ中央に電極６を一列に配列した。今回の実施例で
は簡略のため６個の半導体素子２による実施例とした。
半導体素子２の主面上にはリード３が導出されており、
半導体素子２とリード３はポリイミドテープ４を介して
接着されている。ポリイミドテープ４は両面にポリアミ
ドイミドがあらかじめ塗布されており、半導体素子２や
リード３はこのポリアミドイミドによりポリイミドテー
プに接着される。リードには４２アロイやＣｕ等を用い
る。リード３の内部端子は半導体素子２の電極６近傍ま
で導出され、Ａｕワイヤ５で半導体素子の電極６と接続
される。The semiconductor package accommodates a plurality of identical semiconductor elements 2 arranged in a line without cutting off the short sides. The semiconductor element 2 to be mounted is assumed to be a memory chip,
The electrodes 6 were arranged in a line at the center of the chip. In this example, for the sake of simplification, an example using six semiconductor elements 2 is used.
The leads 3 are led out on the main surface of the semiconductor element 2.
The semiconductor element 2 and the lead 3 are adhered via a polyimide tape 4. Polyamideimide is applied on both sides of the polyimide tape 4 in advance, and the semiconductor element 2 and the leads 3 are bonded to the polyimide tape by this polyamideimide. 42 alloy or Cu is used for the lead. The internal terminal of the lead 3 is led out to the vicinity of the electrode 6 of the semiconductor element 2, and is connected to the electrode 6 of the semiconductor element by the Au wire 5.
【００１７】一方、リード３の外部端子は半導体素子２
の長辺側からパッケージ外部に導出され、パッケージ外
端部で内側に向かってＪ型の形状に折り曲げられてい
る。更に一つの半導体素子２から導出されたリード３の
外部端子はその半導体素子２の長辺内にのみ配置され、
他の半導体素子２の辺にはまたがらない。封止樹脂１に
はエポキシ樹脂を用い、トランスファーモールドによ
り、半導体素子２とリード３の内部端子が封止されてい
る。半導体パッケージは後述するように、それぞれの半
導体素子２が分離可能なように、半導体素子２の短辺に
はあらかじめ分割領域８が形成されている。また、前記
切削部８の上下で封止樹脂１に分割領域の肉薄部７を形
成した。On the other hand, the external terminal of the lead 3 is the semiconductor element 2
Is led out to the outside of the package from the long side, and is bent inward into a J shape at the outer end of the package. Furthermore, the external terminals of the leads 3 derived from one semiconductor element 2 are arranged only within the long side of the semiconductor element 2,
It does not straddle the sides of the other semiconductor elements 2. An epoxy resin is used as the sealing resin 1, and the semiconductor element 2 and the internal terminals of the leads 3 are sealed by transfer molding. As will be described later, in the semiconductor package, divided regions 8 are formed in advance on the short sides of the semiconductor elements 2 so that the respective semiconductor elements 2 can be separated. In addition, thin portions 7 of divided regions were formed in the sealing resin 1 above and below the cutting portion 8.
【００１８】本実施例の半導体パッケージの工程図を図
３の断面図を用いて示す。まず図３（ａ）のように熱圧
着によりポリアミドイミドを溶融させ、リード３にポリ
イミドテープ４を接着する。熱圧着条件は３６０℃、４
０Ｋｇ／ｍｍ2×数秒程度である。A process drawing of the semiconductor package of this embodiment is shown using the sectional view of FIG. First, as shown in FIG. 3A, the polyamide-imide is melted by thermocompression bonding, and the polyimide tape 4 is bonded to the lead 3. Thermocompression bonding conditions are 360 ° C, 4
It is about 0 Kg / mm 2 × several seconds.
【００１９】ついで、図３（ｂ）のように両側の短辺を
互いに切り放さずに１列に並べた複数の半導体素子２
を、そのまま同様にしてポリイミドテープ４に接着す
る。熱圧着条件は４００℃、２０Ｋｇ／ｍｍ2×数秒程
度である。半導体素子２の短辺にはスクライバー等を用
いてあらかじめ分割領域８を形成しておく。Next, as shown in FIG. 3 (b), a plurality of semiconductor elements 2 arranged in a line without cutting the short sides on both sides apart from each other.
Is adhered to the polyimide tape 4 in the same manner. The thermocompression bonding conditions are 400 ° C. and 20 Kg / mm 2 × several seconds. A divided region 8 is formed in advance on the short side of the semiconductor element 2 by using a scriber or the like.
【００２０】次に図３（ｃ）のように、リード３の内部
端子と半導体素子の電極６をＡｕワイヤ５でワイヤボン
ドする。Next, as shown in FIG. 3C, the internal terminal of the lead 3 and the electrode 6 of the semiconductor element are wire-bonded with the Au wire 5.
【００２１】最後に図３（ｄ）のように封止樹脂１を用
いたトランスファーモールドにより、半導体素子２とリ
ード３の内部端子を封止する。この際、金型形状の凹凸
を工夫することにより、封止樹脂１の分割用の肉薄部７
は簡単に形成できる。本工程では半導体素子を一つずつ
パッケージする必要がなく、複数の半導体素子２をまと
めて一括にパッケージできるため、従来に比べてパッケ
ージの工程が簡略化できる。Finally, as shown in FIG. 3D, the semiconductor element 2 and the internal terminals of the leads 3 are sealed by transfer molding using the sealing resin 1. At this time, by devising the unevenness of the mold shape, the thin portion 7 for dividing the sealing resin 1 is formed.
Can be easily formed. In this step, it is not necessary to package the semiconductor elements one by one, and a plurality of semiconductor elements 2 can be collectively packaged, so that the packaging process can be simplified as compared with the related art.
【００２２】図４において、従来の半導体パッケージ
（同図（ａ））と本実施例の半導体パッケージ（同図
（ｂ））の回路基板に実装した場合の比較を示す。本実
施例による半導体パッケージは、封止樹脂１の厚さや実
装に必要な半導体パッケージ間の間隙等の無駄な空間が
省略でき、半導体素子２を間隙無しに直接並べて実装で
きるため、従来の半導体パッケージに比べ、はるかに実
装面積を省略できる。FIG. 4 shows a comparison between the conventional semiconductor package (FIG. 4A) and the semiconductor package of this embodiment (FIG. 4B) mounted on a circuit board. In the semiconductor package according to the present embodiment, wasteful spaces such as the thickness of the sealing resin 1 and the gaps between the semiconductor packages necessary for mounting can be omitted, and the semiconductor elements 2 can be mounted directly side by side without a gap. Compared with, the mounting area can be greatly reduced.
【００２３】また、従来の半導体パッケージを一つずつ
実装するのに比べ、本実施例の半導体パッケージでは多
くの半導体素子２をまとめて一括で実装できるため、実
装工程が少なくなる。Further, as compared with the conventional semiconductor package mounted one by one, in the semiconductor package of this embodiment, a large number of semiconductor elements 2 can be packaged together, so that the mounting process is reduced.
【００２４】また、本構成の半導体パッケージは、半導
体素子２の辺の上下に形成した半導体パッケージの分割
用の溝部７で分割することにより、半導体素子を自由に
個別の半導体パッケージに分割し、使用する電子機器に
応じて必要な数の半導体素子を有する半導体パッケージ
にできる。The semiconductor package of this structure is divided by the dividing grooves 7 of the semiconductor package formed above and below the sides of the semiconductor element 2 to freely divide the semiconductor element into individual semiconductor packages for use. The semiconductor package can have a required number of semiconductor elements according to the electronic device used.
【００２５】図５に本発明の半導体パッケージの分割例
を示す。半導体パッケージの分割は切削、機械的切断や
レーザー等の方法を用いてもよいが、より簡略にするに
は本実施例のように半導体素子の境界にあらかじめ分割
用の切削線を形成しておくのがよい。FIG. 5 shows an example of division of the semiconductor package of the present invention. The semiconductor package may be divided by a method such as cutting, mechanical cutting or laser, but for simplification, a cutting line for division is formed in advance at the boundary of the semiconductor element as in this embodiment. Is good.
【００２６】図６に本発明の第２の実施例の上面図を、
またその断面構造を図７に示す。第２の実施例では長辺
側の一辺、及び両側の短辺を互いに切り放さずに２列に
並べた複数の半導体素子２を用いた。この方法では更に
効率よく半導体素子２を実装することができる。リード
３は図７に示すように、他の半導体素子２とつながった
側の長辺側からは取り出すことができないため、もう一
方の長辺側にＺＩＰやＶパックと同じ要領で配置する。FIG. 6 is a top view of the second embodiment of the present invention.
The cross-sectional structure is shown in FIG. In the second embodiment, a plurality of semiconductor elements 2 in which one side on the long side and the short sides on both sides are arranged in two rows without being cut off from each other are used. With this method, the semiconductor element 2 can be mounted more efficiently. As shown in FIG. 7, since the lead 3 cannot be taken out from the long side connected to the other semiconductor element 2, it is arranged on the other long side in the same manner as the ZIP or V pack.
【００２７】[0027]
【発明の効果】以上のように本発明のＳＯＪ型の半導体
パッケージは、複数の半導体素子を最小面積でまとめて
パッケージ内に収納でき、また半導体パッケージの分割
用の肉薄部で半導体パッケージを分割することにより、
半導体素子を個別の半導体パッケージに分離することが
できる。これにより下記の効果がある。As described above, in the SOJ type semiconductor package of the present invention, a plurality of semiconductor elements can be put together in a package with a minimum area, and the semiconductor package is divided by a thin portion for dividing the semiconductor package. By
The semiconductor device can be separated into individual semiconductor packages. This has the following effects.
【００２８】（ａ）封止樹脂の厚さや実装に必要な半導
体パッケージ間の間隙等の無駄な空間が必要なく、半導
体素子を間隙無しに直接並べて実装できるため、従来の
半導体パッケージに比べて、はるかに実装面積を省略で
きる。(A) Since it is possible to directly mount semiconductor elements without gaps without needless space such as the thickness of the sealing resin and gaps between semiconductor packages necessary for mounting, as compared with conventional semiconductor packages, The mounting area can be greatly reduced.
【００２９】（ｂ）多くの半導体素子をまとめて一括で
実装でき、従来の半導体パッケージを一つずつ実装する
のに比べて、実装工程が少なくなる。(B) A large number of semiconductor elements can be collectively packaged, and the number of mounting steps is reduced as compared with the conventional semiconductor package mounting one by one.
【００３０】（ｃ）半導体素子を一つずつパッケージす
る必要がなく、複数の半導体素子をまとめて一括にパッ
ケージきるため、従来の構成に比べてパッケージの工程
も簡略化できる。(C) Since it is not necessary to package the semiconductor elements one by one, and a plurality of semiconductor elements can be packaged together in a batch, the packaging process can be simplified as compared with the conventional configuration.
【００３１】（ｄ）半導体素子の辺の上下に形成した半
導体パッケージの分割用の肉薄部で自由に個別の半導体
パッケージに分割することができるため、使用する電子
機器に応じて必要な数の半導体素子を有する半導体パッ
ケージにできる。(D) Since the thin portions for dividing the semiconductor package formed above and below the sides of the semiconductor element can be freely divided into individual semiconductor packages, a required number of semiconductors can be obtained according to the electronic equipment used. It can be a semiconductor package having an element.
【００３２】（ｅ）これらにより低コスト、高密度実装
が可能になる。(E) These enable low cost and high density mounting.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の半導体パッケージの第１の実施例の構
成図FIG. 1 is a configuration diagram of a first embodiment of a semiconductor package of the present invention.
【図２】同実施例パッケージの断面図FIG. 2 is a sectional view of the package of the embodiment.
【図３】同実施例パッケージの製造工程を示す断面図FIG. 3 is a sectional view showing a manufacturing process of the package of the embodiment.
【図４】同実施例パッケージと従来パッケージの比較図FIG. 4 is a comparison diagram of the same embodiment package and a conventional package.
【図５】同実施例パッケージの分割例を示す図FIG. 5 is a diagram showing an example of dividing the package of the embodiment.
【図６】本発明の第２の実施例を示す上面図FIG. 6 is a top view showing a second embodiment of the present invention.
【図７】同実施例パッケージの上面断面図FIG. 7 is a top sectional view of the package of the embodiment.
【図８】従来の半導体パッケージの構成図FIG. 8 is a configuration diagram of a conventional semiconductor package.
【図９】従来の半導体パッケージの内部構造を示す断面
図FIG. 9 is a sectional view showing the internal structure of a conventional semiconductor package.
【図１０】従来の半導体パッケージを、複数個、搭載し
た場合の実装状態図FIG. 10 is a mounting state diagram when a plurality of conventional semiconductor packages are mounted.
１ 封止樹脂 ２ 半導体素子 ３ リード ４ ポリイミドテープ ５ Ａｕワイヤ ６ 半導体素子の電極 ７ 分割用の肉薄部 ８ 半導体素子の分割領域 DESCRIPTION OF SYMBOLS 1 Sealing resin 2 Semiconductor element 3 Lead 4 Polyimide tape 5 Au wire 6 Electrode of semiconductor element 7 Thin part for division 8 Division area of semiconductor element
Claims (4)
続されたリード材と、前記半導体素子とリード材の一部
を被覆した成形樹脂からなり、前記リード材は、その先
端部が前記成形樹脂の外部まで導出された半導体パッケ
ージであって、前記半導体素子を複数個接続すると共
に、前記半導体素子が接続される接続部には、半導体素
子を分割可能であるように前記成形樹脂の薄肉部で形成
される分割領域が構成されたことを特徴とする半導体パ
ッケージ。1. A semiconductor element, a lead material connected to an electrode of the semiconductor element, and a molding resin that covers a part of the semiconductor element and the lead material. It is a semiconductor package led out to the outside of a resin, and a plurality of the semiconductor elements are connected, and a thin portion of the molding resin is formed in a connecting portion to which the semiconductor elements are connected so that the semiconductor element can be divided. A semiconductor package, characterized in that a divided region formed by the above is formed.
２列に並んで配置されたことを特徴とする請求項１に記
載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein the semiconductor elements sharing the divided region are arranged in two rows in one direction.
出され、前記半導体素子と前記リード材の一部が絶縁テ
ープを介して接着されていることを特徴とする請求項１
または２に記載の半導体パッケージ。3. A part of the lead material is led out on the main surface of the semiconductor element, and the part of the lead material is adhered to the semiconductor element via an insulating tape.
Alternatively, the semiconductor package described in 2.
ケージを用い、分割領域において分割された半導体パッ
ケージを用いて実装を行うことを特徴とする半導体パッ
ケージの実装方法。4. A method for mounting a semiconductor package, wherein the semiconductor package according to claim 1 is used and mounting is performed using a semiconductor package divided in a division region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5028730A JPH06244313A (en) | 1993-02-18 | 1993-02-18 | Semiconductor package and mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5028730A JPH06244313A (en) | 1993-02-18 | 1993-02-18 | Semiconductor package and mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06244313A true JPH06244313A (en) | 1994-09-02 |
Family
ID=12256556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5028730A Pending JPH06244313A (en) | 1993-02-18 | 1993-02-18 | Semiconductor package and mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06244313A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6180435B1 (en) | 1998-06-24 | 2001-01-30 | Nec Corporation | Semiconductor device with economical compact package and process for fabricating semiconductor device |
| US6200121B1 (en) | 1998-06-25 | 2001-03-13 | Nec Corporation | Process for concurrently molding semiconductor chips without void and wire weep and molding die used therein |
| JP2002289757A (en) * | 2001-03-27 | 2002-10-04 | New Japan Radio Co Ltd | Lead cutting method of electronic component |
-
1993
- 1993-02-18 JP JP5028730A patent/JPH06244313A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6180435B1 (en) | 1998-06-24 | 2001-01-30 | Nec Corporation | Semiconductor device with economical compact package and process for fabricating semiconductor device |
| US6200121B1 (en) | 1998-06-25 | 2001-03-13 | Nec Corporation | Process for concurrently molding semiconductor chips without void and wire weep and molding die used therein |
| US6315540B1 (en) * | 1998-06-25 | 2001-11-13 | Nec Corporation | Molding die for concurrently molding semiconductor chips without voids and wire weep |
| JP2002289757A (en) * | 2001-03-27 | 2002-10-04 | New Japan Radio Co Ltd | Lead cutting method of electronic component |
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