KR970002136B1 - Semiconductor package - Google Patents

Abstract

A semiconductor package is provided in which an electrical port is formed on the surface of a plastic package using an electrode bar to enable vertical stacking of packages, increasing the memory capacity of a memory device. When data or signal is applied to a semiconductor chip 1, the signal is transmitted to the semiconductor chip 1 through external and inner leads 5 and 6 and wire bonded gold wire 2. This signal is simultaneously sent to the electrode bar 8 through the external and inner leads 5 and 6. When a specific signal or data is outputted from the semiconductor chip 1, the specific signal is outputted through the wire bonded gold wire 2 and external and inner leads 5 and 6, and simultaneously sent to the electrode bar 8 through them. Accordingly, when plastic packages are stacked in multilayer structure, input/output of data is simultaneously carried out to/from the upper and lower packages through the electrode bar and external and inner leads, thereby facilitating extension in the memory device and increasing its memory capacity.

Description

Semiconductor package

1 is a cross-sectional view of a conventional SOJ type plastic package.

2 is a cross-sectional view of a SOJ type plastic package according to the present invention.

3 is a plan view of a plastic package according to the present invention.

4 is a state in which an electrorod bar according to the present invention is attached to the inner lead.

5 is a laminated state of the plastic package according to the present invention.

6 is a cross-sectional view of a plastic package of another embodiment according to the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor chip 2 gold wire

3: epoxy resin 4: leadframe paddle

5: External lead 6: Internal lead

7: Electrode bar 8: Electric terminal

9: insulation layer 10: polyimide film

11: solder bump

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor package. In particular, an electronic terminal is formed on a surface of a plastic package by using an electrode bar, so that the semiconductor package can be stacked up and down. It is about.

In general, a plastic package for a semiconductor memory device and a method of manufacturing the same may be classified into two types, first of which is an insert type and second of a surface mount type.

In the case of semiconductor memory devices, the most common type is an insert type (ZIP: Zigzag Inline Package) type, and the surface mount type is SOP, SOJ, TSOP type, etc. Among these, the SOJ type is most commonly used. In the case of TSOP, it is a kind of special package that is made with a thickness of 1mm for a memory card that is in the limelight these days.

Figure 1 shows a cross-sectional structure of a conventional SOJ type plastic package, looking at the manufacturing process as follows.

First, in the sawing process, the semiconductor chip is cut from the wafer into individual semiconductor chips, and the semiconductor chips separated in the die attach process are attached to the leadframe paddle as an adhesive.

After curing for a predetermined time at a certain temperature condition, and then connected to the bonding pads on the surface of the semiconductor chip and the inner lead 6 of the lead frame by a gold wire (2) and electrically connected to each other in the wire bonding process. The resin 3 is used to mold the semiconductor chip 1, and the molding process is to protect the semiconductor chip from thermal, mechanical and chemical shocks from the outside.

After the molding process, electroplating is performed to prevent the external lead 5 from contamination and to improve the contactability of the solder when mounting. In this case, the main component of the electroplating is Tin (Sn) / Lead (Pd), and the thickness thereof is It is about a few μm, and trim process cuts and removes unnecessary parts of the lead frame, and forming process is bent in various forms to fit the printed circuit board.

At this time, according to the shape of the outer lead (5) formed in the forming process can be divided into J-shaped J-lead, gull wing-shaped Gullwing-lead, butterfly-shaped Butt-lead, the formation of the butterfly-shaped Butt-lead The DIP, SIP, and ZIP types are inserted into the printed circuit board and soldered, whereas the SOJ, SOP, TSOP, and QFP types in the shape of J-lead or Gullwing-lead are surface mounted on the printed circuit board and soldered. Here, the surface mount type is a far more advanced form than the insert type.

Subsequently, after the forming process is completed, all manufacturing processes are completed by marking the surface of the plastic package to display the semiconductor device name and the manufacturing date.

Therefore, as shown in FIG. 1, in the conventional plastic package, the semiconductor device can be mounted in a single layer when designing and configuring a printed circuit board for forming a system since the direction in which the external terminal is formed is toward the bottom. As a result, in the case of semiconductor memory devices, in order to increase the storage capacity, the mounting efficiency decreases, which not only acts as a factor of cost increase, but also causes a problem of deterioration of product function due to lengthening of the bonding wire.

The present invention is to solve the above problems by installing an electrorod bar having a predetermined width and length in the inner lead, and protrudes the electrorod bar on the upper surface of the plastic package to form an electrical terminal to the lower side and the electrophoresis through the outer lead SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package in which a plurality of plastic packages can be stacked up and down by forming electrical terminals at the same time through a lower bar, so that the storage capacity of a semiconductor memory device can be increased.

The present invention provides a semiconductor package in which a semiconductor chip 1 is mounted on a lead frame paddle 4, and the semiconductor chip 1 and the inner lead 6 are molded with an epoxy resin 3. The electrode rod bar 7 having a predetermined width and length is installed to protrude on the upper surface of the package so as to have a plurality of electrical terminals 8 on the upper surface of the package.

Hereinafter, described in detail by the accompanying drawings as follows.

2 is a cross-sectional structural view of the SOJ-type plastic package according to the present invention, in which an end portion of the electrode rod 7 is used as an electrical terminal by attaching an electrode rod 7 on the inner lead 6 of the lead frame. In order to be exposed to the outside of the upper surface of the plastic package is configured.

That is, although the electric terminal of the semiconductor chip 1 has conventionally transmitted and received an electrical signal through the external lead 5 in one direction, the present invention provides the external lead 5 in two directions with respect to one electric terminal, that is, the lower side. Through the above, it is to pass through a separate electrorod bar (7).

In addition, Figure 3 shows a plan view of the plastic package according to the present invention, so that the protruding shape of the outer lead (5) and the electrical terminal shape of the electric rod bar 7 protruding on the package surface can be seen at the same time.

That is, on the upper surface of the semiconductor package, electrical terminals 8 formed on the surfaces of the plurality of electrorod bars 7 having the same width as the outer leads 5 and provided at predetermined intervals are arranged.

4 illustrates a state in which the electrode rod 7 according to the present invention is attached to the inner lead 6, and the electrode rod 7 is alternately installed with the insulating layer 9 interposed therebetween. Electrically shorted, the height of the insulating layer 9 is configured not to be higher than the electric rod bar 7, one side of the electric rod bar 7 is electrically connected to the inner lead 6, and another One side is an electrical terminal 8 which is exposed out of the package upper surface.

In addition, the insulating layer 9 located between the inner lead 6 is configured to fill the gap between the inner lead 6 for alignment of the electrode rod 7 and the inner lead 6, In order to electrically connect the rod 7 and the inner lead 6, a solder paste or a conductive epoxy resin, which is a conductive adhesive, is attached.

5 shows a state in which the plastic package according to the present invention is stacked, the outer lead 5 is connected to an electric terminal formed on the upper package of the lower end, and the electric terminal 8 is formed on the outer package of the upper package. The contact with the lead is a laminated structure repeated.

According to the present invention made as described above, when data or a signal is first applied to the semiconductor chip 1, the signal is transferred to the semiconductor chip 1 through the external and internal leads 5 and 6, and the wire bonded gold stone 2. The signal is simultaneously transmitted to the electroload bar 8 via the external and internal leads 5 and 6, and when the data or the specific signal is output from the semiconductor chip 1, the specific signal is It is output through the wire-bonded gold wire 2 and the inner and outer leads 6 and 5, while the signal thereof is simultaneously output through the outer and inner leads 5 and 6 to the electrorod bar 8.

Therefore, as shown in FIG. 5, when the plastic package is stacked in multiple layers, data input and output are simultaneously transmitted to the upper and lower packages through the electroload bar 8 and the external and internal leads 5 and 6, thereby being a memory device. Expansion is easy.

FIG. 6 illustrates another internal cross-sectional structure of the plastic package according to the present invention, and FIG. 6a shows an inner lead 6 formed to extend to a predetermined portion of the semiconductor chip 1, and the inner lead 6 and the semiconductor The polyimide film 10, which is an insulating layer, was inserted between the chips 1, and wire bonding was performed with the gold wire 2, and in FIG. 6b, the inner lead 6 was positioned to a predetermined position of the semiconductor chip 1. And forming solder bumps 11 on the bonding pads on the surface of the semiconductor chip 1 instead of wire bonding between the inner lead 6 and the semiconductor chip 1 to electrically form the inner lead 6. As an example of connection, the electrorod bar 7 is installed more firmly.

As described above, the plastic package structure according to the present invention has an outer rod formed by installing an electric rod bar having a predetermined width and length in the inner lead, and protruding the electric rod bar on the upper surface of the plastic package to form an electrical terminal. Since the electrical terminal is formed at the same time through the lower side and the lower side through the electrorod bar, a plurality of plastic packages can be stacked up and down, thereby increasing the storage capacity of the semiconductor memory device.

Claims (9)

In a semiconductor package in which a semiconductor chip 1 is seated on a lead frame paddle 4, and the semiconductor chip 1 and the inner lead 6 are molded with an epoxy resin 3, a predetermined portion is placed on the inner lead 6. A semiconductor package comprising a plurality of electric terminals (8) on the upper surface of the package by protruding the electrode rod bar (7) having a width and length protruding on the upper surface of the package. 2. The upper surface of the electrorod bar 7 is exposed to the surface of the plastic package and used as an electrical terminal 8, and the lower surface of the electrorod bar 7 is attached to the inner lead 6. A semiconductor package, characterized in that. 2. The semiconductor package according to claim 1, wherein the electrode rods (7) are alternately provided with an insulating layer (9) interposed therebetween so as to be electrically insulated from neighboring electrode rods (7). The method of claim 1, wherein the inner lead 6 is formed so as to be positioned to a predetermined portion of the semiconductor chip 1, and the polyimide film 10 is inserted between the inner lead 6 and the semiconductor chip (1). A semiconductor package, characterized in that. The method of claim 1, wherein the inner lead 6 is formed to a predetermined portion of the semiconductor chip 1, and a solder bump 11 is formed between the inner lead 6 and the semiconductor chip 1. A semiconductor package characterized by electrically connecting the inner lead (6). 3. The semiconductor package according to claim 2, wherein a conductive adhesive is used when attaching the electrorod bar (7) to the inner lead (6). The method of claim 2, wherein two or more semiconductor devices are stacked to increase capacity by using the electrical terminals 8 exposed on the surface of the plastic package to electrically connect with the electrical terminals of another semiconductor package. Semiconductor package. 4. The semiconductor package according to claim 3, wherein the insulating layer (9) is formed lower than the height of the electrode rod (7) and is sandwiched between the inner leads (6). The semiconductor package according to claim 6, wherein the conductive adhesive is selectively used among solder paste and conductive epoxy resin.