KR0161117B1 - Semiconductor package device - Google Patents
Semiconductor package device Download PDFInfo
- Publication number
- KR0161117B1 KR0161117B1 KR1019950003133A KR19950003133A KR0161117B1 KR 0161117 B1 KR0161117 B1 KR 0161117B1 KR 1019950003133 A KR1019950003133 A KR 1019950003133A KR 19950003133 A KR19950003133 A KR 19950003133A KR 0161117 B1 KR0161117 B1 KR 0161117B1
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- chip
- inner lead
- package device
- semiconductor package
- bonding
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 반도체 패키지 디바이스에 관한 것으로, 하나의 패키지 장치안에 복수개의 반도체 칩을 내장하여 용량 증대를 꾀한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package device, in which a plurality of semiconductor chips are embedded in one package device to increase capacity.
그 구조는 상부에 서로 평행하며 대칭적인 구조를 가지는 소정 복수개의 본딩 패드로 구성된 본딩패드 어레이를 형성시킨 2개의 칩과; 칩의 본딩 패드와 전기적으로 연결된 인너리드와, 인너리드에 연장 형성되어 외부와 전기적 접속되는 아웃리드로 이루어진 리드 프레임과; 칩과, 인너리드를 연결시키기 위하여 상기 본딩 패드 어레이로부터 외부 방향으로 상기 칩에 각각 대칭적으로 형성시킨 접착부와; 칩과, 상기 인너리드를 커버하도록 컴파운드로 형성된 몰딩부를 포함하여 구성되어, 특히 메모리 소자 모듈에 있어 실장면적의 축소를 통하여 실장의 용이성과, 동일 면적의 기판상에 용량의 증대를 기한 것을 특징으로 한다.The structure comprises: two chips forming a bonding pad array composed of a plurality of bonding pads having parallel and symmetrical structures on top of each other; A lead frame including an inner lead electrically connected to a bonding pad of a chip, and an outer lead extending to the inner lead and electrically connected to the outside; Bonding portions formed symmetrically on the chips from the bonding pad array in an outward direction to connect chips with inner leads; It comprises a chip and a molding portion formed of a compound to cover the inner lead, characterized in that the ease of mounting and the increase in capacity on the substrate of the same area by reducing the mounting area, especially in the memory device module do.
Description
제1도는 종래의 반도체 패키지 디바이스의 구조를 설명하기 위하여 도시한 도면.1 is a diagram for explaining the structure of a conventional semiconductor package device.
제2도는 본 발명의 반도체 패키지 디바이스의 구조를 설명하기 위하여 도시한 도면.2 is a diagram for explaining the structure of a semiconductor package device of the present invention.
제3도는 종래와 본 발명의 반도체 패키지 디바이스가 인쇄회로기판상에 실장된 상태를 비교하기 위하여 도시한 도면.3 is a view showing a comparison between the conventional and the semiconductor package device of the present invention mounted on a printed circuit board.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,21 : 칩 12 : 패들11,21: Chip 12: Paddle
22 : 접착부 13,23-1 : 본딩패드22: bonding portion 13,23-1: bonding pad
23 : 본딩 패드 어레이 14,24 : 본딩 와이어23 bonding pad array 14,24 bonding wire
15,25 : 리드 프레임 15-1,25-1 : 인너리드15,25: lead frame 15-1,25-1: inner lead
15-2,25-2 : 아웃리드 16,26 : 몰딩부15-2,25-2: Out lead 16,26: molding part
31 : 인쇄회로기판 32 : 싱글 칩 패키지31: printed circuit board 32: single chip package
33 : 멀티 칩 패키지33: multi-chip package
본 발명은 반도체 패키지 디바이스에 관한 것으로, 특히 메모리 소자의 용량 증대에 적당하도록 한 반도체 패키지 디바이스에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package device, and more particularly to a semiconductor package device adapted to increase the capacity of a memory element.
제1도에서 보는 바와 같이, 종래의 반도체 소자의 패키지는 하나의 유니트 패키지에 하나의 칩(11)을 리드 프레임(15)의 패들(12)에 다이 본딩시키고, 칩에 형성시킨 본딩패드(13)와 리드 프레임(15)의 인너리드(15-1)를 본딩 와이어(14)로 전기적으로 연결시킨 후, 컴파운드로 몰딩부(16)를 형성시킨 싱글 칩 패키지 형태로 성형되었다.As shown in FIG. 1, a conventional package of semiconductor devices is die bonded by bonding one chip 11 to a paddle 12 of a lead frame 15 in one unit package and forming a bonding pad 13 on the chip. ) And the inner lead 15-1 of the lead frame 15 are electrically connected to the bonding wire 14, and then molded into a single chip package in which the molding part 16 is formed of a compound.
또한, 제3도의(a)와 같이, 이렇게 형성시킨 종래의 패키지 형태의 메모리 소자는 용량 증대를 위해 싱글 칩 패키지(32)를 일정한 패턴이 형성된 모듈 인쇄회로기판(31)위에 실장, 모듈(module)화시켜 제품화 시켰다.In addition, as shown in FIG. 3A, the conventional package type memory device is mounted and mounted on a module printed circuit board 31 having a single pattern on which a single chip package 32 is formed to increase capacity. ) To commercialize.
그러나, 종래의 싱글 칩 패키지는 그 구조상 PCB 등에의 패키지 실장시에 유니트 패키지 단위로 실장시킴으로써 패키지 실장 면적이 기판 면적에 대비하여 상당히 컸다.However, in the conventional single chip package, the package mounting area is considerably larger than the substrate area by mounting the unit package unit in the package mounting on the PCB or the like.
따라서, 모듈 기판을 설계함에 있어 패턴 형성 마진을 고려하기가 곤란하였다.Therefore, in designing the module substrate, it was difficult to consider the pattern formation margin.
특히, 다 비트(multi bit) 모듈 제작시에는 배선 설계상 상당한 어려움이 있어서, 모듈상에서의 용량 증대에 문제점을 가지고 있었다.In particular, when manufacturing a multi-bit module, there is a considerable difficulty in wiring design, which has a problem in increasing the capacity on the module.
그래서, 본 발명의 반도체 패키지 디바이스는 하나의 패키지에 다수개의 칩을 내장하는 방식을 채택하여 용량 증대의 문제를 개선시키고자 제안된 것이다.Therefore, the semiconductor package device of the present invention is proposed to improve the problem of capacity increase by adopting a method of embedding a plurality of chips in one package.
본 발명의 반도체 패키지 디바이스는 소정의 절연거리를 두고 수평하게 마주하여 형성시키며, 상부에 서로 평행하며 대칭적인 구조를 가지는 본딩패드 어레이를 각각 형성시킨 두개의 칩과, 전기적으로 칩의 본딩 패드와 결합되는 인너리드와 이에 연정되어 외부와 전기적으로 연결되는 아웃리드로 구성된 리드 프레임과, 리드 프레임의 인너리드에 각각의 칩을 다이본딩시키기 위하여 각 칩의 본딩 패드 어레이로부터 외부 방향으로 소정 넓이를 가지게 형성시킨 접착부와, 두 개의 칩과 리드프레임의 인너리드를 커버하도록 컴파운드로 형성시킨 몰딩부로 이루어진다.The semiconductor package device of the present invention is formed to face each other horizontally with a predetermined insulation distance, two chips each formed with a bonding pad array having a parallel and symmetrical structure on top, and electrically coupled with the bonding pad of the chip A lead frame including an inner lead and an outer lead connected to the outside and connected to the outside, and a predetermined width from the bonding pad array of each chip to the outside in order to die-bond each chip to the inner lead of the lead frame. And a molding part formed of a compound to cover the inner lead of the two chips and the lead frame.
이 때, 접착부를 형성시킨 절연필름은 폴리머 계열의 폴리 이미드등을 칩에 도포하여 형성시킨다.At this time, the insulating film formed with the adhesive portion is formed by applying a polymer-based polyimide or the like to the chip.
또한, 몰딩부를 형성시키는 컴파운드는 열경화성 폴리머 수지로 형성시킨다.In addition, the compound for forming the molding portion is formed of a thermosetting polymer resin.
이러한 반도체 패키지 디바이스는 패브리케이션이 끝난 웨이퍼를 소잉하여 얻은 칩의 상부에 소정 면적의 접착부를 양면접착성을 가지는 폴리이미드수지나 에폭시등으로 형성시킨다.Such a semiconductor package device forms an adhesive portion of a predetermined area on a chip obtained by sawing a finished wafer with polyimide resin or epoxy having double-sided adhesiveness.
이 때, 소정 면적이란 이후 공정에서 칩이 리드 프레임의 인너리드에 접착되어 와이어 본딩을 할 수 있을 정도의 넓이를 말한다.In this case, the predetermined area refers to an area that allows the chip to be bonded to the inner lead of the lead frame in the subsequent process to perform wire bonding.
이어서, 리드 온 칩(L.O.C) 방식으로 칩을 리드 프레임의 인너리드에 다이 본딩시킨다.Subsequently, the chip is die-bonded to the inner lead of the lead frame by a lead-on chip (L.O.C) method.
다음으로, 칩의 상부에 미리 형성시킨 본딩 패드와 리드 프레임의 인너리드를 전기적으로 결속시키는 와이어 본딩을 실시한다.Next, the wire bonding which electrically binds the bonding pad previously formed in the upper part of a chip, and the inner lead of a lead frame is performed.
다음으로, 두개의 칩과 인너리드를 커버할 수 있을 정도로 컴파운드로 몰딩한다.Next, mold the compound to cover the two chips and the inner lead.
이어서, 리드 프레임을 트리밍하고, 포밍한 후, 플레이팅하는 공정을 포함하여 형성시킨다.Subsequently, the lead frame is formed by trimming, forming, and then plating.
제2도는 본 발명의 반도체 패키지 디바이스의 구조를 설명하기위하여 도시한 도면이다.2 is a diagram for explaining the structure of a semiconductor package device of the present invention.
제2도와 같이, 소정 절연거리를 두고 서로 수평으로 마주보게 형성시키며, 상부에 서로 평행하며 대칭적인 구조를 가지는 본딩 패드 어레이(23)를 각각 형성시킨 두개의 칩(21)과, 칩 상부에 형성시킨 양면 접착성의 절연필름으로 형성시킨 접착부(22)와, 리드 온 칩 방식으로 칩에 형성시킨 접착부(22)에 접착되어 칩의 본딩 패드(23-1)와 전기적으로 결속시킨 인너리드(25-1)와 인너리드를 연장하여 형성시킨 아웃리드(25-2)로 이루어진 리드프레임(25)과, 칩(21)과 리드프레임의 인너리드(15-1)를 커버하기 위하여 컴파운드로 형성시킨 몰딩부(26)로 이루어진다.As shown in FIG. 2, two chips 21 are formed to face each other horizontally with a predetermined insulation distance, and each bonding pad array 23 having a parallel and symmetrical structure is formed thereon, and formed on the chip. Inner lead 25- adhered to the bonding portion 22 formed of the double-sided adhesive insulating film and the bonding portion 22 formed on the chip by a lead-on chip method, and electrically bonded to the bonding pad 23-1 of the chip. 1) and the lead frame 25 made of the outer lead 25-2 formed by extending the inner lead, and the molding formed by compound to cover the inner lead 15-1 of the chip 21 and the lead frame. It consists of a part 26.
이 때, 칩위의 본딩 패드는 칩의 내측 장변 쪽으로만 배열하여 형성시켜 전기적 특성측면에서 유리하도록 하기 위해서이다.At this time, the bonding pads on the chip are formed to be arranged only on the inner long side of the chip so as to be advantageous in terms of electrical characteristics.
또한, 본 발명의 반도체 패키지 디바이스의 또다른 실시예로 본딩 패드를 센터 패드 구조로 형성시켜 리드 온 칩 방식으로 리드 프레임에 다이 본딩 시킨 구조를 가질 수 도 있다.In addition, another embodiment of the semiconductor package device of the present invention may have a structure in which the bonding pad is formed in a center pad structure and die bonded to the lead frame in a lead-on-chip manner.
이럴 경우에는 위에 설명한 칩의 내측 장변에 본딩 패드를 형성시킨 구조에 비하여 접착부의 접착력은 더욱 요구하지만 인너리드의 길이가 짧아져 전기적 특성은 더욱 좋아진다.In this case, the adhesive force of the adhesive portion is more required than the structure in which the bonding pad is formed on the inner long side of the chip described above, but the inner lead length is shorter, resulting in better electrical characteristics.
한편, 도면을 통하여 걸윙 타입의 아웃리드를 가지는 2 방향 표면 실장용 반도체 디바이스 패키지(SOP : small outline pakage)만을 도시하여 설명하였으나, DIP(dual inline pakage)방식의 홀 삽입 실장용 패키지나, J 밴드 아웃리드의 2 방향 표면 실장용 패키지(SOJ : small outline j-band)에도 적용할 수 있다.On the other hand, although only the two-way surface mount semiconductor device package (SOP: small outline pakage) having a gull-wing type outlead is illustrated through the drawings, the package for the hole insertion package of the dual inline pakage (DIP) method or the J-band. It can also be applied to outlead two-way surface mount packages (SOJ: small outline j-band).
또한, 이러한 수평으로 마주하여 형성시킨 칩 구조를 다층으로 적재하여 형성시키는 스태커(stacker)칩 방식의 패키지에도 적용할 수 있다.Further, the present invention can also be applied to a stacker chip type package in which a chip structure formed by facing each other is stacked and formed in multiple layers.
제3도는 본 발명의 반도체 패키지 디바이스의 효과를 설명하기 위하여 도시한 도면으로써, 제3도의 (a)는 종래의 반도체 패키지 디바이스를 모듈로 구성하기 위하여 인쇄회로기판에 실장시킨 경우를 도시한 것이고, 제3도의 (b)내지 (c)는 본 발명의 반도체 패키지 디바이스를 모듈로 구성하기 위하여 인쇄회로기판에 실장시킨 경우를 도시한 도면이다.3 is a view for explaining the effect of the semiconductor package device of the present invention, Figure 3 (a) shows a case where a conventional semiconductor package device is mounted on a printed circuit board to configure a module, 3 (b) to 3 (c) show a case where the semiconductor package device of the present invention is mounted on a printed circuit board to form a module.
이러한 본 발명의 반도체 패키지 디바이스는 기존의 싱글 칩 패키지에 비해 본딩 패드의 위치를 한 변쪽으로 배치하고 인너리드를 가장 가깝게 구성하여 와이어 본딩함으로써 한 패키지에 다수의 칩이 실장되어 용량 증대가 용이하고 기존의 프로세스에 적합성을 가지고 있으며, 기존의 싱글 칩 패키지보다 구조적 측면에서 패키지 신뢰성이 향상되며 복수개의 칩을 동시에 작업함으로써 생산성이 증대되고, 인쇄회로기판에 실장시 기존 싱글 칩 패키지 보다 차지하는 면적이 작기 때문에 동일 면적에 있어 패키지가 차지하는 면적을 최소화시킴으로써 인쇄회로기판 설계 자유도 측면에서 훨씬 좋아진다.Compared to the conventional single chip package, the semiconductor package device of the present invention arranges the bonding pads to one side and configures the inner leads to be closest to each other, so that a plurality of chips are mounted in one package to easily increase capacity. It is suitable for the process, and the package reliability is improved in terms of structure than the conventional single chip package, productivity is increased by working with multiple chips at the same time, and when it is mounted on a printed circuit board, it occupies a smaller area than the existing single chip package. By minimizing the area occupied by the package in the same area, the design freedom of printed circuit boards is much better.
또한, 인쇄회로기판 실장 프로세스(pick and place)의 횟수가 적어져 생산성이 증대되며 기판위의 풀 프린트 배열을 단순화 시킬 수 있다.In addition, productivity is increased by reducing the number of pick and place processes of printed circuit boards, thereby simplifying the full print arrangement on the substrate.
또한, 인쇄회로기판상의 솔더링이 용이해지며 다 비트 모듈일수록 더욱 패키지 실장 면적이 작아지는 효과가 있다.In addition, the soldering on the printed circuit board is facilitated, and the more the multi-bit module, the smaller the package mounting area.
예를 들어, 4MD × 8BIT용 메모리 모듈의 경우 동일 PCB 면적에 있어서, 싱글 칩 패키지 8개와 모듈 칩 패키지 4개의 사이즈를 점유면적을 비교했을 때 약 15-20 %의 면적이 줄어들게 되며 제3도의 (c)와 같이, 에서 처럼 패키지 배치를 수평으로 했을 때는 PCB기판의 단변의 길이(A)를 30-40%줄일 수 있는 이점을 가지고 있다.For example, in the case of a 4MD × 8BIT memory module, an area of about 15-20% is reduced when the size of eight single chip packages and four module chip packages are compared in the same PCB area. As shown in c), when the package arrangement is horizontal, the length (A) of the short side of the PCB is reduced by 30-40%.
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KR1019950003133A KR0161117B1 (en) | 1995-02-18 | 1995-02-18 | Semiconductor package device |
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KR1019950003133A KR0161117B1 (en) | 1995-02-18 | 1995-02-18 | Semiconductor package device |
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