JPH0430561A - Semiconductor integrated circuit device and packaging structure therefor - Google Patents
Semiconductor integrated circuit device and packaging structure thereforInfo
- Publication number
- JPH0430561A JPH0430561A JP13804790A JP13804790A JPH0430561A JP H0430561 A JPH0430561 A JP H0430561A JP 13804790 A JP13804790 A JP 13804790A JP 13804790 A JP13804790 A JP 13804790A JP H0430561 A JPH0430561 A JP H0430561A
- Authority
- JP
- Japan
- Prior art keywords
- package
- lsi
- package body
- lead pin
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004806 packaging method and process Methods 0.000 title abstract description 6
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000010030 laminating Methods 0.000 abstract 2
- 238000005476 soldering Methods 0.000 abstract 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 241000587161 Gomphocarpus Species 0.000 description 1
- 241000699670 Mus sp. Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置に関し、特にＬＳＩパッ
ケージの高密度実装に適用して有効な技術に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to high-density packaging of LSI packages.
ＬＳＩパッケージを基板に高密度実装する方式の一つと
して、複数個のＬＳＩパッケージを基板に垂直な方向に
積層する多段実装方式が提案されている。従来、Ｄ Ｉ
Ｐ（Ｄｕａｌ Ｉｎ−１ｉｎｅ Ｐａｃｋａｇｅ）、
Ｓ ＯＪ （Ｓｍａｌｌ ［Ｉｕｔｌｉｎｅ Ｐａｃｋ
ａｇｅ＞ 、Ｔ Ａ Ｂ（Ｔａｐｅ＾ｕｔｏｍａｔｅｄ
Ｂｏｎｄｉｎｇ）などを用いた種々ノ多段実装構造が
提案されているが、薄形化に有利なＴＡＢを用いた多段
実装構造が特に注目されている。例えば日経ＢＰ社、１
９８９年１２月１日発行の「日経マイクロデバイス」Ｐ
４８には、ＴＡＢを用いた多段実装構造の具体例として
、ＳＲＡＭチップを搭載したＴＡＢを４個積層してメモ
リー・カード用モジニールを構成したものが記載されて
いる。As one method for high-density mounting of LSI packages on a board, a multi-stage mounting method has been proposed in which a plurality of LSI packages are stacked in a direction perpendicular to the board. Conventionally, DI
P (Dual In-1ine Package),
S OJ (Small [Iutline Pack
age> , T A B (Tape＼automated
Although various multi-stage mounting structures using TAB bonding and the like have been proposed, the multi-stage mounting structure using TAB, which is advantageous for thinning, is attracting particular attention. For example, Nikkei BP, 1
"Nikkei Microdevice" P published on December 1, 989
No. 48 describes, as a specific example of a multi-stage mounting structure using TABs, a module for a memory card is constructed by stacking four TABs each carrying an SRAM chip.
しかし、本発明者の検討によれば、ＴＡＢを用いた多段
実装構造には下記のような問題がある。However, according to the inventor's study, the multi-stage mounting structure using TAB has the following problems.
すなわち、ＴＡＢは約３５μ工程度の極ｔて薄いＣｕ箔
でリードを形成しているため、ＴＡＢを積層する工程で
リードが変形し易いなど、組立て工程での取り扱いに細
心の注意を必要とする煩わしさがある。また、ＴＡＢテ
ープからアウターリードを打ち抜く工程が必要となるな
ど、生産性の点においても問題がある。In other words, since the leads of TAB are made of extremely thin Cu foil with a process thickness of about 35 μm, the leads are easily deformed during the TAB stacking process, so great care must be taken when handling them during the assembly process. It's annoying. Further, there are also problems in terms of productivity, such as the need for a step of punching out the outer leads from the TAB tape.
本発明は上記した問題点に着目してなされたものであり
、その目的はＬＳＩパッケージの高密度実装を容易に実
現することのできる技術を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technology that can easily realize high-density packaging of LSI packages.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本願の一発明は、半導体チップを封止したパッケージ本
体の周縁部に沿ってその上下面を貫通する貫通孔を設け
、この貫通孔内にその下端がノ＜−１ケ一ジ本体の下面
から下方に突出し、その上端が貫通孔の上端よりも下方
に位置するようにリードピンを挿入したＬＳＩパッケー
ジ構造である。One invention of the present application is to provide a through hole that penetrates the upper and lower surfaces of a package body in which a semiconductor chip is sealed along the periphery thereof, and that the lower end of the package body is inserted into the through hole from the lower surface of the package body by 1. This is an LSI package structure in which a lead pin is inserted such that it protrudes downward and its upper end is located below the upper end of the through hole.
上記した手段によれば、第一のパフケージ本体上に第二
のパッケージ本体を積層し、第二のパッケージ本体の下
面から下方に突出するリードピンを第一のパッケージ本
体の上面の貫通孔内に挿入することにより、多段実装構
造を容易に実現することができる。According to the above-described means, the second package body is stacked on the first puff cage body, and the lead pins protruding downward from the bottom surface of the second package body are inserted into the through holes on the top surface of the first package body. By doing so, a multi-stage mounting structure can be easily realized.
第１図は本実施例によるＬＳＩパッケージの断面図、第
２図はこのＬＳＩパッケージの斜視図である。FIG. 1 is a sectional view of an LSI package according to this embodiment, and FIG. 2 is a perspective view of this LSI package.
ＬＳＩパッケージ１のパッケージ本体２は、例えばエポ
キシ樹脂、ＢＴレジン（ビスマレイミド−トリアジン樹
脂）、ポリイミド樹脂などの合成樹脂にガラス繊維を含
浸したものからなる。パッケージ本体２の寸法は、縦Ｘ
横が約２０！ｌ１ｌＯＸ２０鼠程度、厚さが約１〜１．
５ＩＩＩＩ１１程度である。パッケージ本体２の上面中
央部には、キャビティ３が形成されてふり、キャビティ
３の内部にはメモリＬＳＩなどを形成した半導体チップ
４が収容されている。半導体チップ４は、エポキシ系樹
脂からなる接着層５を介してキャビティ３の底面に接合
されている。半導体チップ４は、Ａｕ、ＣｕまたはＡＩ
ｌからなるボンディングワイヤ６を介してパッケージ本
体２の配線層７と電気的に接続されている。半導体チッ
プ４は、キャピテイ３の内部に充填されたエポキシ系の
ポツティング樹脂８によって封止されている。The package body 2 of the LSI package 1 is made of a synthetic resin such as epoxy resin, BT resin (bismaleimide-triazine resin), or polyimide resin impregnated with glass fiber. The dimensions of the package body 2 are length x
The width is about 20! About l1lOX20 mice, thickness about 1~1.
It is about 5III11. A cavity 3 is formed in the center of the upper surface of the package body 2, and a semiconductor chip 4 formed with a memory LSI or the like is housed inside the cavity 3. The semiconductor chip 4 is bonded to the bottom surface of the cavity 3 via an adhesive layer 5 made of epoxy resin. The semiconductor chip 4 is made of Au, Cu or AI.
It is electrically connected to the wiring layer 7 of the package body 2 via a bonding wire 6 made of 1. The semiconductor chip 4 is sealed with an epoxy potting resin 8 filled inside the cavity 3 .
上記パッケージ本体２の周縁部には、パッケージ本体２
の上面から下面に貫通する多数の貫通孔９が所定の間隔
をおいて形成されている。貫通孔９の内径は、約０．５
ｕ程度であるが、その上端部はそれよりも幾分大径と
なっている。貫通孔９の内壁には、前記配線層７と電気
的に接続されたＣＵなどのメツキ層１０が形成されてい
る。At the periphery of the package body 2, there is a
A large number of through holes 9 penetrating from the upper surface to the lower surface are formed at predetermined intervals. The inner diameter of the through hole 9 is approximately 0.5
The diameter of the upper end is somewhat larger than that. A plating layer 10 such as CU electrically connected to the wiring layer 7 is formed on the inner wall of the through hole 9 .
上記多数の貫通孔９のそれぞれには、ＬＳＩノｅッケー
ジ１の外部端子を構成するリードピン１１が挿入されて
いる。リードピン１１は、その上端が貫通孔９の上端よ
りも下方に位置するように挿入されている。また、リー
ドピン１１は、その下端がパッケージ本体２の下面から
下方に突出するように挿入されている。リードピン１１
は、４２アロイ、コバールなどのＦｅ系合金からなり、
その径は約０．５ ｍｍ程度である。本実施例のリード
ピン１１は、その上端部の径が他の部分よりも太いネイ
ルヘッド状をなしている。これは、パッケージ本体２の
上方から貫通孔９内にリードピン１１を打ち込んだとき
、リードピン１１のパッケージ本体２下面から突出する
部分の長さを揃えるためである。Lead pins 11 constituting external terminals of the LSI electronic package 1 are inserted into each of the large number of through holes 9 . Lead pin 11 is inserted such that its upper end is located below the upper end of through hole 9 . Further, the lead pin 11 is inserted so that its lower end protrudes downward from the lower surface of the package body 2. Lead pin 11
is made of Fe-based alloys such as 42 alloy and Kovar,
Its diameter is approximately 0.5 mm. The lead pin 11 of this embodiment has a nail head shape in which the diameter of the upper end portion is larger than that of the other portion. This is to make the lengths of the portions of the lead pins 11 protruding from the lower surface of the package body 2 equal when the lead pins 11 are driven into the through holes 9 from above the package body 2.
第３図は、上記の構成からなる本実施例のＬＳＩパッケ
ージ１を基板１２に多段実装してモジュールを構成した
例を示している。ＬＳＩパッケージ１を基板１２に多段
実装するには、例えば基板１２のマウントパッド１３上
に半田ペーストを被着した後、リードピン１１とマウン
トパッド１３とが重なるようにＬＳＩパッケージ１を基
板１２上に位置決めする。次に、上記ＬＳＩパッケージ
１の上に第二のＬＳＩパッケージ１を積層し、そのパッ
ケージ本体２の下面から下方に突出するり−ドビン１１
を第一のＬＳＩパッケージ１の貫通孔９内に挿入し、そ
の下端を第一のＬＳＩパッケージ１のリードピン１１の
上端と接触させる。このとき、あらかじめ第二のＬＳＩ
パッケージ１のリードピン１１の下端、または第一のＬ
ＳＩパッケージ１のリードピン１１の上端に半田ペース
トを被着しておく。このようにして、所望する数のＬＳ
Ｉパッケージ１を順次積層した後、基板１２をリフロー
炉内に搬送し、半田ペーストを加熱、溶融することによ
ってリードピン１１とマウントパッド１３、および上下
に重なるＬＳＩパッケージ１のそれぞれのリードピン１
１同士を半田で固定する。FIG. 3 shows an example in which the LSI package 1 of this embodiment having the above-mentioned configuration is mounted on a substrate 12 in multiple stages to form a module. To mount the LSI package 1 on the board 12 in multiple stages, for example, after applying solder paste on the mount pad 13 of the board 12, the LSI package 1 is positioned on the board 12 so that the lead pins 11 and the mount pad 13 overlap. do. Next, a second LSI package 1 is stacked on top of the LSI package 1, and a dowel 11 protrudes downward from the bottom surface of the package body 2.
is inserted into the through hole 9 of the first LSI package 1, and its lower end is brought into contact with the upper end of the lead pin 11 of the first LSI package 1. At this time, the second LSI
The lower end of the lead pin 11 of the package 1 or the first L
Solder paste is applied to the upper ends of the lead pins 11 of the SI package 1. In this way, the desired number of LS
After sequentially stacking the I packages 1, the substrate 12 is transferred to a reflow oven, and the solder paste is heated and melted to form the lead pins 11, the mount pads 13, and the lead pins 1 of the LSI packages 1 that overlap one above the other.
Fix them together with solder.
以上のような構成からなる本実施例によれば、下記のよ
うな作用、効果を得ることができる。According to this embodiment having the above configuration, the following actions and effects can be obtained.
（１）０貫通孔９内に挿入したリードピン１１の一部を
パッケージ本体２から突出させるようにしたので、搬送
時や組立て時に変形し難いリードピン１１が得られる。(1) Since a part of the lead pin 11 inserted into the through hole 9 is made to protrude from the package body 2, the lead pin 11 is obtained which is not easily deformed during transportation or assembly.
また、パッケージ本体２から突出する部分の長さを揃え
易いため、平坦度の高いリードピン１１が得られる。こ
れにより、ＬＳＩパッケージ１を容易に基板１２に実装
することができる。In addition, since the lengths of the portions protruding from the package body 2 can be easily aligned, lead pins 11 with high flatness can be obtained. Thereby, the LSI package 1 can be easily mounted on the board 12.
（２）１貫通孔９に挿入されたリードピン１１の上端を
貫通孔９の上端よりも下方に配置し、１つのＬＳＩパッ
ケージ１のリードピン１１をもう１つのＬＳＩパッケー
ジ１の貫通孔９内に挿入できるようにしたので、多数の
ＬＳＩパッケージ１を簡単に積層することができ、かつ
多数のＬＳＩパッケージ１を積層した際の全体の高さを
低くすることができる。(2) The upper end of the lead pin 11 inserted into the through hole 9 is arranged below the upper end of the through hole 9, and the lead pin 11 of one LSI package 1 is inserted into the through hole 9 of the other LSI package 1. As a result, a large number of LSI packages 1 can be easily stacked, and the overall height when a large number of LSI packages 1 are stacked can be reduced.
（３）、リードピン１１をパッケージ本体２の下面から
突出させるようにしたので、ＬＳＩパッケージ１を多段
実装した際に、基板１２の主面とパッケージ本体２の下
面との間、および上段のＬＳＩパッケージ１と下段のＬ
ＳＩパッケージ１との間に適度の隙間が形成される。こ
れにより、ＬＳＩパッケージｌを基板１２に実装した後
の洗浄作業を容易に行うことができる。また、ＬＳＩパ
ッケージ１の放熱性も向上する。(3) Since the lead pins 11 are made to protrude from the bottom surface of the package body 2, when the LSI packages 1 are mounted in multiple stages, the lead pins 11 are arranged between the main surface of the substrate 12 and the bottom surface of the package body 2, and between the LSI packages in the upper stage. 1 and lower L
A suitable gap is formed between the SI package 1 and the SI package 1. Thereby, cleaning work after mounting the LSI package l on the substrate 12 can be easily performed. Moreover, the heat dissipation of the LSI package 1 is also improved.
（４）、上記〔１〕〜（３）により、ＬＳＩパッケージ
１の高密度実装を容易に実現することができる。(4) With the above [1] to (3), high-density packaging of the LSI package 1 can be easily realized.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
例えば第４図に示すように、パッケージ本体２の下面か
ら突出するリードピン１１の側面をパッケージ本体２の
一部で被覆してもよい。このようにすると、搬送時や組
立て時におけるリードピン１１の変形を確実に防止する
ことができる。For example, as shown in FIG. 4, the side surface of the lead pin 11 protruding from the lower surface of the package body 2 may be covered with a part of the package body 2. In this way, deformation of the lead pin 11 during transportation and assembly can be reliably prevented.
また第５図に示すように、パッケージ本体２の下面から
突出するリードピン１１の先端にテーパーを設けてもよ
い。このようにすると、１つのＬＳＩパッケージのリー
ドピンを他のＬＳＩパッケージの貫通孔内に挿入する作
業が一層容易になる。Further, as shown in FIG. 5, the tip of the lead pin 11 protruding from the lower surface of the package body 2 may be tapered. This makes it easier to insert the lead pins of one LSI package into the through holes of another LSI package.
また第６図に示すように、貫通孔９に挿入されたリード
ピン１１の上端に凹溝１４を設け、この凹溝１４内に他
のＬＳＩパッケージのリードピンを挿入するようにして
もよい。このようにすると、１つのＬＳＩパッケージの
リードピンと他のＬＳＩパッケージのリードピンとの接
続信頼性が向上する。Further, as shown in FIG. 6, a groove 14 may be provided at the upper end of the lead pin 11 inserted into the through hole 9, and a lead pin of another LSI package may be inserted into the groove 14. This improves the connection reliability between the lead pins of one LSI package and the lead pins of other LSI packages.
前記実施例では、パッケージ本体を合成樹脂で構成した
例について説明したが、これに限定されるものではなく
、セラミックで構成することもできる。またこの場合に
は、パッケージ本体のキャビティ内に収容された半導体
チップをセラミックキャップで気密封止してもよい。In the above-mentioned embodiment, an example was explained in which the package body was made of synthetic resin, but the package body is not limited to this, and may be made of ceramic. Further, in this case, the semiconductor chip housed in the cavity of the package body may be hermetically sealed with a ceramic cap.
前記実施例では、半導体チップとパッケージ本体の配線
層との電気的接続をボンディングワイヤを用いて行った
例について説明したが、これに限定されるものではなく
、半田やＡｕのバンプ（突起電極）を介して半導体チッ
プとパッケージ本体の配線層との電気的接続を行っても
よい。In the above embodiment, an example was described in which the semiconductor chip and the wiring layer of the package body were electrically connected using a bonding wire, but the present invention is not limited to this, and solder or Au bumps (protruding electrodes) may be used. The semiconductor chip and the wiring layer of the package body may be electrically connected through the wiring layer.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
半導体チップを封止したパッケージ本体の周縁部に沿っ
て前記パッケージ本体の上下面に貫通する貫通孔を設け
、前記貫通孔内にその下端が前記パッケージ本体の下面
から下方に突出し、その上端が前記貫通孔の上端よりも
下方に位置するようにリードピンを挿入した本発明の半
導体集積回路装置によれば、Ｌ、Ｓ Ｉパッケージの多
段実装を容易に実現することができるので、半導体集積
回路装置の実装密度を向上させることができる。A through hole is provided in the upper and lower surfaces of the package body along the peripheral edge of the package body in which a semiconductor chip is sealed, the lower end of which protrudes downward from the lower surface of the package body within the through hole, and the upper end of the through hole extends downward from the lower surface of the package body. According to the semiconductor integrated circuit device of the present invention in which the lead pin is inserted so as to be positioned below the upper end of the through hole, multi-stage mounting of L and SI packages can be easily realized. Packaging density can be improved.
第１図は、本発明の一実施例である半導体集積回路装置
を示す第２図のＩ−Ｉ線における断面図、１２図は、こ
の半導体集積回路装置の斜視図、第３ｉ！Ｉは、この半
導体集積回路装置の実装構造を示す断面図、
第４図乃至第６図は、本発明の他の実施例である半導体
集積回路装置をそれぞれ示す要部断面図である。
１・・・ＬＳＩパッケージ、２・・・パッケージ本体、
３・・・キャビティ、４・・・半導体チップ、５・・・
接着層、６・・・ボンディングワイヤ、７・・・配線層
、８・・・ポツティング樹脂、９・・・貫通孔、１ｏ・
・・メツキ層、１１・・リードピン、１２・・・基板、
１３・・・マウントパッド、１４・・・凹溝。
代理人 弁理士 筒 井 大 和FIG. 1 is a sectional view taken along the line II in FIG. 2 showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 12 is a perspective view of this semiconductor integrated circuit device, and FIG. I is a sectional view showing the mounting structure of this semiconductor integrated circuit device, and FIGS. 4 to 6 are sectional views of essential parts of semiconductor integrated circuit devices according to other embodiments of the present invention. 1...LSI package, 2...package body,
3... Cavity, 4... Semiconductor chip, 5...
Adhesive layer, 6... Bonding wire, 7... Wiring layer, 8... Potting resin, 9... Through hole, 1o.
... Plating layer, 11... Lead pin, 12... Board,
13...Mount pad, 14...Concave groove. Agent Patent Attorney Daiwa Tsutsui
Claims (1)
沿って前記パッケージ本体の上下面を貫通する貫通孔を
設け、前記貫通孔内にその下端が前記パッケージ本体の
下面から下方に突出し、その上端が前記貫通孔の上端よ
りも下方に位置するようにリードピンを挿入したことを
特徴とする半導体集積回路装置。 ２、第一の半導体集積回路装置のパッケージ本体上に第
二の半導体集積回路装置のパッケージ本体を積層し、前
記第二のパッケージ本体の下面から下方に突出するリー
ドピンを前記第一のパッケージ本体の上面の貫通孔内に
挿入したことを特徴とする請求項１記載の半導体集積回
路装置の実装構造。[Claims] 1. A through hole is provided along the peripheral edge of the package body in which a semiconductor chip is sealed, passing through the upper and lower surfaces of the package body, and the lower end of the through hole extends from the lower surface of the package body. A semiconductor integrated circuit device, characterized in that a lead pin is inserted such that it projects downward and its upper end is located below the upper end of the through hole. 2. Stack the package body of a second semiconductor integrated circuit device on the package body of the first semiconductor integrated circuit device, and connect the lead pins protruding downward from the bottom surface of the second package body to the first package body. 2. The mounting structure for a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is inserted into a through hole in the upper surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13804790A JPH0430561A (en) | 1990-05-28 | 1990-05-28 | Semiconductor integrated circuit device and packaging structure therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13804790A JPH0430561A (en) | 1990-05-28 | 1990-05-28 | Semiconductor integrated circuit device and packaging structure therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430561A true JPH0430561A (en) | 1992-02-03 |
Family
ID=15212761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13804790A Pending JPH0430561A (en) | 1990-05-28 | 1990-05-28 | Semiconductor integrated circuit device and packaging structure therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430561A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06268101A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate |
| US5701233A (en) * | 1995-01-23 | 1997-12-23 | Irvine Sensors Corporation | Stackable modules and multimodular assemblies |
| KR19990051841A (en) * | 1997-12-20 | 1999-07-05 | 김영환 | Chip scale package and its manufacturing method |
| KR100280398B1 (en) * | 1997-09-12 | 2001-02-01 | 김영환 | Manufacturing method of stacked semiconductor package module |
| KR100422608B1 (en) * | 1997-05-10 | 2004-06-04 | 삼성전자주식회사 | Stack chip package |
| US6894378B2 (en) | 2001-03-02 | 2005-05-17 | Infineon Technologies Ag | Electronic component with stacked semiconductor chips |
| DE102006037691A1 (en) * | 2006-08-11 | 2008-02-14 | Robert Bosch Gmbh | Molded housing in press-fit technology |
| DE19720275B4 (en) * | 1996-05-17 | 2008-06-26 | LG Semicon Co., Ltd., Cheongju | Substrate for a semiconductor device, manufacturing method for the same and a stackable semiconductor device using the substrate |
| KR100963618B1 (en) * | 2007-11-30 | 2010-06-15 | 주식회사 하이닉스반도체 | Semiconductor package and method of manufacturing the semiconductor package |
| US20100171195A1 (en) * | 2007-07-04 | 2010-07-08 | Shin-Etsu Handotai Co., Ltd | Thin film silicon wafer and method for manufacturing the same |
| CN102637925A (en) * | 2011-02-14 | 2012-08-15 | 株式会社村田制作所 | Band-elimination filter |
| JP2014165341A (en) * | 2013-02-25 | 2014-09-08 | Seiko Instruments Inc | Electronic device |
-
1990
- 1990-05-28 JP JP13804790A patent/JPH0430561A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06268101A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate |
| US5701233A (en) * | 1995-01-23 | 1997-12-23 | Irvine Sensors Corporation | Stackable modules and multimodular assemblies |
| DE19720275B4 (en) * | 1996-05-17 | 2008-06-26 | LG Semicon Co., Ltd., Cheongju | Substrate for a semiconductor device, manufacturing method for the same and a stackable semiconductor device using the substrate |
| KR100422608B1 (en) * | 1997-05-10 | 2004-06-04 | 삼성전자주식회사 | Stack chip package |
| KR100280398B1 (en) * | 1997-09-12 | 2001-02-01 | 김영환 | Manufacturing method of stacked semiconductor package module |
| DE19802347B4 (en) * | 1997-09-12 | 2005-10-06 | LG Semicon Co., Ltd., Cheongju | A stackable semiconductor substrate and stackable semiconductor device, and manufacturing methods thereof, and a semiconductor stackable module module manufacturing method |
| KR19990051841A (en) * | 1997-12-20 | 1999-07-05 | 김영환 | Chip scale package and its manufacturing method |
| US6894378B2 (en) | 2001-03-02 | 2005-05-17 | Infineon Technologies Ag | Electronic component with stacked semiconductor chips |
| DE102006037691A1 (en) * | 2006-08-11 | 2008-02-14 | Robert Bosch Gmbh | Molded housing in press-fit technology |
| US8174834B2 (en) | 2006-08-11 | 2012-05-08 | Robert Bosch Gmbh | Molded housing used in force fit method |
| US20100171195A1 (en) * | 2007-07-04 | 2010-07-08 | Shin-Etsu Handotai Co., Ltd | Thin film silicon wafer and method for manufacturing the same |
| US8728870B2 (en) * | 2007-07-04 | 2014-05-20 | Shin-Etsu Handotai Co., Ltd. | Thin film silicon wafer and method for manufacturing the same |
| KR101436313B1 (en) * | 2007-07-04 | 2014-09-01 | 신에쯔 한도타이 가부시키가이샤 | Fabricating method of multi-layer film silicon wafer |
| KR100963618B1 (en) * | 2007-11-30 | 2010-06-15 | 주식회사 하이닉스반도체 | Semiconductor package and method of manufacturing the semiconductor package |
| CN102637925A (en) * | 2011-02-14 | 2012-08-15 | 株式会社村田制作所 | Band-elimination filter |
| JP2014165341A (en) * | 2013-02-25 | 2014-09-08 | Seiko Instruments Inc | Electronic device |
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