JPS59222947A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59222947A JPS59222947A JP58098351A JP9835183A JPS59222947A JP S59222947 A JPS59222947 A JP S59222947A JP 58098351 A JP58098351 A JP 58098351A JP 9835183 A JP9835183 A JP 9835183A JP S59222947 A JPS59222947 A JP S59222947A
- Authority
- JP
- Japan
- Prior art keywords
- electrode terminal
- frame
- semiconductor element
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高密度実装に適した半導装置の構造とその製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device structure suitable for high-density packaging and a manufacturing method thereof.
従来例の構成とその問題点
近年、機器の小型化・薄型化に伴い高密度実装技術が強
く要望されるようになって来た。そのために半導体素子
の接続にもワイヤレスボンディング技術が広く使用され
るようになって来た。以下第１図にフリップチップを第
２図にはフィルムキャリヤ（以下ＴＡＢと呼ぶ）の例を
示す。Conventional configurations and their problems In recent years, as devices have become smaller and thinner, there has been a strong demand for high-density packaging technology. For this reason, wireless bonding technology has come to be widely used for connecting semiconductor elements. Hereinafter, FIG. 1 shows an example of a flip chip, and FIG. 2 shows an example of a film carrier (hereinafter referred to as TAB).
第１図において、１は半導体素子、２，２′は半田バン
ブ、３は基板、４は導体、５．５’は半田バンプが接合
される領域である。第１図の例では半導体素子上の電極
の上に半田で突起電極が形成されるため、基板への接続
及び多数個実装する際極めて高密度化が実現できる。In FIG. 1, 1 is a semiconductor element, 2 and 2' are solder bumps, 3 is a substrate, 4 is a conductor, and 5.5' is a region to which the solder bumps are bonded. In the example shown in FIG. 1, since the protruding electrodes are formed with solder on the electrodes on the semiconductor element, extremely high density can be achieved when connecting to the substrate and mounting a large number of semiconductor elements.
しかしながら、上記の例では電極は一面にしかついてい
ない上、フェイスダウンで接合する際に位置合せが困難
である。However, in the above example, the electrode is attached only to one side, and alignment is difficult when joining face-down.
丑だ、他の従来例としてＴＡＢの断面スケッチ図を第２
図に示しだ。第２図において、６は半導体素子、７は半
導体素子上に形成されたＡｕ突起電極、８はＳｎメッキ
Ｃｕリード、９はポリイミドフィルム、１０，１０′は
外部回路と接続するだめの領域である。この場合、半導
体素子６上に形成されたＡｕ電極７とＣｕリード上のＳ
ｎメッキ８で合金接続されるため、その信頼性は極めて
高いとされている。さらに第２図の半導体装置を基板に
搭載した例を第３図に示した。第３図におい、第２図と
同一箇所には同一番号を付した。１１は基板、１２は導
体配線、１３は外部回路との接続部分、１４は半導体素
子を接着固定している接着剤又は半田である。このよう
にリード８は一度成形され（フォーミングと呼ぶ）、領
域１３で導体配線１２に接続される。必要な場合、半導
体素子６は基板１１に接着剤１４を用いて固定される○
しかしながら上記の例では、基板１１に搭載するために
はリード８をフォーリングしなければならず、ハンドリ
ングが極めて困雅である。As another conventional example, here is a cross-sectional sketch diagram of TAB.
It is shown in the figure. In FIG. 2, 6 is a semiconductor element, 7 is an Au protruding electrode formed on the semiconductor element, 8 is a Sn-plated Cu lead, 9 is a polyimide film, and 10 and 10' are areas for connection to an external circuit. . In this case, the Au electrode 7 formed on the semiconductor element 6 and the S
Since the alloy is connected by n-plating 8, its reliability is said to be extremely high. Further, FIG. 3 shows an example in which the semiconductor device shown in FIG. 2 is mounted on a substrate. In Figure 3, the same parts as in Figure 2 are given the same numbers. 11 is a substrate, 12 is a conductor wiring, 13 is a connecting portion with an external circuit, and 14 is an adhesive or solder for adhesively fixing the semiconductor element. In this way, the lead 8 is once formed (referred to as forming) and connected to the conductor wiring 12 in the region 13. If necessary, the semiconductor element 6 is fixed to the substrate 11 using an adhesive 14.
However, in the above example, the leads 8 must be fallen in order to be mounted on the substrate 11, making handling extremely difficult.
このような実状に鑑み、本発明は電極端子の一端は半導
体素子上の電極と接続、他の端は枠体の側面に接着され
た構造とし、上記従来例の問題点を解決することができ
たものである。In view of these circumstances, the present invention has a structure in which one end of the electrode terminal is connected to the electrode on the semiconductor element, and the other end is bonded to the side surface of the frame, thereby solving the problems of the conventional example. It is something that
発明の目的
本発明は半導体素子のレベルで充分機能検査することが
可能で、かつ配線基板への高密度実装が提供することを
目的とする。OBJECTS OF THE INVENTION An object of the present invention is to enable sufficient functional testing at the level of semiconductor elements and to provide high-density mounting on wiring boards.
発明の構成
本発明の枠体の一主面に接着された電極端子の内方向に
突出した端には半導体素子を接続し、他を提供するもの
である。Structure of the Invention According to the present invention, a semiconductor element is connected to an inwardly projecting end of an electrode terminal bonded to one main surface of a frame body, and other features are provided.
実施例の説明 第４図は本発明の一実施例を示す断面図である。Description of examples FIG. 4 is a sectional view showing an embodiment of the present invention.
第４図において２１は半導体素子、２２は枠体、２３は
電極端子、２４は枠体の側面に曲げられ接着された電極
端子、２６は突起電極、２６は樹脂である。In FIG. 4, 21 is a semiconductor element, 22 is a frame, 23 is an electrode terminal, 24 is an electrode terminal bent and bonded to the side surface of the frame, 26 is a protruding electrode, and 26 is a resin.
本実施例では枠体２２はポリイミド樹脂で、電（吹端子
２３は錫メッキされた銅リードである。電極端子２３の
一方の端には半導体素子２１が、全突起電極２５を介し
て接続されている。寸だ、電極端子２３の他の端は枠体
の周縁で曲げられ、２４の如く枠体側面に接着されてい
る。なお、半導体素子２１の上面、下面は樹脂２６で被
覆されている。電極端子２３の端部２４は使用上の都合
により枠体２２の厚さよりも短かくした良が良い。In this embodiment, the frame 22 is made of polyimide resin, and the blown terminal 23 is a tin-plated copper lead. The semiconductor element 21 is connected to one end of the electrode terminal 23 via a fully protruding electrode 25. The other end of the electrode terminal 23 is bent at the periphery of the frame and is bonded to the side surface of the frame as shown at 24.The upper and lower surfaces of the semiconductor element 21 are covered with resin 26. The end portion 24 of the electrode terminal 23 is preferably made shorter than the thickness of the frame 22 for convenience of use.
なお、本発明の実施例の製造工程を第６図により説明す
る。第６図において、第４図と同一箇所には同一番号を
付した。第６図ａはＴＡＢ方式に使用されるキャリヤテ
ープの部分拡大図である。Incidentally, the manufacturing process of the embodiment of the present invention will be explained with reference to FIG. In FIG. 6, the same parts as in FIG. 4 are given the same numbers. FIG. 6a is a partially enlarged view of a carrier tape used in the TAB method.
即ち、絶縁性樹脂２２上に電極端子２３が固定されてい
る。２２は半導体素子を挿入する部分を囲んで枠体を構
成している。Ａ、Ａ’は電極端子の切断場所を示してい
る。次に電極端子の一方に半導体素子２１の突起電極２
５を接合し、樹脂２６で被覆しだ後、Ａ、Ａ’で切断し
たものが、第６図すである。この状態で、電極端子を枠
体の側面に沿って曲げ、固定したものが第６図Ｃである
。That is, the electrode terminal 23 is fixed on the insulating resin 22. Reference numeral 22 constitutes a frame body surrounding a portion into which a semiconductor element is inserted. A and A' indicate the cutting locations of the electrode terminals. Next, the protruding electrode 2 of the semiconductor element 21 is attached to one of the electrode terminals.
5 is joined and coated with resin 26, and then cut at A and A' as shown in FIG. In this state, the electrode terminal is bent and fixed along the side surface of the frame as shown in FIG. 6C.
この場合、電極端子の折り曲げ部２４で外部回路との接
続を行なう。また、第６図Ｃでは電極端子２４が、枠体
２２の厚さとはソ等しい長さとしたが場合によっては短
かくした方が良い。In this case, the connection to the external circuit is made at the bent portion 24 of the electrode terminal. Further, in FIG. 6C, the electrode terminal 24 has a length equal to the thickness of the frame 22, but it may be better to make it shorter depending on the case.
次に本発明の半導体装置の実装例を第６図、第７図を用
いて説明する。Next, an example of mounting the semiconductor device of the present invention will be described with reference to FIGS. 6 and 7.
第６図は本発明の半導体装置を基板に実装した状態を示
す。第６図において６１は基板、６２は導体配線、６３
は半田付は部分、６４は本発明の半導体装置である。半
導体装置６４はその電極端子２３の部分で基板６１上の
導体配線６２に半田付けされる。FIG. 6 shows the semiconductor device of the present invention mounted on a substrate. In FIG. 6, 61 is a substrate, 62 is a conductor wiring, and 63
6 is a soldering part, and 64 is a semiconductor device of the present invention. The semiconductor device 64 is soldered to the conductor wiring 62 on the substrate 61 at its electrode terminal 23 portion.
また、第７図は本発明の半導体装置の第二〇実装置を示
す。第７図において、７１，７２．７３は本発明による
半導体装置、７４は半田接続部分である。なお、半導体
装置７１，７２．７３は第４図に示すものと同じてあり
、各部分は第４図と同一番号を付した。第７図は本発明
の半導体装置を重さねたもので、相互の間は接着剤７６
で接着され、かつ、電極端子２３は所定の箇所７４が半
田付けされる。このような構造は、例えばＩＣメモリー
を多数個使用するときに今後必要となるものである。Further, FIG. 7 shows a twentyth actual device of the semiconductor device of the present invention. In FIG. 7, 71, 72, and 73 are semiconductor devices according to the present invention, and 74 is a solder connection portion. The semiconductor devices 71, 72, and 73 are the same as those shown in FIG. 4, and each part is given the same number as in FIG. FIG. 7 shows stacked semiconductor devices of the present invention, with an adhesive 76 between them.
At the same time, the electrode terminal 23 is soldered at a predetermined location 74. Such a structure will be required in the future, for example, when a large number of IC memories are used.
発明の効果
以」二述べた如く、本発明によれば側面に電極端子を有
する小型・薄型の半導体装置が実現できる上、さらにこ
の状態で機能検査が可能であり、基板に実装した段階で
の歩留りは極めて高い。丑だ本発明の半導体装置は第７
図に示す如く、タテ方向に積層することができ、また相
互のチップ間配線が容易なため、メモリー Ｉ Ｃ等の
三次元ハイブリッド化が可能となる。As described in ``Effects of the Invention'', according to the present invention, it is possible to realize a small and thin semiconductor device having electrode terminals on the side surface, and furthermore, it is possible to perform functional inspection in this state, and it is possible to perform a functional test at the stage of mounting on a board. Yield is extremely high. The semiconductor device of the present invention is the seventh
As shown in the figure, since they can be stacked vertically and wiring between chips is easy, three-dimensional hybridization of memory ICs and the like is possible.
第１図、第２図、第３図は従来の半導体装体の断面図、
第４図は本発明の一実施例の半導体装置の断面図、第５
面はａ、ｂ、ｃ本発明の半導体装置の製造方法の工法断
面図、第６図は本発明の半導体装置の実装例の断面図、
第７図は本発明半導体装置の他の完装例の断面図である
。
２１・・・・・・半導体素子、２２・・・・・・枠体、
２３・・・・・・電極端子、２６・・・・・・樹脂、６
１・・・・・基板、６４゜７１．７２．７３・・・・・
・本発明の半導体装置、６３゜７４・・・・・半田付は
部分、了６・・・・・接着剤。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名−６
−
′０ ト
Ｏし）Figures 1, 2, and 3 are cross-sectional views of conventional semiconductor devices;
FIG. 4 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
Surfaces a, b, and c are cross-sectional views of the manufacturing method of the semiconductor device of the present invention, and FIG. 6 is a cross-sectional view of a mounting example of the semiconductor device of the present invention.
FIG. 7 is a sectional view of another complete example of the semiconductor device of the present invention. 21... Semiconductor element, 22... Frame,
23... Electrode terminal, 26... Resin, 6
1... Board, 64°71.72.73...
・Semiconductor device of the present invention, 63°74... Soldering is done partially, 63... Adhesive. Name of agent: Patent attorney Toshio Nakao and 1 other person-6
-'0
Claims (1)
の内方向に突出した部分の先端には前記枠体の開孔部に
挿入された半導体素子の電極が接続され、かつ前記電極
端子の前記枠体の外方向に突出した部分が前記枠体の外
周で折り曲げられ、枠体側面に固定されたことを特徴と
する半導体装置。 （坤 半導体素子の底面が枠体底面より突出していない
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。 （３）枠体が金属で構成され、かつ全表面が絶縁物で被
覆され／ζことを特徴とする特許請求の範囲第１項記載
の半導体装置。 （４）半導体素子を配置するだめのデバイス孔が開口さ
れた枠体の一生面上に複数本の電極端子が配設され、前
記デバイス孔に突出した前記電極端子の先端と半導体素
子上の電極とを接合する工程と、前記枠体の周縁を越え
て延在する電極端子を所定の位置で切断する工程と、切
断された前記電極端子を前記枠体の周縁部で折り曲げ前
記枠体へ側面に配置する工程を有する半導体装置の製造
方法。[Scope of Claims] (1) At the tip of the inwardly projecting portion of the electrode terminal disposed on the entire surface of the frame, a semiconductor element is inserted into the opening of the frame. What is claimed is: 1. A semiconductor device, to which an electrode is connected, and a portion of the electrode terminal protruding outward from the frame is bent around an outer periphery of the frame and fixed to a side surface of the frame. (Kon) The semiconductor device according to claim 1, characterized in that the bottom surface of the semiconductor element does not protrude from the bottom surface of the frame. (3) The frame is made of metal, and the entire surface is covered with an insulator. A semiconductor device according to claim 1, characterized in that: (4) a plurality of electrode terminals are arranged on the entire surface of a frame in which a device hole for arranging a semiconductor element is opened; a step of joining the tip of the electrode terminal provided and protruding into the device hole with an electrode on the semiconductor element; a step of cutting the electrode terminal extending beyond the periphery of the frame at a predetermined position; A method for manufacturing a semiconductor device, comprising a step of bending the cut electrode terminal at a peripheral edge of the frame and arranging the cut electrode terminal on a side surface of the frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58098351A JPS59222947A (en) | 1983-06-02 | 1983-06-02 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58098351A JPS59222947A (en) | 1983-06-02 | 1983-06-02 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59222947A true JPS59222947A (en) | 1984-12-14 |
| JPH0437585B2 JPH0437585B2 (en) | 1992-06-19 |
Family
ID=14217469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58098351A Granted JPS59222947A (en) | 1983-06-02 | 1983-06-02 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59222947A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62226636A (en) * | 1986-03-28 | 1987-10-05 | Matsushita Electric Ind Co Ltd | Plastic chip carrier |
| JPH01173742A (en) * | 1987-12-28 | 1989-07-10 | Hitachi Ltd | Semiconductor device |
| JPH01309362A (en) * | 1988-06-08 | 1989-12-13 | Hitachi Ltd | Multichip semiconductor device |
| JPH02134859A (en) * | 1988-11-16 | 1990-05-23 | Hitachi Ltd | Multi-chip semiconductor device and manufacture |
| JPH02192745A (en) * | 1989-01-20 | 1990-07-30 | Omron Tateisi Electron Co | Ic module and its manufacture |
| US5587341A (en) * | 1987-06-24 | 1996-12-24 | Hitachi, Ltd. | Process for manufacturing a stacked integrated circuit package |
| WO1998022980A1 (en) * | 1996-11-21 | 1998-05-28 | Hitachi, Ltd. | Semiconductor device and process for manufacturing the same |
| EP0798780A3 (en) * | 1996-03-27 | 2000-09-13 | Oki Electric Industry Co., Ltd. | Semiconductor device, manufacturing method thereof and aggregate type semiconductor device |
| US6984885B1 (en) | 2000-02-10 | 2006-01-10 | Renesas Technology Corp. | Semiconductor device having densely stacked semiconductor chips |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57122559A (en) * | 1980-12-08 | 1982-07-30 | Gao Ges Automation Org | Integrated circuit module support |
-
1983
- 1983-06-02 JP JP58098351A patent/JPS59222947A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57122559A (en) * | 1980-12-08 | 1982-07-30 | Gao Ges Automation Org | Integrated circuit module support |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62226636A (en) * | 1986-03-28 | 1987-10-05 | Matsushita Electric Ind Co Ltd | Plastic chip carrier |
| US6424030B2 (en) | 1987-06-24 | 2002-07-23 | Hitachi, Ltd. | Semiconductor memory module having double-sided stacked memory chip layout |
| US5587341A (en) * | 1987-06-24 | 1996-12-24 | Hitachi, Ltd. | Process for manufacturing a stacked integrated circuit package |
| US5708298A (en) * | 1987-06-24 | 1998-01-13 | Hitachi Ltd. | Semiconductor memory module having double-sided stacked memory chip layout |
| US6693346B2 (en) | 1987-06-24 | 2004-02-17 | Hitachi, Ltd. | Semiconductor memory module having double-sided stacked memory chip layout |
| US5910685A (en) * | 1987-06-24 | 1999-06-08 | Hitachi Ltd. | Semiconductor memory module having double-sided stacked memory chip layout |
| US6521993B2 (en) | 1987-06-24 | 2003-02-18 | Hitachi, Ltd. | Semiconductor memory module having double-sided stacked memory chip layout |
| US6262488B1 (en) | 1987-06-24 | 2001-07-17 | Hitachi Ltd. | Semiconductor memory module having double-sided memory chip layout |
| JPH01173742A (en) * | 1987-12-28 | 1989-07-10 | Hitachi Ltd | Semiconductor device |
| JPH01309362A (en) * | 1988-06-08 | 1989-12-13 | Hitachi Ltd | Multichip semiconductor device |
| JPH02134859A (en) * | 1988-11-16 | 1990-05-23 | Hitachi Ltd | Multi-chip semiconductor device and manufacture |
| JPH02192745A (en) * | 1989-01-20 | 1990-07-30 | Omron Tateisi Electron Co | Ic module and its manufacture |
| US6208021B1 (en) | 1996-03-27 | 2001-03-27 | Oki Electric Industry Co., Ltd. | Semiconductor device, manufacturing method thereof and aggregate type semiconductor device |
| US6403398B2 (en) | 1996-03-27 | 2002-06-11 | Oki Electric Industry Co, Ltd. | Semiconductor device, manufacturing method thereof and aggregate type semiconductor device |
| EP0798780A3 (en) * | 1996-03-27 | 2000-09-13 | Oki Electric Industry Co., Ltd. | Semiconductor device, manufacturing method thereof and aggregate type semiconductor device |
| US6664616B2 (en) | 1996-11-21 | 2003-12-16 | Hitachi, Ltd. | Semiconductor device and manufacturing method thereof |
| WO1998022980A1 (en) * | 1996-11-21 | 1998-05-28 | Hitachi, Ltd. | Semiconductor device and process for manufacturing the same |
| US6759272B2 (en) | 1996-11-21 | 2004-07-06 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
| KR100447313B1 (en) * | 1996-11-21 | 2004-09-07 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and process for manufacturing the same |
| US6984885B1 (en) | 2000-02-10 | 2006-01-10 | Renesas Technology Corp. | Semiconductor device having densely stacked semiconductor chips |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0437585B2 (en) | 1992-06-19 |
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