JP3024517B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3024517B2 JP3024517B2 JP7190868A JP19086895A JP3024517B2 JP 3024517 B2 JP3024517 B2 JP 3024517B2 JP 7190868 A JP7190868 A JP 7190868A JP 19086895 A JP19086895 A JP 19086895A JP 3024517 B2 JP3024517 B2 JP 3024517B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- bump
- recess
- forming
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップサイズの半
導体装置及びその製造方法に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a chip-size semiconductor device and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図４に基づいて従来のチップサイズの半
導体装置の一例について説明する。図は、チップサイズ
の半導体装置を母基板に実装した状態を示す断面図であ
る。但し、概略構成のみを図示することとし、詳細部分
は図示を省略する。図で、１は母基板、２は母基板上に
実装したチップサイズの半導体装置、３は回路（図示省
略）が形成された半導体チップ、４は半導体チップ３の
一方の面にシリコン等で形成されたインナーバンプ、５
は、半導体チップ３、及び、インナーバンプ４の側面部
を封止する樹脂、６は、インナーバンプ４の、樹脂５の
外側に露出した上面部分に接合されたアウターバンプで
ある。アウターバンプ６が母基板１上の配線パターン
（図示省略）に接合されることにより半導体装置２が母
基板１上に実装される。2. Description of the Related Art An example of a conventional semiconductor device having a chip size will be described with reference to FIG. The figure is a cross-sectional view showing a state in which a chip-sized semiconductor device is mounted on a motherboard. However, only the schematic configuration is illustrated, and detailed portions are not illustrated. In the drawing, 1 is a mother substrate, 2 is a chip-sized semiconductor device mounted on the mother substrate, 3 is a semiconductor chip on which a circuit (not shown) is formed, 4 is formed of silicon or the like on one surface of the semiconductor chip 3 Inner bumps, 5
Is a resin that seals the side surfaces of the semiconductor chip 3 and the inner bump 4, and 6 is an outer bump that is joined to the upper surface of the inner bump 4 that is exposed outside the resin 5. The semiconductor device 2 is mounted on the mother substrate 1 by joining the outer bumps 6 to a wiring pattern (not shown) on the mother substrate 1.
【０００３】図５の断面図に基づいて、図４に示した半
導体装置の製造方法の一例について説明する。まず、
（ａ）に示すような、回路（図示省略）を形成した半導
体チップ３の一方の面上に、（ｂ）に示すように、イン
ナーバンプ４を形成する。次に、（ｃ）に示すように、
半導体チップ３及びインナーバンプ４を樹脂５にてモー
ルドする。このとき、インナーバンプ４の上面部分が樹
脂５の表面に露出するようにする。さらに、（ｄ）に示
すように、インナーバンプ４の上面部分にアウターバン
プ６を接合して、超小型のチップサイズの半導体装置を
形成していた。An example of a method for manufacturing the semiconductor device shown in FIG. 4 will be described with reference to the cross-sectional view of FIG. First,
An inner bump 4 is formed on one surface of a semiconductor chip 3 on which a circuit (not shown) is formed as shown in FIG. Next, as shown in (c),
The semiconductor chip 3 and the inner bump 4 are molded with a resin 5. At this time, the upper surface portion of the inner bump 4 is exposed on the surface of the resin 5. Further, as shown in (d), the outer bumps 6 are joined to the upper surface of the inner bumps 4 to form a semiconductor device having a very small chip size.
【０００４】[0004]
【発明が解決しようとする課題】しかし、図４に示した
構造では、図５に示したように、バンプ形成工程として
は、インナーバンプ４を形成する工程と、アウターバン
プ６を形成する工程の２つの工程が必要なため、工程が
長くなるという問題点があった。また、半導体チップ３
及びインナーバンプ４をモールドするための成型金型が
必要であった。However, in the structure shown in FIG. 4, as shown in FIG. 5, the bump forming step includes a step of forming the inner bump 4 and a step of forming the outer bump 6. Since two steps are required, there is a problem that the steps become longer. In addition, the semiconductor chip 3
In addition, a molding die for molding the inner bump 4 was required.
【０００５】本発明は、上記問題点に鑑みなされたもの
で、その目的とするところは、工程削減が図れる超小型
の半導体装置の構造及びその製造方法を提供することに
ある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a structure of a microminiature semiconductor device capable of reducing the number of steps and a method of manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するた
め、請求項１記載の半導体装置は、半導体チップの一主
表面に形成された凹部と、その凹部内に形成された回路
と、その凹部内に形成され、その頭部が前記凹部の外側
に突出するように形成されたバンプと、前記凹部内を封
止する封止樹脂とを備えたことを特徴とするものであ
る。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a concave portion formed on one main surface of a semiconductor chip; a circuit formed in the concave portion; And a sealing resin for sealing the inside of the recess, the bump being formed so that the head protrudes outside the recess.
【０００７】請求項２記載の半導体装置の製造方法は、
半導体ウェハの一主表面に、その深さ寸法が、前記半導
体ウェハに形成されるバンプの高さ寸法より小さい凹部
を形成する工程と、その凹部内に回路を形成する工程
と、前記凹部内に前記バンプを形成する工程と、前記バ
ンプを形成した後、前記凹部内を封止する工程と、封止
工程後のダイシング工程とを備えたことを特徴とするも
のである。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a recess on one main surface of the semiconductor wafer, the depth of which is smaller than the height of a bump formed on the semiconductor wafer; forming a circuit in the recess; The method further includes a step of forming the bump, a step of sealing the inside of the concave portion after forming the bump, and a dicing step after the sealing step.
【０００８】請求項１記載の半導体装置の構造、また
は、請求項２記載の半導体装置の製造方法によれば、バ
ンプ形成工程が１度で済み、成型工程も不要であるた
め、工程削減が図れる。また、半導体装置を超小型に製
造することができるので、半導体チップの電極密度と同
等の密度の高密度実装が可能となる。According to the structure of the semiconductor device according to the first aspect or the method of manufacturing the semiconductor device according to the second aspect, the number of steps can be reduced because only one bump forming step is required and no molding step is required. . In addition, since the semiconductor device can be manufactured in an ultra-small size, high-density mounting at a density equal to the electrode density of the semiconductor chip becomes possible.
【０００９】[0009]
【発明の実施の形態】図１の断面図に基づいて本発明の
半導体装置の一実施形態について説明する。但し、概略
構成のみを図示することとし、詳細部分は図示を省略す
る。図で、半導体装置７は、半導体装置７のパッケージ
を兼ねる略平板状の半導体チップ８と、母基板との接続
のためのバンプ９と、半導体装置７の回路部分を封止す
る封止樹脂１０とを備えている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the semiconductor device according to the present invention will be described with reference to the sectional view of FIG. However, only the schematic configuration is illustrated, and detailed portions are not illustrated. In the figure, a semiconductor device 7 includes a substantially flat semiconductor chip 8 also serving as a package of the semiconductor device 7, bumps 9 for connection to a mother board, and a sealing resin 10 for sealing a circuit portion of the semiconductor device 7. And
【００１０】半導体チップ８の一主表面には凹部８ａが
形成されており、その凹部８ａ内には回路１１（詳細は
図示省略）が形成されている。また、凹部８ａ内の回路
１１の電極部（図示省略）に、共晶半田等で構成される
バンプ９が形成されており、凹部８ａ内は封止樹脂１０
によって封止されている。但し、バンプ９の頭部（上
部）が、封止樹脂１０の表面に露出して、凹部８ａの外
側に突出するように、バンプ９の形状及び凹部８ａの深
さ寸法が設定されている。A concave portion 8a is formed on one main surface of the semiconductor chip 8, and a circuit 11 (details not shown) is formed in the concave portion 8a. A bump 9 made of eutectic solder or the like is formed on an electrode portion (not shown) of the circuit 11 in the concave portion 8a, and a sealing resin 10 is formed in the concave portion 8a.
Is sealed by. However, the shape of the bump 9 and the depth dimension of the concave portion 8a are set so that the head (upper portion) of the bump 9 is exposed on the surface of the sealing resin 10 and protrudes outside the concave portion 8a.
【００１１】図１に示した半導体装置７は、図２に示す
ように、バンプ９を、母基板１２（ガラエポ基板等）上
の配線パターン（図示省略）に接合されて母基板１２上
に実装されている。この場合、凹部８ａの深さ寸法を、
母基板１２上に実装された状態のバンプ９の高さ寸法と
略等しい寸法に設定しておけば、半導体装置７のバンプ
９を形成した側の面を、母基板１２の表面に当接させて
実装することによって、バンプ９の実装高さを所望の高
さに揃えることができ、母基板１２への実装工程の接合
歩留りを向上させることができる。In the semiconductor device 7 shown in FIG. 1, as shown in FIG. 2, the bumps 9 are bonded to a wiring pattern (not shown) on a mother substrate 12 (such as a glass epoxy substrate) and mounted on the mother substrate 12. Have been. In this case, the depth dimension of the recess 8a is
If the height of the bump 9 mounted on the motherboard 12 is set to be substantially equal to the height of the bump 9, the surface of the semiconductor device 7 on which the bump 9 is formed is brought into contact with the surface of the motherboard 12. By mounting the bumps 9, the mounting height of the bumps 9 can be adjusted to a desired height, and the bonding yield in the mounting process on the mother board 12 can be improved.
【００１２】図３の断面図に基づいて、図１に示した半
導体装置の製造方法の一実施形態について説明する。
（ａ）は略平板状の半導体ウェハ１３の断面図である。
まず、（ｂ）に示すように、半導体ウェハ１３の一主表
面に、回路１１を形成するための凹部８ａをエッチング
により複数形成する。次に、（ｃ）に示すように、回路
１１を各凹部８ａ内に形成した後、各回路１１の電極部
（図示省略）にバンプ９を形成する。この場合、バンプ
９の頭部（上部）が、凹部８ａの外側に突出するよう
に、凹部８ａの深さ寸法及びバンプ９の形状を設定して
おく。さらに、（ｄ）に示すように、各凹部８ａの内部
に封止樹脂１０を注入し、加熱して硬化させる。最後
に、（ｅ）に示すように、半導体ウェハ１３をダイシン
グ工程によって個々の半導体チップ８に切り離して半導
体装置７を完成させる。An embodiment of a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the sectional view of FIG.
FIG. 2A is a cross-sectional view of a substantially flat semiconductor wafer 13.
First, as shown in (b), a plurality of recesses 8a for forming the circuits 11 are formed on one main surface of the semiconductor wafer 13 by etching. Next, as shown in (c), after the circuits 11 are formed in the respective recesses 8a, the bumps 9 are formed on the electrode portions (not shown) of the respective circuits 11. In this case, the depth dimension of the concave portion 8a and the shape of the bump 9 are set so that the head (upper portion) of the bump 9 protrudes outside the concave portion 8a. Further, as shown in (d), the sealing resin 10 is injected into each recess 8a, and is cured by heating. Finally, as shown in (e), the semiconductor device 13 is completed by cutting the semiconductor wafer 13 into individual semiconductor chips 8 by a dicing process.
【００１３】[0013]
【発明の効果】請求項１記載の半導体装置、または、請
求項２記載の半導体装置の製造方法によれば、バンプ形
成工程が１回で済み、成型工程も不要となるので、工程
削減が図れる。また、半導体装置を超小型に形成するこ
とができるので、半導体チップの電極密度と同等の密度
の高密度実装が可能となる。さらに、成型金型も不要と
なる。According to the method for manufacturing a semiconductor device according to the first aspect or the method for manufacturing a semiconductor device according to the second aspect, the number of steps can be reduced because only one bump forming step is required and no molding step is required. . In addition, since the semiconductor device can be formed in a very small size, high-density mounting at a density equal to the electrode density of the semiconductor chip is possible. Further, a molding die is not required.
【図１】本発明の半導体装置の一実施形態を示す断面図
である。FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置を母基板に実装した状態を
示す断面図である。FIG. 2 is a cross-sectional view showing a state where the semiconductor device of the present invention is mounted on a mother board.
【図３】本発明の半導体装置の製造方法の一実施形態を
示す断面図である。FIG. 3 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device of the present invention.
【図４】従来の半導体装置の一例を示す断面図である。FIG. 4 is a cross-sectional view illustrating an example of a conventional semiconductor device.
【図５】従来の半導体装置の製造方法の一例を示す断面
図である。FIG. 5 is a cross-sectional view illustrating an example of a conventional method for manufacturing a semiconductor device.
８ 半導体チップ ８ａ 凹部 ９ バンプ １０ 封止樹脂 １１ 回路 １３ 半導体ウェハ Reference Signs List 8 semiconductor chip 8a recess 9 bump 10 sealing resin 11 circuit 13 semiconductor wafer
Claims (2)
部と、その凹部内に形成された回路と、その凹部内に形
成され、その頭部が前記凹部の外側に突出するように形
成されたバンプと、前記凹部内を封止する封止樹脂とを
備えたことを特徴とする半導体装置。1. A recess formed in one main surface of a semiconductor chip, a circuit formed in the recess, a recess formed in the recess, and a head formed to project outside the recess. And a sealing resin for sealing the inside of the concave portion.
法が、前記半導体ウェハに形成されるバンプの高さ寸法
より小さい凹部を形成する工程と、その凹部内に回路を
形成する工程と、前記凹部内に前記バンプを形成する工
程と、前記バンプを形成した後、前記凹部内を封止する
工程と、封止工程後のダイシング工程とを備えたことを
特徴とする半導体装置の製造方法。2. A step of forming, on one main surface of a semiconductor wafer, a recess whose depth dimension is smaller than a height dimension of a bump formed on the semiconductor wafer; and a step of forming a circuit in the recess. Forming a bump in the recess, sealing the inside of the recess after forming the bump, and dicing after the sealing process. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7190868A JP3024517B2 (en) | 1995-07-26 | 1995-07-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7190868A JP3024517B2 (en) | 1995-07-26 | 1995-07-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0945730A JPH0945730A (en) | 1997-02-14 |
| JP3024517B2 true JP3024517B2 (en) | 2000-03-21 |
Family
ID=16265105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7190868A Expired - Fee Related JP3024517B2 (en) | 1995-07-26 | 1995-07-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3024517B2 (en) |
-
1995
- 1995-07-26 JP JP7190868A patent/JP3024517B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0945730A (en) | 1997-02-14 |
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