JPH0462942A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0462942A JPH0462942A JP2173052A JP17305290A JPH0462942A JP H0462942 A JPH0462942 A JP H0462942A JP 2173052 A JP2173052 A JP 2173052A JP 17305290 A JP17305290 A JP 17305290A JP H0462942 A JPH0462942 A JP H0462942A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead
- chip mounting
- mounting
- mounting lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 238000007789 sealing Methods 0.000 claims abstract description 18
- 238000005452 bending Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に表面実装を行う樹脂封
止パッケージ構造の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a resin-sealed package structure for surface mounting.
従来のこの種の半導体装置の一例を第３図の斜視図に示
す。ここではトランジスタで例示してあり、１本のチッ
プ搭載リード１１と、その水平方向の両側に配設した２
本の接続リード１２．１３とを備えている。そして、チ
ップ搭載リード１１に半導体素子（トランジスタ）千ツ
ブ１４を搭載しており、このトランジスタチップ１４と
接続リード１２．１３とを細線ワイヤ１５とで電気接続
し、これらを封止樹脂１６で封止してパッケージを構成
している。An example of a conventional semiconductor device of this type is shown in the perspective view of FIG. Here, a transistor is used as an example, and there is one chip mounting lead 11 and two chips arranged on both sides in the horizontal direction.
The book connection leads 12 and 13 are provided. A semiconductor element (transistor) 14 is mounted on the chip mounting lead 11, and the transistor chip 14 and connection leads 12 and 13 are electrically connected with a thin wire 15, and these are sealed with a sealing resin 16. and configure the package.
なお、各リード１１，１２．１３の他端は封止樹脂１６
から突出され、外部回路への接続用端子部１１ａ、１２
ａ、１３ａとして構成されている。Note that the other end of each lead 11, 12, 13 is sealed with a sealing resin 16.
Terminal portions 11a and 12 for connection to an external circuit protrude from the
a, 13a.
このような従来の半導体装置では、チップ搭載リード１
１の両側の略同−平面上に２本の接続リード１２．１３
を配設しているため、封止樹脂１６の水平方向の面積は
これら３本のり−１”１１，１２゜Ｉ３の面積の和以上
にすることができず、半導体装置の小型化を進める上で
の障害になっている。In such conventional semiconductor devices, the chip mounting lead 1
Two connection leads 12.13 on substantially the same plane on both sides of 1.
As a result, the horizontal area of the sealing resin 16 cannot be greater than the sum of the areas of these three beams - 1" 11, 12° I3, which makes it difficult to miniaturize semiconductor devices. It has become a hindrance.
また、従来この種の半導体装置を表面実装させる場合に
は、各リード１１，１２．１３の端子部１１ａ、１２ａ
、１３ａを封止樹脂１６の底面に沿って同一平面上に配
置する必要があるため、各リード１１，１２．１３をそ
の厚さ方向にクランク状に２回曲げ形成する必要があり
、リートの強度が低下されるとともに、加工工程が多（
なって製造が面倒になるという問題がある。Conventionally, when surface mounting this type of semiconductor device, terminal portions 11a, 12a of each lead 11, 12.
, 13a must be arranged on the same plane along the bottom surface of the sealing resin 16, it is necessary to bend each lead 11, 12, 13 twice in the thickness direction into a crank shape. The strength is reduced and the processing steps are increased (
There is a problem that manufacturing becomes troublesome.
本発明の目的は、半導体装置の小型化を図るとともに、
リード強度を向上させ、かつ製造を容易なものとした半
導体装置を擢供することにある。An object of the present invention is to reduce the size of a semiconductor device, and
An object of the present invention is to provide a semiconductor device that has improved lead strength and is easy to manufacture.
本発明の半導体装置は、半導体チップを搭載するチップ
搭載リードの周囲に配設される接続リドを、その表面が
チップ搭載リードの搭載面に対して垂直方向に向くよう
に配設している。In the semiconductor device of the present invention, the connection lid is disposed around the chip mounting lead on which the semiconductor chip is mounted, and the connection lid is arranged so that the surface thereof faces perpendicularly to the mounting surface of the chip mounting lead.
また、接続リードは、端部を厚さ方向に１回曲げ形成し
てチップ搭載リードの端部と同一平面上に配設している
。Further, the end portion of the connection lead is bent once in the thickness direction and is disposed on the same plane as the end portion of the chip mounting lead.
本発明によれば、各リードを封止する封止樹脂の面積は
、チップ搭載リードの面積と、接続リードの厚さ方向の
面積の和で良く、小型化が促進さる。According to the present invention, the area of the sealing resin that seals each lead may be the sum of the area of the chip mounting lead and the area of the connection lead in the thickness direction, and miniaturization is promoted.
また、接続リードは端部を１回曲げ形成ずろだけである
ため、その強度が向上され、かつ加工を容易に行うこと
ができる。Further, since the connecting lead has only one bending and forming gap at the end, its strength is improved and processing can be easily performed.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の半導体装置の第１実施例の斜視図であ
り、ここでは３端子型の半導体装置、例えばトランジス
タに適用した例を示している。FIG. 1 is a perspective view of a first embodiment of the semiconductor device of the present invention, and here shows an example in which the semiconductor device is applied to a three-terminal type semiconductor device, for example, a transistor.
同図において、１はチップ搭載リードであり、その両側
には２本の接続リード２，３を配設している。ここで、
これら接続リート２，３はチップ搭載リード１と平行に
延設されているが、各接続リード２，３の表面はチップ
搭載り−１１のチップ搭載面に対して垂直方向に向けで
ある。そして、前記チップ搭載リード１のチップ搭載面
にトランジスタチップ４を搭載し、細線ワイヤ５でチッ
プ４の電極４ａと前記各接続リード２．３の表面との電
気接続を行っている。さらに、これらは封止樹脂６で封
止してパッケージを構成している。また、前記各リード
１，２．３の先端は、それぞれ封止樹脂６の一側面から
突出され、かつそれぞれを直角に曲げ形成することで各
接続用端部１ａ２ａ、３ａを同一平面上に配置させてい
る。In the figure, 1 is a chip mounting lead, and two connection leads 2 and 3 are arranged on both sides of the chip mounting lead. here,
These connecting leads 2 and 3 extend parallel to the chip mounting lead 1, but the surface of each connecting lead 2 and 3 is oriented perpendicularly to the chip mounting surface of the chip mounting lead 11. A transistor chip 4 is mounted on the chip mounting surface of the chip mounting lead 1, and electrical connection is made between the electrode 4a of the chip 4 and the surface of each connection lead 2.3 using a thin wire 5. Further, these are sealed with a sealing resin 6 to form a package. Further, the tips of the leads 1, 2.3 each protrude from one side of the sealing resin 6, and are bent at right angles so that the connection ends 1a2a, 3a are arranged on the same plane. I'm letting you do it.
この構成によれば、封止樹脂６の平面面積は、少なくと
もチップ搭載リードＩのチップ搭載面の面積と、２木の
接続リード２．３の厚さ方向の面積の和以上とすればよ
いため、略接続リード２゜３の平面方向の面積分だけ低
減することができ、半導体装置の小型化を促進すること
ができる。また、各リード１．２．３の端部１ａ、２ａ
、３ａは１回曲げ形成するだけで、各端部を封止樹脂６
の一側面に沿って配設し、表面実装を可能とするため、
各リードの強度低下が防止でき、かつ加工を容易に行う
ことができる。According to this configuration, the planar area of the sealing resin 6 need only be at least the sum of the area of the chip mounting surface of the chip mounting lead I and the area in the thickness direction of the two connecting leads 2.3. , can be reduced by approximately the area of the connecting lead 2°3 in the plane direction, and miniaturization of the semiconductor device can be promoted. Also, the ends 1a, 2a of each lead 1.2.3
, 3a only needs to be bent once, and each end is sealed with the sealing resin 6.
It is placed along one side of the board to enable surface mounting.
It is possible to prevent the strength of each lead from decreasing and to facilitate processing.
第２図は本発明の第２実施例の斜視図であり、第１実施
例と等価な部分には同一・符号を付しである。FIG. 2 is a perspective view of a second embodiment of the present invention, in which parts equivalent to those of the first embodiment are given the same reference numerals.
この実施例では、チップ搭載リード１の両側に配設する
接続リード２Ａ、３Ａは、チップ搭載リード１と直交す
る方向に延設し、かつ各面はチップ搭載リード１のチッ
プ搭載面と垂直に向けである。そして、チップ搭載り一
ト１にはトランジスタチップ４を搭載し、その電極４ａ
と各接続リード２Ａ、３Ａとを細線ワイヤ５で電気接続
している。また、これらは封止樹脂６により封止してい
る。In this embodiment, the connection leads 2A and 3A arranged on both sides of the chip mounting lead 1 extend in a direction perpendicular to the chip mounting lead 1, and each surface is perpendicular to the chip mounting surface of the chip mounting lead 1. It is aimed at A transistor chip 4 is mounted on the chip mounting table 1, and its electrode 4a
and each connection lead 2A, 3A are electrically connected by a thin wire 5. Further, these are sealed with a sealing resin 6.
さらに、前記チップ搭載リート１の端部１ａはその厚さ
方向にクランク状に２回曲げ形成して封止樹脂５の底面
に沿うように突出させ、かつ各接続リード２Ａ、３Ａの
各端部は厚さ方向に１回曲げ形成して封止樹脂５の底面
に沿うように突出させ、各端部１ａ、２ａ、３ａが同一
平面上に位置するように構成している。Further, the end portion 1a of the chip mounting REET 1 is bent twice in the thickness direction into a crank shape so as to protrude along the bottom surface of the sealing resin 5, and each end portion of each connection lead 2A, 3A is bent once in the thickness direction to protrude along the bottom surface of the sealing resin 5, and each end portion 1a, 2a, 3a is configured to be located on the same plane.
この構成においても、封止樹脂５の面積は、チップ搭載
リードＩのチップ搭載面の面積乙こ、２木の接続リード
２Ａ、３Ａの厚さ方向の面積を加えた大きさで良く、面
積の低減を図ることができる。In this configuration as well, the area of the sealing resin 5 may be the area of the chip mounting surface of the chip mounting lead I plus the area of the two connection leads 2A and 3A in the thickness direction. It is possible to reduce the
また、チップ搭載リード１は２回曲げ形成しているが、
接続リード２Ａ、３Ａは１回の曲げ形成であるため、リ
ード強度の低減が防止できる。Also, the chip mounting lead 1 is bent twice,
Since the connection leads 2A and 3A are bent only once, reduction in lead strength can be prevented.
以上説明したように本発明は、接続リードを、その表面
がチップ搭載リードの搭載面に対して垂直方向に向くよ
うに配設しているので、これらのリードを封止する封止
樹脂の面積は、チップ搭載リードの面積と接続リードの
厚さ方向の面積の和で良く、半導体装置の小型化を図る
ことができる。As explained above, in the present invention, the connection leads are arranged so that their surfaces face perpendicularly to the mounting surface of the chip mounting leads, so that the area of the sealing resin that seals these leads is reduced. can be the sum of the area of the chip mounting lead and the area of the connection lead in the thickness direction, making it possible to downsize the semiconductor device.
また、接続リードは、端部を厚さ方向に１回曲げ形成し
てチップ搭載リードの端部と同一平面上に配設している
ので、表面実装を可能とするとともに、リードの強度が
向上でき、かつ加工を容易に行うことができる。In addition, the ends of the connection leads are bent once in the thickness direction and placed on the same plane as the ends of the chip-mounted leads, making surface mounting possible and improving the strength of the leads. and can be easily processed.
第１図は本発明の第１実施例の斜視図、第２図は本発明
の第２実施例の斜視図、第３図は従来の半導体装置の斜
視図である。
１．１１・・・チップ搭載リード、
２．３．２Ａ、３Ａ、 １２． １３・・・接続リー
ト、４．１４・・・トランジスタチップ、５，１５・・
・細線。
ワイヤ、６．１６・・・封止樹脂。FIG. 1 is a perspective view of a first embodiment of the invention, FIG. 2 is a perspective view of a second embodiment of the invention, and FIG. 3 is a perspective view of a conventional semiconductor device. 1.11...Chip mounting lead, 2.3.2A, 3A, 12. 13...Connection lead, 4.14...Transistor chip, 5,15...
・Thin lines. Wire, 6.16... Sealing resin.
Claims (1)
チップ搭載リードの周囲に配設されて前記半導体チップ
に対して細線ワイヤで電気接続される接続リードとを備
えて各リードを封止樹脂でパッケージしてなる半導体装
置において、前記接続リードはその表面を前記チップ搭
載リードの搭載面に対して垂直方向に向けて配設したこ
とを特徴とする半導体装置。 ２、接続リードは、端部を厚さ方向に１回曲げ形成して
チップ搭載リードの端部と同一平面上に配設してなる特
許請求の範囲第１項記載の半導体装置。[Claims] 1. Each lead includes a chip mounting lead on which a semiconductor chip is mounted, and a connection lead arranged around the chip mounting lead and electrically connected to the semiconductor chip with a thin wire. 1. A semiconductor device packaged with a sealing resin, wherein the connection lead is disposed with its surface oriented perpendicular to the mounting surface of the chip mounting lead. 2. The semiconductor device according to claim 1, wherein the connection lead is formed by bending the end portion once in the thickness direction and is disposed on the same plane as the end portion of the chip mounting lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2173052A JPH0462942A (en) | 1990-06-30 | 1990-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2173052A JPH0462942A (en) | 1990-06-30 | 1990-06-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0462942A true JPH0462942A (en) | 1992-02-27 |
Family
ID=15953327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2173052A Pending JPH0462942A (en) | 1990-06-30 | 1990-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0462942A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6432745B1 (en) * | 1993-09-30 | 2002-08-13 | Siemens Aktiengesellschaft | Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof |
| US7102215B2 (en) | 1997-07-29 | 2006-09-05 | Osram Gmbh | Surface-mountable light-emitting diode structural element |
-
1990
- 1990-06-30 JP JP2173052A patent/JPH0462942A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6432745B1 (en) * | 1993-09-30 | 2002-08-13 | Siemens Aktiengesellschaft | Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof |
| US6716673B2 (en) | 1993-09-30 | 2004-04-06 | Siemens Aktiengesellschaft | Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof |
| US7005311B2 (en) | 1993-09-30 | 2006-02-28 | Osram Gmbh | Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof |
| US7102212B2 (en) | 1993-09-30 | 2006-09-05 | Osram Gmbh | Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof |
| US7288831B2 (en) | 1993-09-30 | 2007-10-30 | Osram Gmbh | Two-pole SMT miniature housing for semiconductor components and method for the manufacture thereof |
| US7102215B2 (en) | 1997-07-29 | 2006-09-05 | Osram Gmbh | Surface-mountable light-emitting diode structural element |
| US7183632B2 (en) | 1997-07-29 | 2007-02-27 | Osram Gmbh | Surface-mountable light-emitting diode structural element |
| US7508002B2 (en) | 1997-07-29 | 2009-03-24 | Osram Gmbh | Surface-mountable light-emitting diode structural element |
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