JP3107648B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3107648B2 JP3107648B2 JP15928692A JP15928692A JP3107648B2 JP 3107648 B2 JP3107648 B2 JP 3107648B2 JP 15928692 A JP15928692 A JP 15928692A JP 15928692 A JP15928692 A JP 15928692A JP 3107648 B2 JP3107648 B2 JP 3107648B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- hole
- conductor
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は基板上に高密度実装する
ことができる半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be mounted on a substrate at high density.
【０００２】[0002]
【従来の技術】図３は従来のＤＩＰ型半導体装置を示す
斜視図であり、図４はこのＤＩＰ型半導体装置を基板上
に実装した場合の側面図である。図において、１は入出
力端子２を２方向に設置したＤＩＰ（デュアル・インラ
イン・パッケージ）型に代表される挿入形の半導体装置
である。2. Description of the Related Art FIG. 3 is a perspective view showing a conventional DIP type semiconductor device, and FIG. 4 is a side view when the DIP type semiconductor device is mounted on a substrate. In the figure, reference numeral 1 denotes an insertion type semiconductor device represented by a DIP (dual in-line package) type in which input / output terminals 2 are installed in two directions.
【０００３】このＤＩＰ型半導体装置１の入出力端子２
を基板３の図示せぬスルーホールに挿入し、半田で接合
するものである。The input / output terminal 2 of this DIP type semiconductor device 1
Is inserted into a through hole (not shown) of the substrate 3 and joined with solder.
【０００４】図５は従来のＱＦＰ型半導体装置を示す斜
視図であり、図６はこのＱＦＰ型半導体装置を基板に実
装した場合の側面図である。図において、４は入出力端
子５を４方向に設置したＱＦＰ（クワッド・フラット・
パッケージ）型に代表される表面実装型の半導体装置で
ある。FIG. 5 is a perspective view showing a conventional QFP type semiconductor device, and FIG. 6 is a side view when the QFP type semiconductor device is mounted on a substrate. In the figure, reference numeral 4 denotes a QFP (Quad Flat
This is a surface-mount type semiconductor device represented by a package type.
【０００５】このＱＦＰ型半導体装置４を基板６に搭載
し、その入出力端子５を基板６の表面の電極部に半田で
接合するものである。The QFP type semiconductor device 4 is mounted on a substrate 6, and its input / output terminals 5 are joined to electrodes on the surface of the substrate 6 by soldering.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記構
成の半導体装置、特にＤＩＰ型半導体装置では、基板に
スルーホールを設けなければならないため、スルーホー
ルの部分には基板の配線パターンを設けることができな
い。However, in the semiconductor device having the above-described structure, in particular, in a DIP type semiconductor device, a through hole must be provided in the substrate, so that the wiring pattern of the substrate cannot be provided in the portion of the through hole. .
【０００７】また、ＱＦＰ型半導体装置では、入出力端
子が同一ピッチの場合、入出力端子数を増やすと、ＱＦ
Ｐ型半導体装置の樹脂筺体の寸法が大きくなる。In a QFP type semiconductor device, when input / output terminals have the same pitch, if the number of input / output terminals is increased, QF
The size of the resin housing of the P-type semiconductor device increases.
【０００８】このように、ＤＩＰ型半導体装置およびＱ
ＦＰ型半導体装置のいずれの入出力端子の設け方でも、
基板への高密度実装という点から満足できるものが得ら
れないという問題点があった。As described above, the DIP type semiconductor device and the Q
Regardless of how to provide the input / output terminals of the FP type semiconductor device,
There was a problem that a satisfactory product could not be obtained in terms of high-density mounting on a substrate.
【０００９】本発明は、以上述べた基板上への高密度実
装が満足できないという問題点を除去するため、半導体
装置の筺体の平面内に、入出力端子を設置する優れた半
導体装置を提供することを目的とする。The present invention provides an excellent semiconductor device in which input / output terminals are provided in a plane of a housing of the semiconductor device in order to eliminate the above-mentioned problem that high-density mounting on a substrate cannot be satisfied. The purpose is to:
【００１０】[0010]
【課題を解決するための手段】本発明に係る半導体装置
は、半導体装置の筺体上面または下面に凹部を設け、こ
の凹部に入出力端子を設置するものである。According to the present invention, there is provided a semiconductor device in which a recess is provided on an upper surface or a lower surface of a housing of a semiconductor device, and an input / output terminal is provided in the recess.
【００１１】[0011]
【作用】本発明は基板への実装を高密度に行なうことが
できる。According to the present invention, mounting on a substrate can be performed at a high density.
【００１２】[0012]
【実施例】図１は本発明に係る半導体装置の一実施例を
示す断面図であり、図２はこの半導体装置を基板に実装
した場合の一部破断した側面図である。図において、７
は半導体素子、８はこの半導体素子７を固着したダイパ
ット、９は一方の面に導体１０を配線し、他方の面に導
体１１を配線し、この導体１０と導体１１をスルーホー
ル１２で接続した絶縁板、１３は樹脂モールド、１４は
半導体素子７の電極と導体１０を接続する金属細線、１
５は一端が導体１１に接続し、他端が半導体装置の筺体
下面凹部１６に配置した入出力端子である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a partially cutaway side view showing a case where the semiconductor device is mounted on a substrate. In the figure, 7
Is a semiconductor element, 8 is a die pad to which the semiconductor element 7 is fixed, 9 is a conductor 10 on one surface, a conductor 11 is wired on the other surface, and the conductor 10 and the conductor 11 are connected by a through hole 12. An insulating plate, 13 is a resin mold, 14 is a thin metal wire connecting the electrode of the semiconductor element 7 and the conductor 10, 1
Reference numeral 5 denotes an input / output terminal having one end connected to the conductor 11 and the other end arranged in the recess 16 on the lower surface of the housing of the semiconductor device.
【００１３】この構成による半導体装置を基板３上に実
装する場合、図２に示すように、その入出力端子１５
は、筺体下面凹部１６に設けたので、接合材料１７によ
り、基板３上の配線パターン（図示せず）に接合するこ
とができる。When the semiconductor device having this configuration is mounted on the substrate 3, as shown in FIG.
Is provided in the recess 16 on the lower surface of the housing, so that it can be joined to a wiring pattern (not shown) on the substrate 3 by the joining material 17.
【００１４】このように、半導体素子の筺体下面に設け
た凹部１６の面積全てを入出力端子として使用すること
ができ、基板への高密度実装を行なうことができる。As described above, the entire area of the recess 16 provided on the lower surface of the housing of the semiconductor element can be used as an input / output terminal, and high-density mounting on a substrate can be performed.
【００１５】なお、上述の実施例では、入出力端子を、
半導体装置の筺体の下面に設置した場合を示したが、こ
れに限定せず、筺体の上面に設けてもよいことはもちろ
んである。In the above embodiment, the input / output terminals are
Although the case where the semiconductor device is installed on the lower surface of the housing of the semiconductor device has been described, it is needless to say that the semiconductor device may be provided on the upper surface of the housing.
【００１６】[0016]
【発明の効果】以上詳細に説明したように、本発明に係
る半導体装置によれば、入出力端子を半導体装置の筺体
の上面または下面に設置したので、基板への実装密度を
上げることができる効果がある。As described in detail above, according to the semiconductor device of the present invention, since the input / output terminals are provided on the upper surface or the lower surface of the housing of the semiconductor device, the mounting density on the substrate can be increased. effective.
【図１】本発明に係る半導体装置の一実施例を示す断面
図である。FIG. 1 is a sectional view showing one embodiment of a semiconductor device according to the present invention.
【図２】図１の半導体装置を基板に実装した場合を示す
一部破断した側面図である。FIG. 2 is a partially broken side view showing a case where the semiconductor device of FIG. 1 is mounted on a substrate.
【図３】従来のＤＩＰ型半導体装置を示す斜視図であ
る。FIG. 3 is a perspective view showing a conventional DIP type semiconductor device.
【図４】図３の半導体装置を基板に実装した場合を示す
側面図である。FIG. 4 is a side view showing a case where the semiconductor device of FIG. 3 is mounted on a substrate.
【図５】従来のＱＦＰ型半導体装置を示す斜視図であ
る。FIG. 5 is a perspective view showing a conventional QFP type semiconductor device.
【図６】図５の半導体装置を基板に実装した場合を示す
側面図である。FIG. 6 is a side view showing a case where the semiconductor device of FIG. 5 is mounted on a substrate.
７ 半導体素子 ８ ダイパット ９ 絶縁板 １０，１１ 導体 １２ スルーホール １３ 樹脂モールド １５ 入出力端子 Reference Signs List 7 semiconductor element 8 die pad 9 insulating plate 10, 11 conductor 12 through hole 13 resin mold 15 input / output terminal
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭51−132765（ＪＰ，Ａ) 特開 平１−145891（ＪＰ，Ａ) 特開 昭59−228739（ＪＰ，Ａ) 特開 昭63−143852（ＪＰ，Ａ) 実開 昭61−70938（ＪＰ，Ｕ) 国際公開92／20097（ＷＯ，Ａ１) ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-51-132765 (JP, A) JP-A-1-145891 (JP, A) JP-A-59-228739 (JP, A) JP-A-63-1988 143852 (JP, A) Japanese Utility Model Showa 61-70938 (JP, U) International Publication No. 92/20097 (WO, A1)
Claims (1)
し該主表面に前記半導体素子が搭載される基板とを備え
た半導体装置であって、 前記基板の主表面に形成され、前記半導体素子と電気的
に接続される第１の導体配線と、 前記基板の主表面から前記基板の裏表面へと貫通する貫
通穴と、 前記貫通穴と該貫通穴の周辺領域とを覆うように前記基
板の裏表面に延在する第２の導体配線と、 前記貫通穴の内部に形成された導体であり、前記第１の
導体配線と前記第２の導体配線とを電気的に接続する導
体と、前記半導体素子及び前記基板を封止し 、前記貫通穴の周
辺領域上にある前記第２の導体配線の一部を露出する開
口部を有する封止樹脂と、 前記開口部内に形成され、前記第２の導体配線の一部と
電気的に接続する外部電極とを有することを特徴とする
半導体装置。 And 1. A semiconductor device, a semiconductor device that includes a substrate on which the semiconductor element to the main surface and a main surface and the back surface is mounted, is formed on the main surface of said substrate, said A first conductor wiring electrically connected to the semiconductor element, a through hole penetrating from a main surface of the substrate to a back surface of the substrate, and a region surrounding the through hole and a peripheral region of the through hole. A second conductor wiring extending on the back surface of the substrate, a conductor formed inside the through hole, and electrically connecting the first conductor wiring and the second conductor wiring; And a sealing resin that seals the semiconductor element and the substrate and has an opening exposing a part of the second conductive wiring on a peripheral region of the through hole; and a sealing resin formed in the opening, An external electrode electrically connected to a part of the second conductor wiring; Wherein a.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15928692A JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
| JP2000129910A JP3589941B2 (en) | 1992-06-18 | 2000-04-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15928692A JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000129910A Division JP3589941B2 (en) | 1992-06-18 | 2000-04-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH065732A JPH065732A (en) | 1994-01-14 |
| JP3107648B2 true JP3107648B2 (en) | 2000-11-13 |
Family
ID=15690482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15928692A Expired - Fee Related JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3107648B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010125958A1 (en) | 2009-04-28 | 2010-11-04 | 三菱電機株式会社 | Command generation device |
-
1992
- 1992-06-18 JP JP15928692A patent/JP3107648B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH065732A (en) | 1994-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1662565A3 (en) | Semiconductor package | |
| JP2509027B2 (en) | Semiconductor device | |
| US5841183A (en) | Chip resistor having insulating body with a continuous resistance layer and semiconductor device | |
| JPH11214606A (en) | Resin molded semiconductor device and lead frame | |
| JP3107648B2 (en) | Semiconductor device | |
| JP2902918B2 (en) | Surface mount type semiconductor device | |
| JP2798108B2 (en) | Hybrid integrated circuit device | |
| JP3150560B2 (en) | Semiconductor device | |
| JPS6334968A (en) | Lead frame for semiconductor device | |
| JP2524482B2 (en) | QFP structure semiconductor device | |
| JPS6097654A (en) | Sealed type semiconductor device | |
| JP2000323625A (en) | Semiconductor device | |
| JP2577916B2 (en) | High frequency semiconductor device and lead frame for the device | |
| JP3576228B2 (en) | Surface mount type semiconductor device | |
| JPH08279593A (en) | Semiconductor device for high-density mounting | |
| JPH0974158A (en) | Package for high-power hybrid integrated circuit | |
| JPS61144834A (en) | Resin-sealed semiconductor device | |
| JP3153185B2 (en) | Semiconductor device | |
| JP2670505B2 (en) | Substrate for mounting electronic components | |
| JP3396948B2 (en) | Resin molded semiconductor device | |
| JPH01270256A (en) | Semiconductor device | |
| JP2944247B2 (en) | Semiconductor device | |
| JPH077111A (en) | Semiconductor device surface mounting package | |
| JPS63307762A (en) | Semiconductor device | |
| JPH0648875Y2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20000822 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070908 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080908 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080908 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090908 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090908 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100908 Year of fee payment: 10 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100908 Year of fee payment: 10 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100908 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110908 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |