JPH08279593A - Semiconductor device for high-density mounting - Google Patents
Semiconductor device for high-density mountingInfo
- Publication number
- JPH08279593A JPH08279593A JP7878695A JP7878695A JPH08279593A JP H08279593 A JPH08279593 A JP H08279593A JP 7878695 A JP7878695 A JP 7878695A JP 7878695 A JP7878695 A JP 7878695A JP H08279593 A JPH08279593 A JP H08279593A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- semiconductor
- chip
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路チップ
をパッケージングした半導体装置に関し、特にパッケー
ジに電子部品を搭載して接続できる半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor integrated circuit chip is packaged, and more particularly to a semiconductor device in which electronic parts can be mounted and connected to the package.
【０００２】[0002]
【従来の技術】従来、半導体装置を実装したプリント基
板の実装密度を向上するため、一部の電子部品を半導体
装置のパッケージの表面に実装して、パッケージ内部の
半導体集積回路チップ（ＩＣチップ）とその電子部品を
接続するものが特開平３−４２８６４号公報に開示され
ている。2. Description of the Related Art Conventionally, in order to improve the mounting density of a printed circuit board on which a semiconductor device is mounted, some electronic components are mounted on the surface of the package of the semiconductor device and a semiconductor integrated circuit chip (IC chip) inside the package is mounted. Japanese Patent Application Laid-Open No. 3-42864 discloses a device for connecting the electronic component and the electronic component.
【０００３】図７はその公報に開示された従来の半導体
装置の斜視図、図８は図７の断面図である。但し、図８
には図７に使用される電子部品６９が省略されている。
図において、半導体装置本体５０は、パッケージ（樹脂
封止体）６１の中に半導体素子６０を封止している。半
導体素子６０は、半導体装置本体の外部端子６２と金属
細線６３によって接続される。電極６４は外部端子６２
とパッケージ６１の中で接続され、パッケージ表面に対
して垂直に延び、パッケージ上面に突き出ている。パッ
ケージ６１の上面には電子部品６７、６８と６９が実装
される。その実装のために、パッケージ６１の上面に配
線パターン６５、６６が形成され、その配線パターンに
パッケージ上面から突き出た電極６４が接続される。す
なわち、電子部品６７、６８および６９は、半導体素子
６０に電極６４および配線パターン６５、６６を介して
接続される。このように、半導体装置に他の電子部品が
実装されることで、プリント基板実装の高密度化が実現
される。FIG. 7 is a perspective view of a conventional semiconductor device disclosed in that publication, and FIG. 8 is a sectional view of FIG. However, FIG.
The electronic component 69 used in FIG. 7 is omitted.
In the figure, the semiconductor device body 50 has a semiconductor element 60 sealed in a package (resin sealing body) 61. The semiconductor element 60 is connected to an external terminal 62 of the semiconductor device body by a thin metal wire 63. The electrode 64 is the external terminal 62
Are connected in the package 61, extend perpendicular to the package surface, and project from the package upper surface. Electronic components 67, 68 and 69 are mounted on the upper surface of the package 61. For the mounting, wiring patterns 65 and 66 are formed on the upper surface of the package 61, and the electrodes 64 protruding from the upper surface of the package are connected to the wiring pattern. That is, the electronic components 67, 68 and 69 are connected to the semiconductor element 60 via the electrodes 64 and the wiring patterns 65 and 66. As described above, by mounting other electronic components on the semiconductor device, high density mounting on the printed circuit board is realized.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前述し
た従来の半導体装置では、電子部品とパッケージ内の半
導体部品とを接続するために、パッケージを貫通する電
極を外部電極に接続する必要があり、またパッケージ上
面に配線パターンを形成しなければならないため、製造
工程が多くなり高価になるという欠点がある。However, in the above-mentioned conventional semiconductor device, in order to connect the electronic component and the semiconductor component in the package, it is necessary to connect the electrode penetrating the package to the external electrode. Since a wiring pattern has to be formed on the upper surface of the package, there is a drawback that the number of manufacturing processes increases and the cost becomes high.
【０００５】本発明の目的は、部品点数を少なくし、パ
ッケージ上に配線パターンを形成する必要がない半導体
装置を提供することにある。An object of the present invention is to provide a semiconductor device in which the number of parts is reduced and it is not necessary to form a wiring pattern on a package.
【０００６】[0006]
【課題を解決するための手段】本発明によれば、半導体
ＩＣチップを絶縁材でパッケージングした半導体装置に
おいて、半導体ＩＣチップに接続するリードフレームか
ら分岐した電極が、半導体ＩＣチップを封止したパッケ
ージの上面に平行に延びて上部電極を形成したことを特
徴とする半導体装置が得られる。According to the present invention, in a semiconductor device in which a semiconductor IC chip is packaged with an insulating material, electrodes branched from a lead frame connected to the semiconductor IC chip seal the semiconductor IC chip. A semiconductor device is obtained in which an upper electrode is formed so as to extend parallel to the upper surface of the package.
【０００７】[0007]
【実施例】次に、本発明の実施例について図面を参照し
て詳細に説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
【０００８】図１は本発明の実施例の半導体装置の平面
図、図２は図１の半導体装置をプリント基板に実装した
ときのＡＡ線断面図である。図において、半導体装置１
００は、半導体ＩＣチップ（以下、単にＩＣチップと称
す）２をパッケージ１の中心に封止したものである。半
導体ＩＣチップ２は、複数のリードフレーム３にボンデ
ィングワイヤ９によって接続される。各リードフレーム
３は、パッケージ１の内部ボンディングワイヤ９との接
続部分からパッケージ側面に向かって水平に延びるボン
ディング部分３１と、パッケージ１の側面を突き出てか
ら折れ曲がった外部端子６とが連続して形成されてい
る。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA when the semiconductor device of FIG. 1 is mounted on a printed board. In the figure, the semiconductor device 1
00 is a semiconductor IC chip (hereinafter, simply referred to as an IC chip) 2 sealed in the center of the package 1. The semiconductor IC chip 2 is connected to the lead frames 3 by bonding wires 9. Each lead frame 3 is formed by continuously forming a bonding portion 31 that extends horizontally from the connection portion with the internal bonding wire 9 of the package 1 toward the package side surface, and an external terminal 6 that protrudes from the side surface of the package 1 and is then bent. Has been done.
【０００９】複数のリードフレーム３のうち、リードフ
レーム３ａ，３ｂ，３ｃ，３ｄ，３ｅ，３ｆの６本は、
上部電極４と一体に形成されている。図２及び図３に示
すように、上部電極４は、パッケージ１の内部でリード
フレーム３ａ〜３ｆの途中から分岐しかつパッケージ上
面１０に向かって延びた分岐部３０の延長上に形成さ
れ、途中で折れ曲がってパッケージ上面１０に平行に延
びている。Of the plurality of lead frames 3, the six lead frames 3a, 3b, 3c, 3d, 3e and 3f are
It is formed integrally with the upper electrode 4. As shown in FIGS. 2 and 3, the upper electrode 4 is formed on the extension of the branch portion 30 that branches from the middle of the lead frames 3 a to 3 f inside the package 1 and extends toward the package upper surface 10. Is bent and extends parallel to the package upper surface 10.
【００１０】図２に示すように、上部電極４には電子部
品２０の部品端子２２が半田づけによって接続される。
また、リードフレーム３の外部端子６は、プリント基板
５の配線パターン７に接続される。したがって、電子部
品２０は、ＩＣチップ２とプリント基板５の配線パター
ン７とに接続される。As shown in FIG. 2, the component terminal 22 of the electronic component 20 is connected to the upper electrode 4 by soldering.
The external terminals 6 of the lead frame 3 are connected to the wiring pattern 7 of the printed board 5. Therefore, the electronic component 20 is connected to the IC chip 2 and the wiring pattern 7 of the printed board 5.
【００１１】本実施例によれば、リードフレーム３ａ〜
３ｆとパッケージ上面に平行な上部電極４とが一体に形
成されるので、半導体装置１００の部品数は増えず、製
造工程が増えない。また、上部電極４は、パッケージ上
面に平行に延びるので、上部電極自体が配線パターンの
役割を果たす。半導体装置１００を製造する場合、パッ
ケージ１の下半分にＩＣチップ２と複数のリードフレー
ム３を載せてボンディングワイヤ９で接続し、その後、
パッケージ１の上半分を形成して封止する。パッケージ
１は耐熱性の樹脂でモールドによって形成するのが望ま
しいが、樹脂以外の絶縁材でもよい。リードフレーム３
とＩＣチップ２との接続は、ボンディングワイヤ９によ
る接続に限定せず、他の接続方法でも良い。上部電極４
は、リードフレーム３のうちの６本に形成されたが、他
のどのリードフレームに形成されても良い。According to this embodiment, the lead frames 3a ...
Since 3f and the upper electrode 4 parallel to the upper surface of the package are integrally formed, the number of parts of the semiconductor device 100 does not increase and the number of manufacturing steps does not increase. Further, since the upper electrode 4 extends parallel to the upper surface of the package, the upper electrode itself serves as a wiring pattern. When manufacturing the semiconductor device 100, the IC chip 2 and the plurality of lead frames 3 are placed on the lower half of the package 1 and connected by the bonding wires 9, and then,
The upper half of the package 1 is formed and sealed. The package 1 is preferably formed of a heat-resistant resin by molding, but an insulating material other than resin may be used. Lead frame 3
The connection between the IC chip 2 and the IC chip 2 is not limited to the connection by the bonding wire 9, and another connection method may be used. Upper electrode 4
Are formed on six of the lead frames 3, but may be formed on any other lead frame.
【００１２】図４は本発明の第２の実施例の半導体装置
の平面図、図５は図４の半導体装置をプリント基板に実
装したときのＢＢ断面図である。図において、半導体装
置２００が第１の実施例の半導体装置１００と違う点
は、半導体装置２００ではパッケージ上面１０に電子部
品２１の端子２３を挿入する端子挿入受け穴１８が形成
されていることと、そのパッケージ挿入受け穴１８に対
応して上部電極４に、図６に示すように端子挿入穴８が
形成されていることである。電子部品２１の端子２３
は、上部電極４の部品挿入穴８からパッケージ１の端子
挿入受け穴１８に挿入され、その後半田つけされる。FIG. 4 is a plan view of a semiconductor device according to a second embodiment of the present invention, and FIG. 5 is a BB sectional view when the semiconductor device of FIG. 4 is mounted on a printed board. In the figure, the semiconductor device 200 differs from the semiconductor device 100 of the first embodiment in that the semiconductor device 200 has a terminal insertion receiving hole 18 for inserting the terminal 23 of the electronic component 21 in the package upper surface 10. The terminal insertion hole 8 is formed in the upper electrode 4 corresponding to the package insertion receiving hole 18 as shown in FIG. Terminal 23 of electronic component 21
Is inserted from the component insertion hole 8 of the upper electrode 4 into the terminal insertion receiving hole 18 of the package 1 and then soldered.
【００１３】以上説明した実施例では、１つのリードフ
レームに対し１つの上部電極しか一体に形成されていな
いが、１つのリードフレームに複数の上部電極が一体に
形成されても良い。In the embodiment described above, only one upper electrode is integrally formed for one lead frame, but a plurality of upper electrodes may be integrally formed for one lead frame.
【００１４】[0014]
【発明の効果】以上説明したように、本発明によれば、
半導体装置内部の半導体ＩＣチップに接続するリードフ
レームから分岐した上部電極が、半導体ＩＣチップを封
止したパッケージの上面に平行に延びて形成されるの
で、半導体装置の部品点数を増やさずに高密度実装がで
き、また、上部電極に電子部品を直接に実装できるの
で、パッケージ上に電子部品を実装するための配線パタ
ーンの形成が不要になるという効果がある。As described above, according to the present invention,
Since the upper electrode branched from the lead frame connected to the semiconductor IC chip inside the semiconductor device is formed to extend parallel to the upper surface of the package encapsulating the semiconductor IC chip, the high density can be achieved without increasing the number of parts of the semiconductor device. Since the mounting can be performed and the electronic component can be directly mounted on the upper electrode, there is an effect that it is not necessary to form a wiring pattern for mounting the electronic component on the package.
【図１】本発明の第１の実施例の半導体装置を示す図で
ある。FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.
【図２】図１の半導体装置をプリント基板に実装したと
きのＡＡ断面図である。2 is a cross-sectional view taken along the line AA of the semiconductor device of FIG. 1 when mounted on a printed circuit board.
【図３】図２の半導体装置のリードフレームの接合を示
す拡大斜視図である。FIG. 3 is an enlarged perspective view showing the joining of the lead frames of the semiconductor device of FIG.
【図４】本発明の第２の実施例の半導体装置を示す図で
ある。FIG. 4 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
【図５】図４の半導体装置をプリント基板に実装したと
きのＢＢ断面図である。5 is a BB sectional view when the semiconductor device of FIG. 4 is mounted on a printed board.
【図６】図５の半導体装置のリードフレームの接合を示
す拡大斜視図である。6 is an enlarged perspective view showing the joining of the lead frames of the semiconductor device of FIG.
【図７】従来の半導体装置を示す斜視図である。FIG. 7 is a perspective view showing a conventional semiconductor device.
【図８】図７の半導体装置の断面図である。8 is a cross-sectional view of the semiconductor device of FIG.
１００ 半導体装置 １ パッケージ ２ 半導体ＩＣチップ ３ リードフレーム ４ 上部電極 100 semiconductor device 1 package 2 semiconductor IC chip 3 lead frame 4 upper electrode
Claims (3)
ングした半導体装置において、前記半導体ＩＣチップに
接続するリードフレームから分岐した電極が、前記半導
体ＩＣチップを封止した絶縁材のパッケージの上面に平
行に延びて上部電極を形成したことを特徴とする半導体
装置。1. In a semiconductor device in which a semiconductor IC chip is packaged with an insulating material, an electrode branched from a lead frame connected to the semiconductor IC chip is parallel to an upper surface of an insulating material package encapsulating the semiconductor IC chip. A semiconductor device, wherein an upper electrode is formed so as to extend to the.
は、電子部品の端子を挿入するための端子挿入穴が形成
されたことを特徴とする請求項１に記載された半導体装
置。2. The semiconductor device according to claim 1, wherein a terminal insertion hole for inserting a terminal of an electronic component is formed in the upper electrode and the upper surface of the package.
チップと導電線によって接続され、一端がパッケージの
外部に出て外部端子を形成したことを特徴とする請求項
１及び２に記載された半導体装置。3. The lead frame is the semiconductor IC.
3. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the chip by a conductive wire, and one end of the chip is exposed to the outside of the package to form an external terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7878695A JPH08279593A (en) | 1995-04-04 | 1995-04-04 | Semiconductor device for high-density mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7878695A JPH08279593A (en) | 1995-04-04 | 1995-04-04 | Semiconductor device for high-density mounting |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08279593A true JPH08279593A (en) | 1996-10-22 |
Family
ID=13671575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7878695A Pending JPH08279593A (en) | 1995-04-04 | 1995-04-04 | Semiconductor device for high-density mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08279593A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777795B2 (en) | 2001-09-12 | 2004-08-17 | Hitachi, Ltd. | Semiconductor integrated circuit modules, manufacturing methods and usage thereof |
| KR100668811B1 (en) * | 2000-10-06 | 2007-01-17 | 주식회사 하이닉스반도체 | Stack package |
| WO2007139132A1 (en) * | 2006-05-31 | 2007-12-06 | Toshihiko Mizukami | Semiconductor device |
| JP2012195502A (en) * | 2011-03-17 | 2012-10-11 | Yazaki Corp | Terminal structure for module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6355448B2 (en) * | 1981-12-02 | 1988-11-02 | Diesel Kiki Co | |
| JPH06350025A (en) * | 1993-06-08 | 1994-12-22 | Toshiba Corp | Semiconductor device |
-
1995
- 1995-04-04 JP JP7878695A patent/JPH08279593A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6355448B2 (en) * | 1981-12-02 | 1988-11-02 | Diesel Kiki Co | |
| JPH06350025A (en) * | 1993-06-08 | 1994-12-22 | Toshiba Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100668811B1 (en) * | 2000-10-06 | 2007-01-17 | 주식회사 하이닉스반도체 | Stack package |
| US6777795B2 (en) | 2001-09-12 | 2004-08-17 | Hitachi, Ltd. | Semiconductor integrated circuit modules, manufacturing methods and usage thereof |
| WO2007139132A1 (en) * | 2006-05-31 | 2007-12-06 | Toshihiko Mizukami | Semiconductor device |
| JP2012195502A (en) * | 2011-03-17 | 2012-10-11 | Yazaki Corp | Terminal structure for module |
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