JP3589941B2 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP3589941B2 JP3589941B2 JP2000129910A JP2000129910A JP3589941B2 JP 3589941 B2 JP3589941 B2 JP 3589941B2 JP 2000129910 A JP2000129910 A JP 2000129910A JP 2000129910 A JP2000129910 A JP 2000129910A JP 3589941 B2 JP3589941 B2 JP 3589941B2
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- JP
- Japan
- Prior art keywords
- semiconductor device
- terminals
- substrate
- semiconductor element
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Description
【0001】
【発明の属する技術分野】
本発明は基板上に高密度実装することができる半導体装置に関するものである。
【0002】
【従来技術】
図3は従来のDIP型半導体装置を示す斜視図であり、図4はこのDIP型半導体装置を基板上に実装した場合の側面図である。図において、1は、入出力端子2を2方向に設置したDIP(デュアル・インライン・パッケージ)型に代表される挿入形の半導体装置である。
【0003】
このDIP型半導体装置1の入出力端子2を基板3の図示せぬスルーホールに挿入し、半田で接合するものである。
【0004】
図5は従来のQFP型半導体装置を示す斜視図であり、図6はこのQFP型半導体装置を基板に実装した場合の側面図である。図において、4は入出力端子5を4方向に設置したQFP(クワッド・フラット・パッケージ)型に代表される表面実装型の半導体装置である。
【0005】
このQFP型半導体装置4を基板6に搭載し、その入出力端子5を基板6の表面の電極部に半田で接合するものである。
【0006】
【発明が解決しようとする課題】
しかしながら、上記構成の半導体装置、特にDIP型半導体装置では、基板にスルーホールを設けなければならないため、スルーホールの部分には基板の配線パターンを設けることができない。
【0007】
また、QFP型半導体装置では、入出力端子が同一ピッチの場合、入出力端子数を増やすと、QFP型半導体装置の樹脂筐体の寸法が大きくなる。
【0008】
このように、DIP型半導体装置およびQFP型半導体装置のいずれの入出力端子の設け方でも、基板への高密度実装という点から満足できるものが得られないという問題点があった。
【0009】
本発明は、以上述べた基板上への高密度実装が満足できないという問題点を除去するため、半導体装置の筐体の平面内に、入出力端子を設置する優れた半導体装置を提供することを目的とする。
【0010】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。
【0011】
すなわち、本発明の半導体装置は、半導体素子(7)と、前記半導体素子(7)を支持する部材(9)と、表面に、底面(18)と側面(19)とを持つ凹部(16)を有し、前記半導体素子(7)及び前記部材(9)を覆う封止樹脂(13)と、前記凹部(16)の前記底面(18)にて前記封止樹脂(13)から露出するように形成された複数の端子(15)と、を有するものとし、前記複数の端子(15)はそれぞれが前記部材(9)を介して半導体素子(7)に電気的に接続され、前記凹部(16)の前記底面(18)に設けられた複数の前記端子(15)の各々は前記凹部(16)の前記側面(19)から所定間隔離れて設けられているようにしたものである。
【0012】
上記の手段によれば、基板上への高密度実装が満足できる半導体装置を提供することができる。
【0013】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、本発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付与し、その繰り返しの説明は省略する。
【0014】
図1及び図2は、本発明の実施の形態の半導体装置に係わる図である。図1は本発明の実施の形態の半導体装置の構造を示し、図2は本発明の実施の形態の半導体装置を基板に実装した場合の一部破断した側面図である。
【0015】
本発明の実施の形態の半導体装置は、半導体素子7と、半導体装置7を固着するダイパット8と、一方の面に導体10を配線し、他方の面に導体11を配線し、この導体10と導体11とをスルーホール12で接続した絶縁板9と、樹脂モールド13と、半導体素子7の電極と導体10とを接続する金属細線14と、一端が導体11に接続し、他端が半導体装置の筐体下面凹部16に配置した入出力端子15とにより構成される。
【0016】
この構成による半導体装置を基板3上に実装する場合、図2に示すように、その入出力端子15は、筐体下面凹部16に設けたので、接合材料17により、基板3上の配線パターン(図示せず)に接合することができる。
【0017】
このように、半導体素子の筐体下面に設けた凹部16の面積すべてを入出力端子として使用することができ、基板への高密度実装を行うことができる。
【0018】
以上本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
【0019】
特に、上述の実施の形態において、入出力端子を、半導体装置の筐体の下面に設置した場合を示したが、これに限定されず、筐体の上面に設けても良いことはもちろんである。
【0020】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。
【0021】
本発明の半導体装置によれば、入出力端子としての複数の端子を半導体装置の筐体としての封止樹脂の上面または下面に設置したので、基板への実装密度を上げることができる効果がある。さらに、複数の端子の各々を封止樹脂の凹部の側面から所定間隔離れて設けるものとしたことにより、以下の効果が期待できるものである。
(1) 凹部の側面部分によって水分の侵入を抑えることができ、複数の端子に対するレイアウトの自由度を損なうことなく、実装状態において底面に設けられた複数の端子が水分により腐食することを低減することができる。
(2) 実装基板実装する際にパッケージと実装基板との熱膨張率の差による応力を端子と樹脂との間の間隔により吸収することが可能となり、熱膨張で端子が損傷を受ける可能性を低減することが可能となる。
(3) 端子数の増加に伴う複数の端子のレイアウトを変更するに際して、凹部の底面でレイアウトすることで、レイアウト変更前と後とで封止樹脂の全体形状やサイズの変更が伴わないことから、共通の金型を用いて樹脂封止する場合でも、端子に対する自由なレイアウトを可能となる。
(4) 凹部の底面内にて複数の端子が露出した構成であることから、実装する基板にスルーホールを設ける必要もない。
(5) 半導体装置と実装する基板との電気的な接続部分(例えば、図2における接合材料17にて電気的な接続をしている部分)を、封止樹脂に凹部を設けて、凹部の側面により電気的な接続部分に対して外部からの衝撃が直接与えられることを防ぐことができ、実装時の電気的な接続状態を安定して維持できる。
【図面の簡単な説明】
【図1】本発明の実施の形態の半導体装置を示す断面図である。
【図2】図1の半導体装置を基板に実装した場合を示す一部破断した側面図である。
【図3】従来のDIP型半導体装置を示す斜視図である。
【図4】図3の半導体装置を基板に実装した場合を示す側面図である。
【図5】従来のQFP型半導体装置を示す斜視図である。
【図6】図5の半導体装置を基板に実装した場合を示す側面図である。
【符号の説明】
7 半導体素子
8 ダイパッド
9 絶縁板
10,11 導体
12 スルーホール
13 樹脂モールド
15 入出力端子
16 凹部
18 底面
19 側面 [0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device that can be mounted on a substrate at high density.
[0002]
[Prior art]
FIG. 3 is a perspective view showing a conventional DIP type semiconductor device, and FIG. 4 is a side view when this DIP type semiconductor device is mounted on a substrate. In the figure,
[0003]
The input / output terminal 2 of the DIP
[0004]
FIG. 5 is a perspective view showing a conventional QFP type semiconductor device, and FIG. 6 is a side view when the QFP type semiconductor device is mounted on a substrate. In the figure, reference numeral 4 denotes a surface-mounted semiconductor device typified by a QFP (quad flat package) in which input /
[0005]
The QFP type semiconductor device 4 is mounted on a
[0006]
[Problems to be solved by the invention]
However, in the semiconductor device having the above configuration, particularly a DIP type semiconductor device, a through-hole must be provided in the substrate, so that a wiring pattern of the substrate cannot be provided in the portion of the through-hole.
[0007]
In the QFP semiconductor device, when the input / output terminals have the same pitch, if the number of input / output terminals is increased, the size of the resin housing of the QFP semiconductor device increases.
[0008]
As described above, there has been a problem that any method of providing the input / output terminals of the DIP type semiconductor device and the QFP type semiconductor device does not provide a satisfactory device in terms of high-density mounting on a substrate.
[0009]
The present invention provides an excellent semiconductor device in which input / output terminals are provided in a plane of a housing of the semiconductor device in order to eliminate the above-mentioned problem that high-density mounting on a substrate cannot be satisfied. Aim.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0011]
That is, the semiconductor device of the present invention includes a semiconductor element (7), with a member (9) for supporting the semiconductor device (7), on the surface, a bottom surface (18) and side (19) recesses with a (16) has the semiconductor element (7) and said member (9) covering the sealing resin (13), so as to expose from said sealing resin (13) at said bottom surface (18) of the recess (16) And a plurality of terminals (15) formed on the semiconductor element (7) via the member (9), and the plurality of terminals (15) are electrically connected to the semiconductor element (7) through the member (9). Each of the plurality of terminals (15) provided on the bottom surface (18) of (16) is provided at a predetermined distance from the side surface (19) of the concave portion (16).
[0012]
According to the above means, it is possible to provide a semiconductor device that can satisfy high-density mounting on a substrate.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are given the same reference numerals, and their repeated description will be omitted.
[0014]
1 and 2 are diagrams related to a semiconductor device according to an embodiment of the present invention. FIG. 1 shows a structure of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a partially cutaway side view when the semiconductor device of the embodiment of the present invention is mounted on a substrate.
[0015]
The semiconductor device according to the embodiment of the present invention includes a
[0016]
When the semiconductor device having this configuration is mounted on the
[0017]
As described above, the entire area of the
[0018]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say.
[0019]
In particular, in the above-described embodiment, the case where the input / output terminals are provided on the lower surface of the housing of the semiconductor device is described. However, the present invention is not limited to this, and the input / output terminals may be provided on the upper surface of the housing. .
[0020]
【The invention's effect】
The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
[0021]
According to the semiconductor device of the present invention, since the plurality of terminals as input / output terminals are provided on the upper surface or the lower surface of the sealing resin as the housing of the semiconductor device, the mounting density on the substrate can be increased. . Furthermore, the following effects can be expected by providing each of the plurality of terminals at a predetermined distance from the side surface of the concave portion of the sealing resin.
(1) Intrusion of moisture can be suppressed by the side surface portion of the concave portion, and the corrosion of the plurality of terminals provided on the bottom surface in the mounted state by moisture is reduced without impairing the degree of freedom of layout for the plurality of terminals. be able to.
(2) When mounting the mounting board, it is possible to absorb the stress due to the difference in the coefficient of thermal expansion between the package and the mounting board by the distance between the terminal and the resin, thereby reducing the possibility of the terminal being damaged by the thermal expansion. It becomes possible to reduce.
(3) When the layout of a plurality of terminals is changed with an increase in the number of terminals, the layout is performed on the bottom surface of the concave portion, so that the entire shape and size of the sealing resin do not change before and after the layout change. In addition, even when resin sealing is performed using a common mold, a free layout for terminals can be realized.
(4) Since a plurality of terminals are exposed in the bottom surface of the concave portion, it is not necessary to provide a through-hole in the board to be mounted.
(5) The electrical connection between the semiconductor device and the substrate to be mounted (for example, the portion electrically connected by the
[Brief description of the drawings]
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a partially broken side view showing a case where the semiconductor device of FIG. 1 is mounted on a substrate.
FIG. 3 is a perspective view showing a conventional DIP type semiconductor device.
FIG. 4 is a side view showing a case where the semiconductor device of FIG. 3 is mounted on a substrate.
FIG. 5 is a perspective view showing a conventional QFP type semiconductor device.
FIG. 6 is a side view showing a case where the semiconductor device of FIG. 5 is mounted on a substrate.
[Explanation of symbols]
7
16 recesses
18 bottom
19 sides
Claims (2)
前記半導体素子を支持する部材と、
表面に、底面と側面とを持つ凹部を有し、前記半導体素子及び前記部材を覆う封止樹脂と、
前記凹部の前記底面にて前記封止樹脂から露出するように形成された複数の端子とを有し、
前記複数の端子はそれぞれが前記部材を介して半導体素子に電気的に接続され、前記凹部の前記底面に設けられた複数の前記端子の各々は前記凹部の前記側面から所定間隔離れて設けられていることを特徴とする半導体装置。A semiconductor element;
A member for supporting the semiconductor element,
On the surface, having a recess having a bottom surface and side surfaces, a sealing resin covering the semiconductor element and the member,
A plurality of terminals formed so as to be exposed from the sealing resin at the bottom surface of the concave portion ,
Each of the plurality of terminals is electrically connected to the semiconductor element via the member, and each of the plurality of terminals provided on the bottom surface of the recess is provided at a predetermined distance from the side surface of the recess. A semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000129910A JP3589941B2 (en) | 1992-06-18 | 2000-04-28 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15928692A JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
JP2000129910A JP3589941B2 (en) | 1992-06-18 | 2000-04-28 | Semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP15928692A Division JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
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JP2000323625A JP2000323625A (en) | 2000-11-24 |
JP3589941B2 true JP3589941B2 (en) | 2004-11-17 |
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JP2000129910A Expired - Fee Related JP3589941B2 (en) | 1992-06-18 | 2000-04-28 | Semiconductor device |
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CN107484350A (en) * | 2017-09-14 | 2017-12-15 | 中国电子科技集团公司第十三研究所 | Microwave device and its assembly method |
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